From owner-freebsd-mips@FreeBSD.ORG Mon Jul 12 11:07:04 2010 Return-Path: Delivered-To: freebsd-mips@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 6056A106567E for ; Mon, 12 Jul 2010 11:07:04 +0000 (UTC) (envelope-from owner-bugmaster@FreeBSD.org) Received: from freefall.freebsd.org (freefall.freebsd.org [IPv6:2001:4f8:fff6::28]) by mx1.freebsd.org (Postfix) with ESMTP id 355278FC12 for ; Mon, 12 Jul 2010 11:07:04 +0000 (UTC) Received: from freefall.freebsd.org (localhost [127.0.0.1]) by freefall.freebsd.org (8.14.4/8.14.4) with ESMTP id o6CB74mi094066 for ; Mon, 12 Jul 2010 11:07:04 GMT (envelope-from owner-bugmaster@FreeBSD.org) Received: (from gnats@localhost) by freefall.freebsd.org (8.14.4/8.14.4/Submit) id o6CB7301094064 for freebsd-mips@FreeBSD.org; Mon, 12 Jul 2010 11:07:03 GMT (envelope-from owner-bugmaster@FreeBSD.org) Date: Mon, 12 Jul 2010 11:07:03 GMT Message-Id: <201007121107.o6CB7301094064@freefall.freebsd.org> X-Authentication-Warning: freefall.freebsd.org: gnats set sender to owner-bugmaster@FreeBSD.org using -f From: FreeBSD bugmaster To: freebsd-mips@FreeBSD.org Cc: Subject: Current problem reports assigned to freebsd-mips@FreeBSD.org X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Jul 2010 11:07:04 -0000 Note: to view an individual PR, use: http://www.freebsd.org/cgi/query-pr.cgi?pr=(number). The following is a listing of current problems submitted by FreeBSD users. These represent problem reports covering all versions including experimental development code and obsolete releases. S Tracker Resp. Description -------------------------------------------------------------------------------- o misc/147471 mips [includes] [patch] whitespace discrepancy in sys/mips/ 1 problem total. From owner-freebsd-mips@FreeBSD.ORG Thu Jul 15 12:36:01 2010 Return-Path: Delivered-To: mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id BFE1A106566C; Thu, 15 Jul 2010 12:36:01 +0000 (UTC) (envelope-from tinderbox@freebsd.org) Received: from freebsd-current.sentex.ca (freebsd-current.sentex.ca [64.7.128.98]) by mx1.freebsd.org (Postfix) with ESMTP id 77BDC8FC1D; Thu, 15 Jul 2010 12:35:59 +0000 (UTC) Received: from freebsd-current.sentex.ca (localhost [127.0.0.1]) by freebsd-current.sentex.ca (8.14.4/8.14.3) with ESMTP id o6FCZwZE086835; Thu, 15 Jul 2010 08:35:58 -0400 (EDT) (envelope-from tinderbox@freebsd.org) Received: (from tinderbox@localhost) by freebsd-current.sentex.ca (8.14.4/8.14.3/Submit) id o6FCZvG3086813; Thu, 15 Jul 2010 12:35:57 GMT (envelope-from tinderbox@freebsd.org) Date: Thu, 15 Jul 2010 12:35:57 GMT Message-Id: <201007151235.o6FCZvG3086813@freebsd-current.sentex.ca> X-Authentication-Warning: freebsd-current.sentex.ca: tinderbox set sender to FreeBSD Tinderbox using -f Sender: FreeBSD Tinderbox From: FreeBSD Tinderbox To: FreeBSD Tinderbox , , Precedence: bulk Cc: Subject: [head tinderbox] failure on mips/mips X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Jul 2010 12:36:01 -0000 TB --- 2010-07-15 12:35:16 - tinderbox 2.6 running on freebsd-current.sentex.ca TB --- 2010-07-15 12:35:16 - starting HEAD tinderbox run for mips/mips TB --- 2010-07-15 12:35:16 - cleaning the object tree TB --- 2010-07-15 12:35:28 - cvsupping the source tree TB --- 2010-07-15 12:35:28 - /usr/bin/csup -z -r 3 -g -L 1 -h cvsup.sentex.ca /tinderbox/HEAD/mips/mips/supfile TB --- 2010-07-15 12:35:57 - building world TB --- 2010-07-15 12:35:57 - MAKEOBJDIRPREFIX=/obj TB --- 2010-07-15 12:35:57 - PATH=/usr/bin:/usr/sbin:/bin:/sbin TB --- 2010-07-15 12:35:57 - TARGET=mips TB --- 2010-07-15 12:35:57 - TARGET_ARCH=mips TB --- 2010-07-15 12:35:57 - TZ=UTC TB --- 2010-07-15 12:35:57 - __MAKE_CONF=/dev/null TB --- 2010-07-15 12:35:57 - cd /src TB --- 2010-07-15 12:35:57 - /usr/bin/make -B buildworld "/src/Makefile.inc1", line 1484: ERROR: kernel config file not found. *** Error code 1 Stop in /src. TB --- 2010-07-15 12:35:57 - WARNING: /usr/bin/make returned exit code 1 TB --- 2010-07-15 12:35:57 - ERROR: failed to build world TB --- 2010-07-15 12:35:57 - 2.39 user 10.01 system 41.80 real http://tinderbox.freebsd.org/tinderbox-head-HEAD-mips-mips.full From owner-freebsd-mips@FreeBSD.ORG Thu Jul 15 22:22:31 2010 Return-Path: Delivered-To: mips@FreeBSD.ORG Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 00C401065672 for ; Thu, 15 Jul 2010 22:22:31 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id A43558FC14 for ; Thu, 15 Jul 2010 22:22:30 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by harmony.bsdimp.com (8.14.3/8.14.1) with ESMTP id o6FMJ5WC088237 for ; Thu, 15 Jul 2010 16:19:05 -0600 (MDT) (envelope-from imp@bsdimp.com) Date: Thu, 15 Jul 2010 16:19:26 -0600 (MDT) Message-Id: <20100715.161926.175946041864758761.imp@bsdimp.com> To: mips@FreeBSD.ORG From: "M. Warner Losh" X-Mailer: Mew version 6.3 on Emacs 22.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cc: Subject: Review X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Jul 2010 22:22:31 -0000 OK. Please find enclosed a minor cleanup diff for assembler files. It moves ITLBNOPFIX and HAZARD_DELAY into a common header, as well as replacing MIPS_CPU_NOP_DELAY with HAZARD_DELAY. The only real change is increasing the number of nops in a few places from 4 to 5. This is in preparation for making these (a) much shorter and (b) optimizing for specific CPUs... mips32/mips64 define ssnop to deal with the super-scaler effects (so ITLBNOPFIX can be shorter), and mips32r2 and mips64r2 have eh, which can help with HAZARD_DELAY. The latter will need some careful study of the docs to make sure that the proper number of instructions are executed (which is why I'm not doing it yet :). The former is just shuffling deck chairs, so should be invisible to people. Comments? Warner Index: include/asm.h =================================================================== --- include/asm.h (revision 209963) +++ include/asm.h (working copy) @@ -843,4 +843,18 @@ #define _JB_SIGMASK 13 +/* + * Various macros for dealing with TLB hazards + * (a) why so many? + * (b) when to use? + * (c) why not used everywhere? + */ +/* + * Assume that w alaways need nops to escape CP0 hazard + * TODO: Make hazard delays configurable. Stuck with 5 cycles on the moment + * For more info on CP0 hazards see Chapter 7 (p.99) of "MIPS32 Architecture + * For Programmers Volume III: The MIPS32 Privileged Resource Architecture" + */ +#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop; +#define HAZARD_DELAY nop;nop;nop;nop;nop; #endif /* !_MACHINE_ASM_H_ */ Index: mips/tlb.S =================================================================== --- mips/tlb.S (revision 209963) +++ mips/tlb.S (working copy) @@ -97,14 +97,6 @@ .set mips3 #endif -#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop; - -/* - * FREEBSD_DEVELOPERS_FIXME - * Some MIPS CPU may need delays using nops between executing CP0 Instructions - */ -#define MIPS_CPU_NOP_DELAY nop;nop;nop;nop; - /*-------------------------------------------------------------------------- * * Mips_TLBWriteIndexed(unsigned index, tlb *tlb); @@ -134,9 +126,9 @@ mtc0 a0, COP_0_TLB_INDEX # Set the index. _MTC0 a2, COP_0_TLB_PG_MASK # Set up entry mask. _MTC0 a3, COP_0_TLB_HI # Set up entry high. - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbwi # Write the TLB - MIPS_CPU_NOP_DELAY + HAZARD_DELAY _MTC0 t0, COP_0_TLB_HI # Restore the PID. nop @@ -252,9 +244,9 @@ _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid addu t1, t1, 1 # Increment index. addu v0, v0, 8 * 1024 - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbwi # Write the TLB entry. - MIPS_CPU_NOP_DELAY + HAZARD_DELAY bne t1, a0, 1b nop _MTC0 t0, COP_0_TLB_HI # Restore the PID @@ -288,9 +280,9 @@ _MFC0 t0, COP_0_TLB_HI # Get current PID mfc0 t3, COP_0_TLB_PG_MASK # Save current pgMask _MTC0 a0, COP_0_TLB_HI # look for addr & PID - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbp # Probe for the entry. - MIPS_CPU_NOP_DELAY + HAZARD_DELAY mfc0 v0, COP_0_TLB_INDEX # See what we got li t1, MIPS_KSEG0_START bltz v0, 1f # index < 0 => !found @@ -305,9 +297,9 @@ _MTC0 zero, COP_0_TLB_LO0 # Zero out low entry. _MTC0 zero, COP_0_TLB_LO1 # Zero out low entry. - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbwi - MIPS_CPU_NOP_DELAY + HAZARD_DELAY 1: _MTC0 t0, COP_0_TLB_HI # restore PID mtc0 t3, COP_0_TLB_PG_MASK # Restore pgMask @@ -341,7 +333,7 @@ _MFC0 t0, COP_0_TLB_HI # Save current PID _MTC0 a0, COP_0_TLB_HI # Init high reg and a2, a1, PTE_G # Copy global bit - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbp # Probe for the entry. _SLL a1, a1, WIRED_SHIFT _SRL a1, a1, WIRED_SHIFT @@ -351,12 +343,12 @@ # EVEN nop bltz v0, 1f # index < 0 => !found - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbr # update, read entry first - MIPS_CPU_NOP_DELAY + HAZARD_DELAY _MTC0 a1, COP_0_TLB_LO0 # init low reg0. - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbwi # update slot found b 4f nop @@ -365,23 +357,23 @@ _MTC0 a0, COP_0_TLB_HI # init high reg. _MTC0 a1, COP_0_TLB_LO0 # init low reg0. _MTC0 a2, COP_0_TLB_LO1 # init low reg1. - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbwr # enter into a random slot - MIPS_CPU_NOP_DELAY + HAZARD_DELAY b 4f nop # ODD 2: nop bltz v0, 3f # index < 0 => !found - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbr # read the entry first - MIPS_CPU_NOP_DELAY + HAZARD_DELAY _MTC0 a1, COP_0_TLB_LO1 # init low reg1. - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbwi # update slot found - MIPS_CPU_NOP_DELAY + HAZARD_DELAY b 4f nop 3: @@ -389,11 +381,11 @@ _MTC0 a0, COP_0_TLB_HI # init high reg. _MTC0 a2, COP_0_TLB_LO0 # init low reg0. _MTC0 a1, COP_0_TLB_LO1 # init low reg1. - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbwr # enter into a random slot 4: # Make shure pipeline - MIPS_CPU_NOP_DELAY + HAZARD_DELAY _MTC0 t0, COP_0_TLB_HI # restore PID mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX @@ -422,15 +414,15 @@ _MFC0 t0, COP_0_TLB_HI # Get current PID mtc0 a0, COP_0_TLB_INDEX # Set the index register - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbr # Read from the TLB - MIPS_CPU_NOP_DELAY + HAZARD_DELAY mfc0 t2, COP_0_TLB_PG_MASK # fetch the hi entry _MFC0 t3, COP_0_TLB_HI # fetch the hi entry _MFC0 ta0, COP_0_TLB_LO0 # See what we got _MFC0 ta1, COP_0_TLB_LO1 # See what we got _MTC0 t0, COP_0_TLB_HI # restore PID - MIPS_CPU_NOP_DELAY + HAZARD_DELAY mtc0 v1, COP_0_STATUS_REG # Restore the status register ITLBNOPFIX sw t2, 0(a1) @@ -491,9 +483,9 @@ # do {} while (t1 < t2) 1: mtc0 t1, COP_0_TLB_INDEX # set index - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbr # obtain an entry - MIPS_CPU_NOP_DELAY + HAZARD_DELAY _MFC0 a0, COP_0_TLB_LO1 and a0, a0, PTE_G # check to see it has G bit bnez a0, 2f @@ -503,7 +495,7 @@ _MTC0 zero, COP_0_TLB_LO0 # zero out entryLo0 _MTC0 zero, COP_0_TLB_LO1 # zero out entryLo1 mtc0 zero, COP_0_TLB_PG_MASK # zero out mask entry - MIPS_CPU_NOP_DELAY + HAZARD_DELAY tlbwi # invalidate the TLB entry 2: addu t1, t1, 1 @@ -513,7 +505,7 @@ _MTC0 ta0, COP_0_TLB_HI # restore PID mtc0 t3, COP_0_TLB_PG_MASK # restore pgMask - MIPS_CPU_NOP_DELAY + HAZARD_DELAY mtc0 v1, COP_0_STATUS_REG # restore status register j ra # new ASID will be set soon nop Index: mips/exception.S =================================================================== --- mips/exception.S (revision 209963) +++ mips/exception.S (working copy) @@ -80,15 +80,6 @@ */ #define INTRCNT_COUNT 128 -/* - * Assume that w alaways need nops to escape CP0 hazard - * TODO: Make hazard delays configurable. Stuck with 5 cycles on the moment - * For more info on CP0 hazards see Chapter 7 (p.99) of "MIPS32 Architecture - * For Programmers Volume III: The MIPS32 Privileged Resource Architecture" - */ -#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop; -#define HAZARD_DELAY nop;nop;nop;nop;nop; - /* Pointer size and mask for n64 */ #if defined(__mips_n64) #define PTRSHIFT 3 Index: mips/swtch.S =================================================================== --- mips/swtch.S (revision 209963) +++ mips/swtch.S (working copy) @@ -67,17 +67,6 @@ .set noreorder # Noreorder is default style! -/* - * FREEBSD_DEVELOPERS_FIXME - * Some MIPS CPU may need delays using nops between executing CP0 Instructions - */ - -#if 1 -#define HAZARD_DELAY nop ; nop ; nop ; nop -#else -#define HAZARD_DELAY -#endif - #define SAVE_U_PCB_REG(reg, offs, base) \ REG_S reg, U_PCB_REGS + (SZREG * offs) (base) @@ -102,8 +91,6 @@ #define RESTORE_U_PCB_CONTEXT(reg, offs, base) \ REG_L reg, U_PCB_CONTEXT + (SZREG * offs) (base) -#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop; - /* * Setup for and return to user. */ Index: mips/support.S =================================================================== --- mips/support.S (revision 209963) +++ mips/support.S (working copy) @@ -1351,8 +1351,6 @@ #endif /* DDB */ #endif /* DDB || DEBUG */ -#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop; - .text LEAF(breakpoint) break BREAK_SOVER_VAL From owner-freebsd-mips@FreeBSD.ORG Fri Jul 16 03:47:55 2010 Return-Path: Delivered-To: mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id BD4D81065672; Fri, 16 Jul 2010 03:47:55 +0000 (UTC) (envelope-from tinderbox@freebsd.org) Received: from freebsd-current.sentex.ca (freebsd-current.sentex.ca [64.7.128.98]) by mx1.freebsd.org (Postfix) with ESMTP id 612058FC08; Fri, 16 Jul 2010 03:47:55 +0000 (UTC) Received: from freebsd-current.sentex.ca (localhost [127.0.0.1]) by freebsd-current.sentex.ca (8.14.4/8.14.3) with ESMTP id o6G3lsSv089985; Thu, 15 Jul 2010 23:47:54 -0400 (EDT) (envelope-from tinderbox@freebsd.org) Received: (from tinderbox@localhost) by freebsd-current.sentex.ca (8.14.4/8.14.3/Submit) id o6G3lsqW089969; Fri, 16 Jul 2010 03:47:54 GMT (envelope-from tinderbox@freebsd.org) Date: Fri, 16 Jul 2010 03:47:54 GMT Message-Id: <201007160347.o6G3lsqW089969@freebsd-current.sentex.ca> X-Authentication-Warning: freebsd-current.sentex.ca: tinderbox set sender to FreeBSD Tinderbox using -f Sender: FreeBSD Tinderbox From: FreeBSD Tinderbox To: FreeBSD Tinderbox , , Precedence: bulk Cc: Subject: [head tinderbox] failure on mips/mips X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Jul 2010 03:47:55 -0000 TB --- 2010-07-16 03:20:35 - tinderbox 2.6 running on freebsd-current.sentex.ca TB --- 2010-07-16 03:20:35 - starting HEAD tinderbox run for mips/mips TB --- 2010-07-16 03:20:35 - cleaning the object tree TB --- 2010-07-16 03:20:35 - cvsupping the source tree TB --- 2010-07-16 03:20:35 - /usr/bin/csup -z -r 3 -g -L 1 -h cvsup.sentex.ca /tinderbox/HEAD/mips/mips/supfile TB --- 2010-07-16 03:21:09 - building world TB --- 2010-07-16 03:21:09 - MAKEOBJDIRPREFIX=/obj TB --- 2010-07-16 03:21:09 - PATH=/usr/bin:/usr/sbin:/bin:/sbin TB --- 2010-07-16 03:21:09 - TARGET=mips TB --- 2010-07-16 03:21:09 - TARGET_ARCH=mips TB --- 2010-07-16 03:21:09 - TZ=UTC TB --- 2010-07-16 03:21:09 - __MAKE_CONF=/dev/null TB --- 2010-07-16 03:21:09 - cd /src TB --- 2010-07-16 03:21:09 - /usr/bin/make -B buildworld >>> World build started on Fri Jul 16 03:21:10 UTC 2010 >>> Rebuilding the temporary build tree >>> stage 1.1: legacy release compatibility shims >>> stage 1.2: bootstrap tools >>> stage 2.1: cleaning up the object tree >>> stage 2.2: rebuilding the object tree >>> stage 2.3: build tools >>> stage 3: cross tools >>> stage 4.1: building includes >>> stage 4.2: building libraries [...] ===> lib/libalias/modules/cuseeme (all) cc -O -pipe -EL -G0 -std=gnu99 -Wsystem-headers -Werror -Wno-pointer-sign -c /src/lib/libalias/modules/cuseeme/../../../../sys/netinet/libalias/alias_cuseeme.c cc1: warnings being treated as errors In file included from /src/lib/libalias/modules/cuseeme/../../../../sys/netinet/libalias/alias_sctp.h:83, from /src/lib/libalias/modules/cuseeme/../../../../sys/netinet/libalias/alias_local.h:63, from /src/lib/libalias/modules/cuseeme/../../../../sys/netinet/libalias/alias_cuseeme.c:52: /obj/mips.mips/src/tmp/usr/include/machine/cpu.h: In function 'get_cyclecount': /obj/mips.mips/src/tmp/usr/include/machine/cpu.h:84: warning: implicit declaration of function 'mips_rd_count' *** Error code 1 Stop in /src/lib/libalias/modules/cuseeme. *** Error code 1 Stop in /src/lib/libalias/modules. *** Error code 1 Stop in /src/lib/libalias. *** Error code 1 Stop in /src/lib. *** Error code 1 Stop in /src. *** Error code 1 Stop in /src. *** Error code 1 Stop in /src. *** Error code 1 Stop in /src. TB --- 2010-07-16 03:47:54 - WARNING: /usr/bin/make returned exit code 1 TB --- 2010-07-16 03:47:54 - ERROR: failed to build world TB --- 2010-07-16 03:47:54 - 1129.48 user 289.05 system 1638.48 real http://tinderbox.freebsd.org/tinderbox-head-HEAD-mips-mips.full From owner-freebsd-mips@FreeBSD.ORG Fri Jul 16 04:37:16 2010 Return-Path: Delivered-To: mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 1E3661065670 for ; Fri, 16 Jul 2010 04:37:16 +0000 (UTC) (envelope-from c.jayachandran@gmail.com) Received: from mail-vw0-f54.google.com (mail-vw0-f54.google.com [209.85.212.54]) by mx1.freebsd.org (Postfix) with ESMTP id C85FD8FC15 for ; Fri, 16 Jul 2010 04:37:15 +0000 (UTC) Received: by vws19 with SMTP id 19so2563967vws.13 for ; Thu, 15 Jul 2010 21:37:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=83tKAvSiOJsk8Q5sp8jvQ1EEw2ys5oDAeCQ88nnBMxs=; b=Yfvf1b4qXDyWTWSguNpwrhL1W9lzVdHzNk2dF7NPPcrHnjPxXjsyKsgRqFyE9ECiII VUe1LXf1PuW6Y3/5zTQ9cRaLboNE8xqLALBUDx859ncM2u0VuC41QK7LBq383fw+JtJE 3eu9JEjS77pAVkpSLFGin/qWxnUmguoi8cYJI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=XXuXZ71nceLgzgKj+25JkJENG2HpVi+Ekkp8umhxcjcJdzIT7362grc6jqCRpfhOy5 yGrWtrLh/wqTEEAbXMcZVsSfFmk4m0zaGVA8z6GcvVf6O+TV0IUGa1+KvouAqIssIl5s 1jbD28Xipyr5+B698ENMXzT5Eq0pXCiWZNyIw= MIME-Version: 1.0 Received: by 10.220.124.153 with SMTP id u25mr169366vcr.206.1279255033757; Thu, 15 Jul 2010 21:37:13 -0700 (PDT) Received: by 10.220.199.200 with HTTP; Thu, 15 Jul 2010 21:37:13 -0700 (PDT) In-Reply-To: <20100715.161926.175946041864758761.imp@bsdimp.com> References: <20100715.161926.175946041864758761.imp@bsdimp.com> Date: Fri, 16 Jul 2010 10:07:13 +0530 Message-ID: From: "Jayachandran C." To: "M. Warner Losh" Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: mips@freebsd.org Subject: Re: Review X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Jul 2010 04:37:16 -0000 On Fri, Jul 16, 2010 at 3:49 AM, M. Warner Losh wrote: > OK. =A0Please find enclosed a minor cleanup diff for assembler files. > It moves ITLBNOPFIX and HAZARD_DELAY into a common header, as well as > replacing MIPS_CPU_NOP_DELAY with HAZARD_DELAY. > > The only real change is increasing the number of nops in a few places > from 4 to 5. > > This is in preparation for making these (a) much shorter and (b) > optimizing for specific CPUs... =A0mips32/mips64 define ssnop to deal > with the super-scaler effects (so ITLBNOPFIX can be shorter), and > mips32r2 and mips64r2 have eh, which can help with HAZARD_DELAY. > > The latter will need some careful study of the docs to make sure that > the proper number of instructions are executed (which is why I'm not > doing it yet :). =A0The former is just shuffling deck chairs, so should b= e > invisible to people. > > Comments? There is a mips_barrier() in cpufunc.h too which does similar things - and is confusingly named - we can to get rid of that too in a similar way. Another cleanup I wanted to do for sometime is to get the status register settings into a header files and avoid the ifdef everywhere. Maybe cpuregs.h (or cpufunc.h) can add cpu_xlr.h/cpu_octeon.h etc which will have hazard/status/extra registers for the specific cpu. Thanks, JC. From owner-freebsd-mips@FreeBSD.ORG Sat Jul 17 13:00:38 2010 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 73DCA1065675 for ; Sat, 17 Jul 2010 13:00:38 +0000 (UTC) (envelope-from mavbsd@gmail.com) Received: from mail-fx0-f54.google.com (mail-fx0-f54.google.com [209.85.161.54]) by mx1.freebsd.org (Postfix) with ESMTP id 04ACD8FC18 for ; Sat, 17 Jul 2010 13:00:37 +0000 (UTC) Received: by fxm13 with SMTP id 13so1692146fxm.13 for ; Sat, 17 Jul 2010 06:00:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:message-id:date:from :user-agent:mime-version:to:cc:subject:x-enigmail-version :content-type:content-transfer-encoding; bh=P9ofWNmWHHtADwh/HZlPinwdcPQ6QRxFHcTPyUhMU74=; b=Zta1gJa5huGcFekcespcCU+XbyCbXjRCnFMt4YmAxmA7BSsoZ+BYJb7TNR+DKEAbHU EGiOSUVurQdpJ0IqWTg5oIXe8PkXQfQK7zrdlfo0Wwitj4zlj6E8HjUXhZp7CM/e0Mue kDC2LDpYc2nipBDCdjw5GTo10EQlxDkpsOuwM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:message-id:date:from:user-agent:mime-version:to:cc:subject :x-enigmail-version:content-type:content-transfer-encoding; b=mVlwn5MLdzt9poHqvygn0g+3/5QfTzCm7ddqzv2jL8bl+r7hweTUo60NZTv5iRTtAI XNngt2FjhIpKlhG+8CsWB/dKtlmbWxVnVo+mJzkCPzguHDXw6PSM3xlthNfvKnjNRipV E/kwsYQ16KtoKdWwvf3iKdaze9zTuJo2pSX0k= Received: by 10.223.120.65 with SMTP id c1mr1629694far.68.1279369872331; Sat, 17 Jul 2010 05:31:12 -0700 (PDT) Received: from mavbook2.mavhome.dp.ua (pc.mavhome.dp.ua [212.86.226.226]) by mx.google.com with ESMTPS id r5sm1162928faq.8.2010.07.17.05.31.10 (version=SSLv3 cipher=RC4-MD5); Sat, 17 Jul 2010 05:31:11 -0700 (PDT) Sender: Alexander Motin Message-ID: <4C41A248.8090605@FreeBSD.org> Date: Sat, 17 Jul 2010 15:30:00 +0300 From: Alexander Motin User-Agent: Thunderbird 2.0.0.23 (X11/20091212) MIME-Version: 1.0 To: freebsd-mips@freebsd.org X-Enigmail-Version: 0.96.0 Content-Type: text/plain; charset=KOI8-R Content-Transfer-Encoding: 7bit Cc: Neel Natu Subject: [RFC] Event timers on MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Jul 2010 13:00:38 -0000 Hi. I've made a patch, updating MIPS timer code (except RMI) to utilize new MI event timer infrastructure. I've successfully built QEMU and XLR kernels with the patch. Unluckily I can't test how it works, unless somebody teach me how to cook QEMU to run it. I also haven't ported RMI timers drivers, as I am not sure how that hardware is intended to work. Patch for HEAD can be found here: http://people.freebsd.org/~mav/timers_mips.patch Could somebody falimiar with MIPS review/test my patch and extend it to RMI hardware? Thank you. -- Alexander Motin From owner-freebsd-mips@FreeBSD.ORG Sat Jul 17 13:27:24 2010 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id A9F72106566B; Sat, 17 Jul 2010 13:27:24 +0000 (UTC) (envelope-from c.jayachandran@gmail.com) Received: from mail-vw0-f44.google.com (mail-vw0-f44.google.com [209.85.212.44]) by mx1.freebsd.org (Postfix) with ESMTP id D4A298FC1B; Sat, 17 Jul 2010 13:27:23 +0000 (UTC) Received: by vws14 with SMTP id 14so4224553vws.17 for ; Sat, 17 Jul 2010 06:27:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=jBYk3g0CthyVltpCeDPeW69T78CPcvRl9pI8fCBppuo=; b=isVMFSqHiYFOQt2B72Gz8V/VYpIeeArsfyXUXB0621Lo6Fw90rr6w0RfJUz3zWncb8 FZ+P93Penz8GGez4Zn6XdW0/ZKkMZfBLPSIUD4LHOe4luiKm7DoFPrVsp/nSOYqtfy6F XtYMcwfBBbQ/E8sCZgWkI252TgoxrMWbi1K38= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=qrutVyt+rjRduZ8v9pR4i1MAK0ex4rSPDQNXjW9gS91uAriQeLhFPZg62idUCkuIjN w8YibkZaD66zIuYVrZYf2dXSv6lNqB6fk34vCy3ie7e2vZOiEgj1fA+RDbqeoTynnfJt i5b364gvZbRPmcRwBBZlTdIViCNryx9KuCjE4= MIME-Version: 1.0 Received: by 10.220.75.148 with SMTP id y20mr1424916vcj.4.1279373243022; Sat, 17 Jul 2010 06:27:23 -0700 (PDT) Received: by 10.220.188.138 with HTTP; Sat, 17 Jul 2010 06:27:22 -0700 (PDT) In-Reply-To: <4C41A248.8090605@FreeBSD.org> References: <4C41A248.8090605@FreeBSD.org> Date: Sat, 17 Jul 2010 18:57:22 +0530 Message-ID: From: "Jayachandran C." To: Alexander Motin Content-Type: text/plain; charset=ISO-8859-1 Cc: Neel Natu , freebsd-mips@freebsd.org Subject: Re: [RFC] Event timers on MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Jul 2010 13:27:24 -0000 2010/7/17 Alexander Motin : > Hi. > > I've made a patch, updating MIPS timer code (except RMI) to utilize new > MI event timer infrastructure. I've successfully built QEMU and XLR > kernels with the patch. Unluckily I can't test how it works, unless > somebody teach me how to cook QEMU to run it. I also haven't ported RMI > timers drivers, as I am not sure how that hardware is intended to work. > > Patch for HEAD can be found here: > http://people.freebsd.org/~mav/timers_mips.patch > > Could somebody falimiar with MIPS review/test my patch and extend it to > RMI hardware? XLR uses an on-chip PIC clock (running at 66MHz) for cpu 0 and count/compare clock (running at CPU freq) for the other CPUs, hope this is supported with the new code. Other than that, I should be able to merge the code into XLR specific rmi/tick.c rmi/clock.c, if it works on other MIPS platforms. JC. From owner-freebsd-mips@FreeBSD.ORG Sat Jul 17 13:50:12 2010 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 324BA106567E; Sat, 17 Jul 2010 13:50:12 +0000 (UTC) (envelope-from mavbsd@gmail.com) Received: from mail-fx0-f54.google.com (mail-fx0-f54.google.com [209.85.161.54]) by mx1.freebsd.org (Postfix) with ESMTP id 8DDA68FC12; Sat, 17 Jul 2010 13:50:11 +0000 (UTC) Received: by fxm13 with SMTP id 13so1703958fxm.13 for ; Sat, 17 Jul 2010 06:50:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:message-id:date:from :user-agent:mime-version:to:cc:subject:references:in-reply-to :x-enigmail-version:content-type:content-transfer-encoding; bh=zVJvkuxr4NNqTOqG/vLSd3rPQsEihM4RUdzkYWxL+Nw=; b=BHDi2ms0YGwr59Aq/gI+JuTUxtejIaxrz9WcADBlbx+SN+ORZO7mbulQJB8Ya1JU2h CDKjukGRYQx4CYODmXOvHEDWCKtLVVXCIPP9AylAHQCHmHGLsEBzp/pYYaTAhczyumfu RTgXrdX99+SchfoM5qWEcNJEjsDWGdh53Hi2U= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:x-enigmail-version:content-type :content-transfer-encoding; b=px//GE8PXRN0S/sH7s0y5BUsK05mjH0wdH5H0UeLT7bpr8hEn8NcrXP1IZEe1+uL4c VaohsLz66Hj//pXf2RrajnjzP3QO7n966zTupp1QoAwT4Phv0WS576nLjcHFbsFM3dm5 GtfzQz/s6Svk8Dpc7GSfDmBcDITHwpRnqAtY8= Received: by 10.223.108.204 with SMTP id g12mr1694405fap.21.1279374610369; Sat, 17 Jul 2010 06:50:10 -0700 (PDT) Received: from mavbook2.mavhome.dp.ua (pc.mavhome.dp.ua [212.86.226.226]) by mx.google.com with ESMTPS id n27sm1185829fam.20.2010.07.17.06.50.09 (version=SSLv3 cipher=RC4-MD5); Sat, 17 Jul 2010 06:50:09 -0700 (PDT) Sender: Alexander Motin Message-ID: <4C41B4CF.6080409@FreeBSD.org> Date: Sat, 17 Jul 2010 16:49:03 +0300 From: Alexander Motin User-Agent: Thunderbird 2.0.0.23 (X11/20091212) MIME-Version: 1.0 To: "Jayachandran C." References: <4C41A248.8090605@FreeBSD.org> In-Reply-To: X-Enigmail-Version: 0.96.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: Neel Natu , freebsd-mips@freebsd.org Subject: Re: [RFC] Event timers on MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Jul 2010 13:50:12 -0000 Jayachandran C. wrote: > 2010/7/17 Alexander Motin : >> I've made a patch, updating MIPS timer code (except RMI) to utilize new >> MI event timer infrastructure. I've successfully built QEMU and XLR >> kernels with the patch. Unluckily I can't test how it works, unless >> somebody teach me how to cook QEMU to run it. I also haven't ported RMI >> timers drivers, as I am not sure how that hardware is intended to work. >> >> Patch for HEAD can be found here: >> http://people.freebsd.org/~mav/timers_mips.patch >> >> Could somebody falimiar with MIPS review/test my patch and extend it to >> RMI hardware? > > XLR uses an on-chip PIC clock (running at 66MHz) for cpu 0 and > count/compare clock (running at CPU freq) for the other CPUs, hope > this is supported with the new code. I suppose that one type of timers should run on all CPUs (either one timer per CPU, or one timer for all of them + IPI for distribution). Theoretically you can implement "single" per-CPU timer implemented in different fashion for different CPUs, though I don't understand why it is needed. If these timers are independent, I would register every of them as-is: on-chip PIC clock as global timer (infrastructure will automatically manage rebroadcasting it's events via IPIs) and per-CPU comparators as another per-CPU timer. This give independent hardclock and statclock for less aliased time accounting. > Other than that, I should be able to merge the code into XLR specific > rmi/tick.c rmi/clock.c, if it works on other MIPS platforms. rmi/tick.c looks somewhat strange to me, registering timecounter with the same "MIPS32" name, but with different meaning. -- Alexander Motin From owner-freebsd-mips@FreeBSD.ORG Sat Jul 17 17:27:12 2010 Return-Path: Delivered-To: freebsd-mips@FreeBSD.ORG Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id A3B53106566B; Sat, 17 Jul 2010 17:27:12 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id 62F3F8FC18; Sat, 17 Jul 2010 17:27:12 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by harmony.bsdimp.com (8.14.3/8.14.1) with ESMTP id o6HHMAni013293; Sat, 17 Jul 2010 11:22:10 -0600 (MDT) (envelope-from imp@bsdimp.com) Date: Sat, 17 Jul 2010 11:22:33 -0600 (MDT) Message-Id: <20100717.112233.994790107173916507.imp@bsdimp.com> To: mav@FreeBSD.ORG From: "M. Warner Losh" In-Reply-To: <4C41A248.8090605@FreeBSD.org> References: <4C41A248.8090605@FreeBSD.org> X-Mailer: Mew version 6.3 on Emacs 22.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cc: neel@FreeBSD.ORG, freebsd-mips@FreeBSD.ORG Subject: Re: [RFC] Event timers on MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Jul 2010 17:27:12 -0000 In message: <4C41A248.8090605@FreeBSD.org> Alexander Motin writes: : Hi. : : I've made a patch, updating MIPS timer code (except RMI) to utilize new : MI event timer infrastructure. I've successfully built QEMU and XLR : kernels with the patch. Unluckily I can't test how it works, unless : somebody teach me how to cook QEMU to run it. I also haven't ported RMI : timers drivers, as I am not sure how that hardware is intended to work. : : Patch for HEAD can be found here: : http://people.freebsd.org/~mav/timers_mips.patch I'll have to take a look at things. On MIPS, the COMPARE register is per core, so you don't need to send an IPI if you are using that hardware. IPIs are a little expensive, IIRC, since they tend to have bad cache effects and put extra pressure on the TLBs. It wasn't clear from these patches if you are using one core to do the signalling for all the others or not. If so, that represents a bit of a regression. I'm also not sure about not having a per-cpu timer's effect on performance on a 16 or 32 core MIPS box... : Could somebody falimiar with MIPS review/test my patch and extend it to : RMI hardware? I see someone else has commented on that. Warner From owner-freebsd-mips@FreeBSD.ORG Sat Jul 17 17:34:10 2010 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 95680106566B; Sat, 17 Jul 2010 17:34:10 +0000 (UTC) (envelope-from mavbsd@gmail.com) Received: from mail-fx0-f54.google.com (mail-fx0-f54.google.com [209.85.161.54]) by mx1.freebsd.org (Postfix) with ESMTP id D75258FC16; Sat, 17 Jul 2010 17:34:09 +0000 (UTC) Received: by fxm13 with SMTP id 13so1758307fxm.13 for ; Sat, 17 Jul 2010 10:34:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:message-id:date:from :user-agent:mime-version:to:cc:subject:references:in-reply-to :x-enigmail-version:content-type:content-transfer-encoding; bh=UW1lqRR7EjGsoetvAYL+fm8TbPcY8SScLFVaAqd+4p8=; b=OU8VjVunz0l3qshhW88DsaETR9F5YGfjMm5RLeOTnuT0mAwbCzg3TKyp1HPseKLfPM CLQFmyb8z/dlKDPsKp2YUfW87WAb7HZ/FPc/EaRE1CVCVy2JUPMANzI3BXrSx3lsUzYL CEh143CvWQhj4XwxPbOXJBlIpuufbwIVIOkUw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:x-enigmail-version:content-type :content-transfer-encoding; b=B7c6Os6PZS+LaS2zKT9PmW9SO4WBuxZHAvuc6unAXH/2GRjULTaftNPdals7Ar7xUs uBWKGwHOWR6EBqdwYVcOVqjtpQEHuIbeV7uiJ7k3UXl8vPTWb+YudUGHRpwtocbLAlQy GpH5QxPkzgjchBt7rtywT/kgBjc8r2pnv7tHU= Received: by 10.223.107.137 with SMTP id b9mr1835331fap.17.1279388048551; Sat, 17 Jul 2010 10:34:08 -0700 (PDT) Received: from mavbook2.mavhome.dp.ua (pc.mavhome.dp.ua [212.86.226.226]) by mx.google.com with ESMTPS id b36sm1252051faq.35.2010.07.17.10.34.07 (version=SSLv3 cipher=RC4-MD5); Sat, 17 Jul 2010 10:34:07 -0700 (PDT) Sender: Alexander Motin Message-ID: <4C41E94D.5030206@FreeBSD.org> Date: Sat, 17 Jul 2010 20:33:01 +0300 From: Alexander Motin User-Agent: Thunderbird 2.0.0.23 (X11/20091212) MIME-Version: 1.0 To: "M. Warner Losh" References: <4C41A248.8090605@FreeBSD.org> <20100717.112233.994790107173916507.imp@bsdimp.com> In-Reply-To: <20100717.112233.994790107173916507.imp@bsdimp.com> X-Enigmail-Version: 0.96.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: neel@FreeBSD.ORG, freebsd-mips@FreeBSD.ORG Subject: Re: [RFC] Event timers on MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Jul 2010 17:34:10 -0000 M. Warner Losh wrote: > In message: <4C41A248.8090605@FreeBSD.org> > Alexander Motin writes: > : I've made a patch, updating MIPS timer code (except RMI) to utilize new > : MI event timer infrastructure. I've successfully built QEMU and XLR > : kernels with the patch. Unluckily I can't test how it works, unless > : somebody teach me how to cook QEMU to run it. I also haven't ported RMI > : timers drivers, as I am not sure how that hardware is intended to work. > : > : Patch for HEAD can be found here: > : http://people.freebsd.org/~mav/timers_mips.patch > > I'll have to take a look at things. On MIPS, the COMPARE register is > per core, so you don't need to send an IPI if you are using that > hardware. IPIs are a little expensive, IIRC, since they tend to have > bad cache effects and put extra pressure on the TLBs. > > It wasn't clear from these patches if you are using one core to do the > signalling for all the others or not. If so, that represents a bit of > a regression. I'm also not sure about not having a per-cpu timer's > effect on performance on a 16 or 32 core MIPS box... I am registering event timer as per-CPU: + sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | + ET_FLAGS_PERCPU; Clock IPI's added only for completeness, in case there will be supported any other non-per-CPU timers, like mentioned PIC clock on XLR. Thanks. -- Alexander Motin From owner-freebsd-mips@FreeBSD.ORG Sat Jul 17 17:58:15 2010 Return-Path: Delivered-To: freebsd-mips@FreeBSD.ORG Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 3BB571065677; Sat, 17 Jul 2010 17:58:15 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id 1E1E68FC19; Sat, 17 Jul 2010 17:58:14 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by harmony.bsdimp.com (8.14.3/8.14.1) with ESMTP id o6HHs8K5013503; Sat, 17 Jul 2010 11:54:08 -0600 (MDT) (envelope-from imp@bsdimp.com) Date: Sat, 17 Jul 2010 11:54:32 -0600 (MDT) Message-Id: <20100717.115432.680326283860859045.imp@bsdimp.com> To: mav@FreeBSD.ORG From: "M. Warner Losh" In-Reply-To: <4C41E94D.5030206@FreeBSD.org> References: <4C41A248.8090605@FreeBSD.org> <20100717.112233.994790107173916507.imp@bsdimp.com> <4C41E94D.5030206@FreeBSD.org> X-Mailer: Mew version 6.3 on Emacs 22.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cc: neel@FreeBSD.ORG, freebsd-mips@FreeBSD.ORG Subject: Re: [RFC] Event timers on MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Jul 2010 17:58:15 -0000 In message: <4C41E94D.5030206@FreeBSD.org> Alexander Motin writes: : M. Warner Losh wrote: : > In message: <4C41A248.8090605@FreeBSD.org> : > Alexander Motin writes: : > : I've made a patch, updating MIPS timer code (except RMI) to utilize new : > : MI event timer infrastructure. I've successfully built QEMU and XLR : > : kernels with the patch. Unluckily I can't test how it works, unless : > : somebody teach me how to cook QEMU to run it. I also haven't ported RMI : > : timers drivers, as I am not sure how that hardware is intended to work. : > : : > : Patch for HEAD can be found here: : > : http://people.freebsd.org/~mav/timers_mips.patch : > : > I'll have to take a look at things. On MIPS, the COMPARE register is : > per core, so you don't need to send an IPI if you are using that : > hardware. IPIs are a little expensive, IIRC, since they tend to have : > bad cache effects and put extra pressure on the TLBs. : > : > It wasn't clear from these patches if you are using one core to do the : > signalling for all the others or not. If so, that represents a bit of : > a regression. I'm also not sure about not having a per-cpu timer's : > effect on performance on a 16 or 32 core MIPS box... : : I am registering event timer as per-CPU: : + sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | : + ET_FLAGS_PERCPU; : : Clock IPI's added only for completeness, in case there will be supported : any other non-per-CPU timers, like mentioned PIC clock on XLR. That sounds good.... Warner From owner-freebsd-mips@FreeBSD.ORG Sat Jul 17 18:36:00 2010 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 8030F10656FF; Sat, 17 Jul 2010 18:36:00 +0000 (UTC) (envelope-from c.jayachandran@gmail.com) Received: from mail-vw0-f54.google.com (mail-vw0-f54.google.com [209.85.212.54]) by mx1.freebsd.org (Postfix) with ESMTP id 9CC2A8FC21; Sat, 17 Jul 2010 18:35:59 +0000 (UTC) Received: by vws19 with SMTP id 19so4459105vws.13 for ; Sat, 17 Jul 2010 11:35:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=DMZT54iP6ChPCXLSR9L95jYbP9VHiYNZqnQEVRQmsMY=; b=pQ3XCsTRHbQGTFrHMFUfQGLbkMlWDMZ+aUD6QbYjN4pefMrscxz/7tNRGga3ZFXerW Kf2f/BmumIIAGytHVk3F/ANss124fnO8n/B0i5G/JsEA0UDLupFwy7HAwx30+GWWReKo 8A+vRTEqzKCIckmsOqEoKJGsrIOAd/gsAfGhA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=MTA86ZAfWy3fVee+oHWS3/Tn1xEJi91c3vbHbGFMIR190aR5Igytq0KWYudDKI9Mg3 jOSfoKSSlnHcprPLW9qsLUftaH0cmqyRifDvgIyC0dZzv1OvWAGcV0rNqcswoOBorEJL 8gvhGLPLGYubDBFu3tijljBAF80Ee7Ez/VmgU= MIME-Version: 1.0 Received: by 10.220.60.203 with SMTP id q11mr1483399vch.28.1279391758920; Sat, 17 Jul 2010 11:35:58 -0700 (PDT) Received: by 10.220.188.138 with HTTP; Sat, 17 Jul 2010 11:35:58 -0700 (PDT) In-Reply-To: <4C41B4CF.6080409@FreeBSD.org> References: <4C41A248.8090605@FreeBSD.org> <4C41B4CF.6080409@FreeBSD.org> Date: Sun, 18 Jul 2010 00:05:58 +0530 Message-ID: From: "Jayachandran C." To: Alexander Motin Content-Type: text/plain; charset=ISO-8859-1 Cc: Neel Natu , freebsd-mips@freebsd.org Subject: Re: [RFC] Event timers on MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Jul 2010 18:36:00 -0000 On Sat, Jul 17, 2010 at 7:19 PM, Alexander Motin wrote: > Jayachandran C. wrote: >> 2010/7/17 Alexander Motin : >>> I've made a patch, updating MIPS timer code (except RMI) to utilize new >>> MI event timer infrastructure. I've successfully built QEMU and XLR >>> kernels with the patch. Unluckily I can't test how it works, unless >>> somebody teach me how to cook QEMU to run it. I also haven't ported RMI >>> timers drivers, as I am not sure how that hardware is intended to work. >>> >>> Patch for HEAD can be found here: >>> http://people.freebsd.org/~mav/timers_mips.patch >>> >>> Could somebody falimiar with MIPS review/test my patch and extend it to >>> RMI hardware? >> >> XLR uses an on-chip PIC clock (running at 66MHz) for cpu 0 and >> count/compare clock (running at CPU freq) for the other CPUs, hope >> this is supported with the new code. > > I suppose that one type of timers should run on all CPUs (either one > timer per CPU, or one timer for all of them + IPI for distribution). > Theoretically you can implement "single" per-CPU timer implemented in > different fashion for different CPUs, though I don't understand why it > is needed. If these timers are independent, I would register every of > them as-is: on-chip PIC clock as global timer (infrastructure will > automatically manage rebroadcasting it's events via IPIs) and per-CPU > comparators as another per-CPU timer. This give independent hardclock > and statclock for less aliased time accounting. > >> Other than that, I should be able to merge the code into XLR specific >> rmi/tick.c rmi/clock.c, if it works on other MIPS platforms. > > rmi/tick.c looks somewhat strange to me, registering timecounter with > the same "MIPS32" name, but with different meaning. On XLR we would like to use the count/compare which is faster but less accurate on all cpus - we can have upto 32 cpus now. We also have a PIC which can provide a better timestamp and timer interrupts. This PIC timestamp can be read from all CPUs but the timer interrupt can be delivered to just one CPU at a time. I think this is how we ended up with the current implementation, but any suggestions on how to improve this is welcome. Thanks, JC. From owner-freebsd-mips@FreeBSD.ORG Sat Jul 17 19:35:49 2010 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id AD84E1065677; Sat, 17 Jul 2010 19:35:49 +0000 (UTC) (envelope-from mavbsd@gmail.com) Received: from mail-fx0-f54.google.com (mail-fx0-f54.google.com [209.85.161.54]) by mx1.freebsd.org (Postfix) with ESMTP id 121FD8FC1C; Sat, 17 Jul 2010 19:35:44 +0000 (UTC) Received: by fxm13 with SMTP id 13so1785330fxm.13 for ; Sat, 17 Jul 2010 12:35:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:message-id:date:from :user-agent:mime-version:to:cc:subject:references:in-reply-to :x-enigmail-version:content-type:content-transfer-encoding; bh=4qI01sPq9nxyVfBLb9j2LlAOvtPR84ZCAMiIC/q57cs=; b=AFy4+MujYfquAgBPicV3gTaoLEh+zj9sfrWOQEodsrFKj/r4BSDZ6N7n+5VUA9iFMp pSGUNECedc21BeeDbvCbraMEnZr+FGKxTtwDa5mSXkziUfGOVTxkl9eOYa9odH2tKoXR hhy+qjk20dSPXabTZKHH2awummix1YzxcLVgo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:x-enigmail-version:content-type :content-transfer-encoding; b=qdDYOI7/YrXXP2BMn0dNGo3h02fdUnH9oMACMblHOyjHIW+oC/EoVNGYzUU1nY4nu2 WRHgqK3DBrDCm+G7uVWoF9+Oj/93waNqg+8uOtaAXhCq1XTt77Kelw0vByX7I8HpQ46z NoEXw4k01Te0XoyLhq739/Ij05g5L0PR93Ovg= Received: by 10.223.111.200 with SMTP id t8mr1919308fap.31.1279395343801; Sat, 17 Jul 2010 12:35:43 -0700 (PDT) Received: from mavbook2.mavhome.dp.ua (pc.mavhome.dp.ua [212.86.226.226]) by mx.google.com with ESMTPS id h8sm1288701faj.14.2010.07.17.12.35.42 (version=SSLv3 cipher=RC4-MD5); Sat, 17 Jul 2010 12:35:43 -0700 (PDT) Sender: Alexander Motin Message-ID: <4C4205CC.6080700@FreeBSD.org> Date: Sat, 17 Jul 2010 22:34:36 +0300 From: Alexander Motin User-Agent: Thunderbird 2.0.0.23 (X11/20091212) MIME-Version: 1.0 To: "Jayachandran C." References: <4C41A248.8090605@FreeBSD.org> <4C41B4CF.6080409@FreeBSD.org> In-Reply-To: X-Enigmail-Version: 0.96.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: Neel Natu , freebsd-mips@freebsd.org Subject: Re: [RFC] Event timers on MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Jul 2010 19:35:49 -0000 Jayachandran C. wrote: > On XLR we would like to use the count/compare which is faster but less > accurate on all cpus - we can have upto 32 cpus now. We also have a > PIC which can provide a better timestamp and timer interrupts. This > PIC timestamp can be read from all CPUs but the timer interrupt can be > delivered to just one CPU at a time. I think this is how we ended up > with the current implementation, but any suggestions on how to improve > this is welcome. I would prefer to not mix the things. I think: - PIC timestamp looks like the best candidate for system timecounter. - per-CPU counters could be registered as per-CPU timecounters with set_cputicker() - the main criteria there is a speed. - if per-CPU counters are synchronized between CPUs - they could be registered as alternative timecounter for people who wish fastest timecounting; if they are not - they are useless in that role. - both PIC timer and per-CPU comparators should be independently registered as eventtimers - it is better to have two of them to from accounting correctness PoV, and it will allow user to experiment which one he likes more. - if there is any other timer hardware - it also should be registered - it will give additional flexibility. PS: I've managed to run MALTA kernel with patch under gxemul. It works, except time is not going right. But I suppose it is emulator problem, as original kernel works the same. -- Alexander Motin From owner-freebsd-mips@FreeBSD.ORG Sat Jul 17 21:40:33 2010 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 32FA3106564A; Sat, 17 Jul 2010 21:40:33 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id C6F578FC1B; Sat, 17 Jul 2010 21:40:32 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by harmony.bsdimp.com (8.14.3/8.14.1) with ESMTP id o6HLcIiG015139; Sat, 17 Jul 2010 15:38:18 -0600 (MDT) (envelope-from imp@bsdimp.com) Date: Sat, 17 Jul 2010 15:38:42 -0600 (MDT) Message-Id: <20100717.153842.466815693171225157.imp@bsdimp.com> To: mav@freebsd.org From: "M. Warner Losh" In-Reply-To: <4C4205CC.6080700@FreeBSD.org> References: <4C41B4CF.6080409@FreeBSD.org> <4C4205CC.6080700@FreeBSD.org> X-Mailer: Mew version 6.3 on Emacs 22.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cc: neel@freebsd.org, freebsd-mips@freebsd.org Subject: Re: [RFC] Event timers on MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Jul 2010 21:40:33 -0000 In message: <4C4205CC.6080700@FreeBSD.org> Alexander Motin writes: : Jayachandran C. wrote: : > On XLR we would like to use the count/compare which is faster but less : > accurate on all cpus - we can have upto 32 cpus now. We also have a : > PIC which can provide a better timestamp and timer interrupts. This : > PIC timestamp can be read from all CPUs but the timer interrupt can be : > delivered to just one CPU at a time. I think this is how we ended up : > with the current implementation, but any suggestions on how to improve : > this is welcome. : : I would prefer to not mix the things. : : I think: : - PIC timestamp looks like the best candidate for system timecounter. No it doesn't. Reading the PIC is a lot more expensive than reading the COUNTER register. It would be better to read the PIC from time to time and correlate it to the COUNTER register, and interpolate the final result. This would keep the COUNTER register time device on time and on frequency, while still giving us the speed advantage of the less accurate COUNTER. Small differences in the time it takes to get the time of day can make huge differences in some work loads. We need to be sensitive here that we're not unduly penalizing the XLR in this case. : - per-CPU counters could be registered as per-CPU timecounters with : set_cputicker() - the main criteria there is a speed. : - if per-CPU counters are synchronized between CPUs - they could be : registered as alternative timecounter for people who wish fastest : timecounting; if they are not - they are useless in that role. I don't know how well synchronized they are between CPUs. I'm not 100% sure that you can count on that on Cavium. I'm looking for my Cavium docs to see if they say anything about that or not, but given the number of people using multi-core caviums and some of the code that runs on them, I'm pretty sure the cycle counters there, at least, are coherent. I don't have XLR docs. : - both PIC timer and per-CPU comparators should be independently : registered as eventtimers - it is better to have two of them to from : accounting correctness PoV, and it will allow user to experiment which : one he likes more. : - if there is any other timer hardware - it also should be registered - : it will give additional flexibility. : : PS: I've managed to run MALTA kernel with patch under gxemul. It works, : except time is not going right. But I suppose it is emulator problem, as : original kernel works the same. gxemul is known to have time issues. Warner From owner-freebsd-mips@FreeBSD.ORG Sat Jul 17 22:34:42 2010 Return-Path: Delivered-To: mips@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 29F0F1065677 for ; Sat, 17 Jul 2010 22:34:42 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id DFE808FC14 for ; Sat, 17 Jul 2010 22:34:41 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by harmony.bsdimp.com (8.14.3/8.14.1) with ESMTP id o6HMTcxT015499; Sat, 17 Jul 2010 16:29:38 -0600 (MDT) (envelope-from imp@bsdimp.com) Date: Sat, 17 Jul 2010 16:30:02 -0600 (MDT) Message-Id: <20100717.163002.13040899182090510.imp@bsdimp.com> To: c.jayachandran@gmail.com From: "M. Warner Losh" In-Reply-To: References: <20100715.161926.175946041864758761.imp@bsdimp.com> X-Mailer: Mew version 6.3 on Emacs 22.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Cc: mips@FreeBSD.org Subject: Re: Review X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Jul 2010 22:34:42 -0000 In message: "Jayachandran C." writes: : On Fri, Jul 16, 2010 at 3:49 AM, M. Warner Losh wrot= e: : > OK. =A0Please find enclosed a minor cleanup diff for assembler file= s. : > It moves ITLBNOPFIX and HAZARD_DELAY into a common header, as well = as : > replacing MIPS_CPU_NOP_DELAY with HAZARD_DELAY. : > : > The only real change is increasing the number of nops in a few plac= es : > from 4 to 5. : > : > This is in preparation for making these (a) much shorter and (b) : > optimizing for specific CPUs... =A0mips32/mips64 define ssnop to de= al : > with the super-scaler effects (so ITLBNOPFIX can be shorter), and : > mips32r2 and mips64r2 have eh, which can help with HAZARD_DELAY. : > : > The latter will need some careful study of the docs to make sure th= at : > the proper number of instructions are executed (which is why I'm no= t : > doing it yet :). =A0The former is just shuffling deck chairs, so sh= ould be : > invisible to people. : > : > Comments? : = : There is a mips_barrier() in cpufunc.h too which does similar things = - : and is confusingly named - we can to get rid of that too in a similar= : way. Yea, there's similar things in that file to the other stuff... : Another cleanup I wanted to do for sometime is to get the status : register settings into a header files and avoid the ifdef everywhere.= I've wanted that too.... : Maybe cpuregs.h (or cpufunc.h) can add cpu_xlr.h/cpu_octeon.h etc : which will have hazard/status/extra registers for the specific cpu. Yea, that's a good idea, I think... There's also lots of places we disable interrupts by writing to STATUS, but that could be dealt with EI or DI... Warner : Thanks, : JC. : = : =