From owner-svn-src-vendor@freebsd.org Thu Feb 1 21:07:59 2018 Return-Path: Delivered-To: svn-src-vendor@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 372B2EC9703; Thu, 1 Feb 2018 21:07:59 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id D67418632C; Thu, 1 Feb 2018 21:07:58 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id D12EC124E8; Thu, 1 Feb 2018 21:07:58 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w11L7wQH073450; Thu, 1 Feb 2018 21:07:58 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w11L7tio073418; Thu, 1 Feb 2018 21:07:55 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201802012107.w11L7tio073418@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Thu, 1 Feb 2018 21:07:55 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r328734 - in vendor/llvm/dist-release_60: docs include/llvm/Analysis include/llvm/MC lib/Analysis lib/CodeGen lib/CodeGen/GlobalISel lib/CodeGen/SelectionDAG lib/MC lib/Target/AArch64 l... X-SVN-Group: vendor X-SVN-Commit-Author: dim X-SVN-Commit-Paths: in vendor/llvm/dist-release_60: docs include/llvm/Analysis include/llvm/MC lib/Analysis lib/CodeGen lib/CodeGen/GlobalISel lib/CodeGen/SelectionDAG lib/MC lib/Target/AArch64 lib/Target/AMDGPU lib/Targ... X-SVN-Commit-Revision: 328734 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-vendor@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the vendor work area tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Feb 2018 21:07:59 -0000 Author: dim Date: Thu Feb 1 21:07:55 2018 New Revision: 328734 URL: https://svnweb.freebsd.org/changeset/base/328734 Log: Vendor import of llvm release_60 branch r323948: https://llvm.org/svn/llvm-project/llvm/branches/release_60@323948 Added: vendor/llvm/dist-release_60/test/Analysis/ValueTracking/select-pattern.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir vendor/llvm/dist-release_60/test/CodeGen/X86/pr34592.ll vendor/llvm/dist-release_60/test/MC/X86/eval-fill.s (contents, props changed) vendor/llvm/dist-release_60/test/ThinLTO/X86/Inputs/dicompositetype-unique-alias.ll vendor/llvm/dist-release_60/test/ThinLTO/X86/dicompositetype-unique-alias.ll vendor/llvm/dist-release_60/test/Transforms/StructurizeCFG/bug36015.ll Modified: vendor/llvm/dist-release_60/docs/ReleaseNotes.rst vendor/llvm/dist-release_60/include/llvm/Analysis/ValueTracking.h vendor/llvm/dist-release_60/include/llvm/MC/MCFragment.h vendor/llvm/dist-release_60/include/llvm/MC/MCObjectStreamer.h vendor/llvm/dist-release_60/include/llvm/MC/MCStreamer.h vendor/llvm/dist-release_60/lib/Analysis/ValueTracking.cpp vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/IRTranslator.cpp vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/LegalizerHelper.cpp vendor/llvm/dist-release_60/lib/CodeGen/RegAllocFast.cpp vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp vendor/llvm/dist-release_60/lib/CodeGen/TargetPassConfig.cpp vendor/llvm/dist-release_60/lib/MC/MCAsmStreamer.cpp vendor/llvm/dist-release_60/lib/MC/MCAssembler.cpp vendor/llvm/dist-release_60/lib/MC/MCMachOStreamer.cpp vendor/llvm/dist-release_60/lib/MC/MCObjectStreamer.cpp vendor/llvm/dist-release_60/lib/MC/MCStreamer.cpp vendor/llvm/dist-release_60/lib/MC/MCWinCOFFStreamer.cpp vendor/llvm/dist-release_60/lib/MC/WasmObjectWriter.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FastISel.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64Subtarget.cpp vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInsertSkips.cpp vendor/llvm/dist-release_60/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/CallSiteSplitting.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/StructurizeCFG.cpp vendor/llvm/dist-release_60/lib/Transforms/Utils/ValueMapper.cpp vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir vendor/llvm/dist-release_60/test/CodeGen/AArch64/dllimport.ll vendor/llvm/dist-release_60/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll vendor/llvm/dist-release_60/test/CodeGen/AMDGPU/multilevel-break.ll vendor/llvm/dist-release_60/test/CodeGen/AMDGPU/nested-loop-conditions.ll vendor/llvm/dist-release_60/test/MC/X86/x86-32-coverage.s vendor/llvm/dist-release_60/test/Transforms/CallSiteSplitting/callsite-no-splitting.ll vendor/llvm/dist-release_60/test/Transforms/InstCombine/minmax-fold.ll vendor/llvm/dist-release_60/test/Transforms/StructurizeCFG/AMDGPU/backedge-id-bug.ll vendor/llvm/dist-release_60/test/Transforms/StructurizeCFG/nested-loop-order.ll Modified: vendor/llvm/dist-release_60/docs/ReleaseNotes.rst ============================================================================== --- vendor/llvm/dist-release_60/docs/ReleaseNotes.rst Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/docs/ReleaseNotes.rst Thu Feb 1 21:07:55 2018 (r328734) @@ -15,7 +15,7 @@ Introduction ============ This document contains the release notes for the LLVM Compiler Infrastructure, -release 5.0.0. Here we describe the status of LLVM, including major improvements +release 6.0.0. Here we describe the status of LLVM, including major improvements from the previous release, improvements in various subprojects of LLVM, and some of the current users of the code. All LLVM releases may be downloaded from the `LLVM releases web site `_. Modified: vendor/llvm/dist-release_60/include/llvm/Analysis/ValueTracking.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/Analysis/ValueTracking.h Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/include/llvm/Analysis/ValueTracking.h Thu Feb 1 21:07:55 2018 (r328734) @@ -508,7 +508,8 @@ class Value; /// -> LHS = %a, RHS = i32 4, *CastOp = Instruction::SExt /// SelectPatternResult matchSelectPattern(Value *V, Value *&LHS, Value *&RHS, - Instruction::CastOps *CastOp = nullptr); + Instruction::CastOps *CastOp = nullptr, + unsigned Depth = 0); inline SelectPatternResult matchSelectPattern(const Value *V, const Value *&LHS, const Value *&RHS, Instruction::CastOps *CastOp = nullptr) { Modified: vendor/llvm/dist-release_60/include/llvm/MC/MCFragment.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/MC/MCFragment.h Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/include/llvm/MC/MCFragment.h Thu Feb 1 21:07:55 2018 (r328734) @@ -422,14 +422,21 @@ class MCFillFragment : public MCFragment { uint8_t Value; /// The number of bytes to insert. - uint64_t Size; + const MCExpr &Size; + /// Source location of the directive that this fragment was created for. + SMLoc Loc; + public: - MCFillFragment(uint8_t Value, uint64_t Size, MCSection *Sec = nullptr) - : MCFragment(FT_Fill, false, 0, Sec), Value(Value), Size(Size) {} + MCFillFragment(uint8_t Value, const MCExpr &Size, SMLoc Loc, + MCSection *Sec = nullptr) + : MCFragment(FT_Fill, false, 0, Sec), Value(Value), Size(Size), Loc(Loc) { + } uint8_t getValue() const { return Value; } - uint64_t getSize() const { return Size; } + const MCExpr &getSize() const { return Size; } + + SMLoc getLoc() const { return Loc; } static bool classof(const MCFragment *F) { return F->getKind() == MCFragment::FT_Fill; Modified: vendor/llvm/dist-release_60/include/llvm/MC/MCObjectStreamer.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/MC/MCObjectStreamer.h Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/include/llvm/MC/MCObjectStreamer.h Thu Feb 1 21:07:55 2018 (r328734) @@ -161,7 +161,6 @@ class MCObjectStreamer : public MCStreamer { (public) bool EmitRelocDirective(const MCExpr &Offset, StringRef Name, const MCExpr *Expr, SMLoc Loc) override; using MCStreamer::emitFill; - void emitFill(uint64_t NumBytes, uint8_t FillValue) override; void emitFill(const MCExpr &NumBytes, uint64_t FillValue, SMLoc Loc = SMLoc()) override; void emitFill(const MCExpr &NumValues, int64_t Size, int64_t Expr, Modified: vendor/llvm/dist-release_60/include/llvm/MC/MCStreamer.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/MC/MCStreamer.h Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/include/llvm/MC/MCStreamer.h Thu Feb 1 21:07:55 2018 (r328734) @@ -662,7 +662,7 @@ class MCStreamer { (public) /// \brief Emit NumBytes bytes worth of the value specified by FillValue. /// This implements directives such as '.space'. - virtual void emitFill(uint64_t NumBytes, uint8_t FillValue); + void emitFill(uint64_t NumBytes, uint8_t FillValue); /// \brief Emit \p Size bytes worth of the value specified by \p FillValue. /// Modified: vendor/llvm/dist-release_60/lib/Analysis/ValueTracking.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Analysis/ValueTracking.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Analysis/ValueTracking.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -4165,17 +4165,18 @@ static SelectPatternResult matchClamp(CmpInst::Predica /// a < c ? min(a,b) : min(b,c) ==> min(min(a,b),min(b,c)) static SelectPatternResult matchMinMaxOfMinMax(CmpInst::Predicate Pred, Value *CmpLHS, Value *CmpRHS, - Value *TrueVal, Value *FalseVal) { + Value *TVal, Value *FVal, + unsigned Depth) { // TODO: Allow FP min/max with nnan/nsz. assert(CmpInst::isIntPredicate(Pred) && "Expected integer comparison"); Value *A, *B; - SelectPatternResult L = matchSelectPattern(TrueVal, A, B); + SelectPatternResult L = matchSelectPattern(TVal, A, B, nullptr, Depth + 1); if (!SelectPatternResult::isMinOrMax(L.Flavor)) return {SPF_UNKNOWN, SPNB_NA, false}; Value *C, *D; - SelectPatternResult R = matchSelectPattern(FalseVal, C, D); + SelectPatternResult R = matchSelectPattern(FVal, C, D, nullptr, Depth + 1); if (L.Flavor != R.Flavor) return {SPF_UNKNOWN, SPNB_NA, false}; @@ -4214,7 +4215,7 @@ static SelectPatternResult matchMinMaxOfMinMax(CmpInst break; return {SPF_UNKNOWN, SPNB_NA, false}; default: - llvm_unreachable("Bad flavor while matching min/max"); + return {SPF_UNKNOWN, SPNB_NA, false}; } // a pred c ? m(a, b) : m(c, b) --> m(m(a, b), m(c, b)) @@ -4240,7 +4241,8 @@ static SelectPatternResult matchMinMaxOfMinMax(CmpInst static SelectPatternResult matchMinMax(CmpInst::Predicate Pred, Value *CmpLHS, Value *CmpRHS, Value *TrueVal, Value *FalseVal, - Value *&LHS, Value *&RHS) { + Value *&LHS, Value *&RHS, + unsigned Depth) { // Assume success. If there's no match, callers should not use these anyway. LHS = TrueVal; RHS = FalseVal; @@ -4249,7 +4251,7 @@ static SelectPatternResult matchMinMax(CmpInst::Predic if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN) return SPR; - SPR = matchMinMaxOfMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal); + SPR = matchMinMaxOfMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, Depth); if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN) return SPR; @@ -4313,7 +4315,8 @@ static SelectPatternResult matchSelectPattern(CmpInst: FastMathFlags FMF, Value *CmpLHS, Value *CmpRHS, Value *TrueVal, Value *FalseVal, - Value *&LHS, Value *&RHS) { + Value *&LHS, Value *&RHS, + unsigned Depth) { LHS = CmpLHS; RHS = CmpRHS; @@ -4429,7 +4432,7 @@ static SelectPatternResult matchSelectPattern(CmpInst: } if (CmpInst::isIntPredicate(Pred)) - return matchMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, LHS, RHS); + return matchMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, LHS, RHS, Depth); // According to (IEEE 754-2008 5.3.1), minNum(0.0, -0.0) and similar // may return either -0.0 or 0.0, so fcmp/select pair has stricter @@ -4550,7 +4553,11 @@ static Value *lookThroughCast(CmpInst *CmpI, Value *V1 } SelectPatternResult llvm::matchSelectPattern(Value *V, Value *&LHS, Value *&RHS, - Instruction::CastOps *CastOp) { + Instruction::CastOps *CastOp, + unsigned Depth) { + if (Depth >= MaxDepth) + return {SPF_UNKNOWN, SPNB_NA, false}; + SelectInst *SI = dyn_cast(V); if (!SI) return {SPF_UNKNOWN, SPNB_NA, false}; @@ -4579,7 +4586,7 @@ SelectPatternResult llvm::matchSelectPattern(Value *V, FMF.setNoSignedZeros(); return ::matchSelectPattern(Pred, FMF, CmpLHS, CmpRHS, cast(TrueVal)->getOperand(0), C, - LHS, RHS); + LHS, RHS, Depth); } if (Value *C = lookThroughCast(CmpI, FalseVal, TrueVal, CastOp)) { // If this is a potential fmin/fmax with a cast to integer, then ignore @@ -4588,11 +4595,11 @@ SelectPatternResult llvm::matchSelectPattern(Value *V, FMF.setNoSignedZeros(); return ::matchSelectPattern(Pred, FMF, CmpLHS, CmpRHS, C, cast(FalseVal)->getOperand(0), - LHS, RHS); + LHS, RHS, Depth); } } return ::matchSelectPattern(Pred, FMF, CmpLHS, CmpRHS, TrueVal, FalseVal, - LHS, RHS); + LHS, RHS, Depth); } /// Return true if "icmp Pred LHS RHS" is always true. Modified: vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/IRTranslator.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/IRTranslator.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/IRTranslator.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -812,6 +812,10 @@ bool IRTranslator::translateCall(const User &U, Machin auto TII = MF->getTarget().getIntrinsicInfo(); const Function *F = CI.getCalledFunction(); + // FIXME: support Windows dllimport function calls. + if (F && F->hasDLLImportStorageClass()) + return false; + if (CI.isInlineAsm()) return translateInlineAsm(CI, MIRBuilder); Modified: vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/LegalizerHelper.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -661,7 +661,24 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigne } case TargetOpcode::G_FCONSTANT: { unsigned DstExt = MRI.createGenericVirtualRegister(WideTy); - MIRBuilder.buildFConstant(DstExt, *MI.getOperand(1).getFPImm()); + const ConstantFP *CFP = MI.getOperand(1).getFPImm(); + APFloat Val = CFP->getValueAPF(); + LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); + auto LLT2Sem = [](LLT Ty) { + switch (Ty.getSizeInBits()) { + case 32: + return &APFloat::IEEEsingle(); + break; + case 64: + return &APFloat::IEEEdouble(); + break; + default: + llvm_unreachable("Unhandled fp widen type"); + } + }; + bool LosesInfo; + Val.convert(*LLT2Sem(WideTy), APFloat::rmTowardZero, &LosesInfo); + MIRBuilder.buildFConstant(DstExt, *ConstantFP::get(Ctx, Val)); MIRBuilder.buildFPTrunc(MI.getOperand(0).getReg(), DstExt); MI.eraseFromParent(); return Legalized; Modified: vendor/llvm/dist-release_60/lib/CodeGen/RegAllocFast.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/RegAllocFast.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/CodeGen/RegAllocFast.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -193,9 +193,10 @@ namespace { void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg); void usePhysReg(MachineOperand &MO); - void definePhysReg(MachineInstr &MI, MCPhysReg PhysReg, RegState NewState); + void definePhysReg(MachineBasicBlock::iterator MI, MCPhysReg PhysReg, + RegState NewState); unsigned calcSpillCost(MCPhysReg PhysReg) const; - void assignVirtToPhysReg(LiveReg&, MCPhysReg PhysReg); + void assignVirtToPhysReg(LiveReg &, MCPhysReg PhysReg); LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); @@ -434,8 +435,8 @@ void RegAllocFast::usePhysReg(MachineOperand &MO) { /// Mark PhysReg as reserved or free after spilling any virtregs. This is very /// similar to defineVirtReg except the physreg is reserved instead of /// allocated. -void RegAllocFast::definePhysReg(MachineInstr &MI, MCPhysReg PhysReg, - RegState NewState) { +void RegAllocFast::definePhysReg(MachineBasicBlock::iterator MI, + MCPhysReg PhysReg, RegState NewState) { markRegUsedInInstr(PhysReg); switch (unsigned VirtReg = PhysRegState[PhysReg]) { case regDisabled: @@ -857,7 +858,7 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBloc // Add live-in registers as live. for (const MachineBasicBlock::RegisterMaskPair LI : MBB.liveins()) if (MRI->isAllocatable(LI.PhysReg)) - definePhysReg(*MII, LI.PhysReg, regReserved); + definePhysReg(MII, LI.PhysReg, regReserved); VirtDead.clear(); Coalesced.clear(); Modified: vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -1380,8 +1380,10 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Func FastISelFailed = false; // Initialize the Fast-ISel state, if needed. FastISel *FastIS = nullptr; - if (TM.Options.EnableFastISel) + if (TM.Options.EnableFastISel) { + DEBUG(dbgs() << "Enabling fast-isel\n"); FastIS = TLI->createFastISel(*FuncInfo, LibInfo); + } setupSwiftErrorVals(Fn, TLI, FuncInfo); Modified: vendor/llvm/dist-release_60/lib/CodeGen/TargetPassConfig.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/TargetPassConfig.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/CodeGen/TargetPassConfig.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -717,6 +717,8 @@ bool TargetPassConfig::addCoreISelPasses() { if (EnableGlobalISel == cl::BOU_TRUE || (EnableGlobalISel == cl::BOU_UNSET && isGlobalISelEnabled() && EnableFastISelOption != cl::BOU_TRUE)) { + TM->setFastISel(false); + if (addIRTranslator()) return true; Modified: vendor/llvm/dist-release_60/lib/MC/MCAsmStreamer.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCAsmStreamer.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/MCAsmStreamer.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -192,9 +192,6 @@ class MCAsmStreamer final : public MCStreamer { (publi void EmitGPRel32Value(const MCExpr *Value) override; - - void emitFill(uint64_t NumBytes, uint8_t FillValue) override; - void emitFill(const MCExpr &NumBytes, uint64_t FillValue, SMLoc Loc = SMLoc()) override; @@ -965,17 +962,12 @@ void MCAsmStreamer::EmitGPRel32Value(const MCExpr *Val EmitEOL(); } -/// emitFill - Emit NumBytes bytes worth of the value specified by -/// FillValue. This implements directives such as '.space'. -void MCAsmStreamer::emitFill(uint64_t NumBytes, uint8_t FillValue) { - if (NumBytes == 0) return; - - const MCExpr *E = MCConstantExpr::create(NumBytes, getContext()); - emitFill(*E, FillValue); -} - void MCAsmStreamer::emitFill(const MCExpr &NumBytes, uint64_t FillValue, SMLoc Loc) { + int64_t IntNumBytes; + if (NumBytes.evaluateAsAbsolute(IntNumBytes) && IntNumBytes == 0) + return; + if (const char *ZeroDirective = MAI->getZeroDirective()) { // FIXME: Emit location directives OS << ZeroDirective; Modified: vendor/llvm/dist-release_60/lib/MC/MCAssembler.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCAssembler.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/MCAssembler.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -281,8 +281,18 @@ uint64_t MCAssembler::computeFragmentSize(const MCAsmL return cast(F).getContents().size(); case MCFragment::FT_CompactEncodedInst: return cast(F).getContents().size(); - case MCFragment::FT_Fill: - return cast(F).getSize(); + case MCFragment::FT_Fill: { + auto &FF = cast(F); + int64_t Size = 0; + if (!FF.getSize().evaluateAsAbsolute(Size, Layout)) + getContext().reportError(FF.getLoc(), + "expected assembly-time absolute expression"); + if (Size < 0) { + getContext().reportError(FF.getLoc(), "invalid number of bytes"); + return 0; + } + return Size; + } case MCFragment::FT_LEB: return cast(F).getContents().size(); @@ -540,7 +550,7 @@ static void writeFragment(const MCAssembler &Asm, cons for (unsigned I = 1; I < MaxChunkSize; ++I) Data[I] = Data[0]; - uint64_t Size = FF.getSize(); + uint64_t Size = FragmentSize; for (unsigned ChunkSize = MaxChunkSize; ChunkSize; ChunkSize /= 2) { StringRef Ref(Data, ChunkSize); for (uint64_t I = 0, E = Size / ChunkSize; I != E; ++I) Modified: vendor/llvm/dist-release_60/lib/MC/MCMachOStreamer.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCMachOStreamer.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/MCMachOStreamer.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -411,29 +411,19 @@ void MCMachOStreamer::EmitLocalCommonSymbol(MCSymbol * void MCMachOStreamer::EmitZerofill(MCSection *Section, MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment) { - getAssembler().registerSection(*Section); - - // The symbol may not be present, which only creates the section. - if (!Symbol) - return; - // On darwin all virtual sections have zerofill type. assert(Section->isVirtualSection() && "Section does not have zerofill type!"); - assert(Symbol->isUndefined() && "Cannot define a symbol twice!"); + PushSection(); + SwitchSection(Section); - getAssembler().registerSymbol(*Symbol); - - // Emit an align fragment if necessary. - if (ByteAlignment != 1) - new MCAlignFragment(ByteAlignment, 0, 0, ByteAlignment, Section); - - MCFragment *F = new MCFillFragment(0, Size, Section); - Symbol->setFragment(F); - - // Update the maximum alignment on the zero fill section if necessary. - if (ByteAlignment > Section->getAlignment()) - Section->setAlignment(ByteAlignment); + // The symbol may not be present, which only creates the section. + if (Symbol) { + EmitValueToAlignment(ByteAlignment, 0, 1, 0); + EmitLabel(Symbol); + EmitZeros(Size); + } + PopSection(); } // This should always be called with the thread local bss section. Like the Modified: vendor/llvm/dist-release_60/lib/MC/MCObjectStreamer.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCObjectStreamer.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/MCObjectStreamer.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -577,28 +577,13 @@ bool MCObjectStreamer::EmitRelocDirective(const MCExpr return false; } -void MCObjectStreamer::emitFill(uint64_t NumBytes, uint8_t FillValue) { - assert(getCurrentSectionOnly() && "need a section"); - insert(new MCFillFragment(FillValue, NumBytes)); -} - void MCObjectStreamer::emitFill(const MCExpr &NumBytes, uint64_t FillValue, SMLoc Loc) { MCDataFragment *DF = getOrCreateDataFragment(); flushPendingLabels(DF, DF->getContents().size()); - int64_t IntNumBytes; - if (!NumBytes.evaluateAsAbsolute(IntNumBytes, getAssembler())) { - getContext().reportError(Loc, "expected absolute expression"); - return; - } - - if (IntNumBytes <= 0) { - getContext().reportError(Loc, "invalid number of bytes"); - return; - } - - emitFill(IntNumBytes, FillValue); + assert(getCurrentSectionOnly() && "need a section"); + insert(new MCFillFragment(FillValue, NumBytes, Loc)); } void MCObjectStreamer::emitFill(const MCExpr &NumValues, int64_t Size, Modified: vendor/llvm/dist-release_60/lib/MC/MCStreamer.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCStreamer.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/MCStreamer.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -184,8 +184,7 @@ void MCStreamer::EmitGPRel32Value(const MCExpr *Value) /// Emit NumBytes bytes worth of the value specified by FillValue. /// This implements directives such as '.space'. void MCStreamer::emitFill(uint64_t NumBytes, uint8_t FillValue) { - for (uint64_t i = 0, e = NumBytes; i != e; ++i) - EmitIntValue(FillValue, 1); + emitFill(*MCConstantExpr::create(NumBytes, getContext()), FillValue); } void MCStreamer::emitFill(uint64_t NumValues, int64_t Size, int64_t Expr) { Modified: vendor/llvm/dist-release_60/lib/MC/MCWinCOFFStreamer.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCWinCOFFStreamer.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/MCWinCOFFStreamer.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -257,20 +257,13 @@ void MCWinCOFFStreamer::EmitLocalCommonSymbol(MCSymbol auto *Symbol = cast(S); MCSection *Section = getContext().getObjectFileInfo()->getBSSSection(); - getAssembler().registerSection(*Section); - if (Section->getAlignment() < ByteAlignment) - Section->setAlignment(ByteAlignment); - - getAssembler().registerSymbol(*Symbol); + PushSection(); + SwitchSection(Section); + EmitValueToAlignment(ByteAlignment, 0, 1, 0); + EmitLabel(Symbol); Symbol->setExternal(false); - - if (ByteAlignment != 1) - new MCAlignFragment(ByteAlignment, /*Value=*/0, /*ValueSize=*/0, - ByteAlignment, Section); - - MCFillFragment *Fragment = new MCFillFragment( - /*Value=*/0, Size, Section); - Symbol->setFragment(Fragment); + EmitZeros(Size); + PopSection(); } void MCWinCOFFStreamer::EmitZerofill(MCSection *Section, MCSymbol *Symbol, Modified: vendor/llvm/dist-release_60/lib/MC/WasmObjectWriter.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/WasmObjectWriter.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/MC/WasmObjectWriter.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -528,7 +528,10 @@ static void addData(SmallVectorImpl &DataBytes, Align->getMaxBytesToEmit()); DataBytes.resize(Size, Value); } else if (auto *Fill = dyn_cast(&Frag)) { - DataBytes.insert(DataBytes.end(), Fill->getSize(), Fill->getValue()); + int64_t Size; + if (!Fill->getSize().evaluateAsAbsolute(Size)) + llvm_unreachable("The fill should be an assembler constant"); + DataBytes.insert(DataBytes.end(), Size, Fill->getValue()); } else { const auto &DataFrag = cast(Frag); const SmallVectorImpl &Contents = DataFrag.getContents(); Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FastISel.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FastISel.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FastISel.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -476,26 +476,27 @@ unsigned AArch64FastISel::materializeGV(const GlobalVa // ADRP + LDRX BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP), ADRPReg) - .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE); + .addGlobalAddress(GV, 0, AArch64II::MO_PAGE | OpFlags); ResultReg = createResultReg(&AArch64::GPR64RegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui), ResultReg) - .addReg(ADRPReg) - .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF | - AArch64II::MO_NC); + .addReg(ADRPReg) + .addGlobalAddress(GV, 0, + AArch64II::MO_PAGEOFF | AArch64II::MO_NC | OpFlags); } else { // ADRP + ADDX BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP), ADRPReg) - .addGlobalAddress(GV, 0, AArch64II::MO_PAGE); + .addGlobalAddress(GV, 0, AArch64II::MO_PAGE | OpFlags); ResultReg = createResultReg(&AArch64::GPR64spRegClass); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri), ResultReg) - .addReg(ADRPReg) - .addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC) - .addImm(0); + .addReg(ADRPReg) + .addGlobalAddress(GV, 0, + AArch64II::MO_PAGEOFF | AArch64II::MO_NC | OpFlags) + .addImm(0); } return ResultReg; } Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstructionSelector.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -929,6 +929,12 @@ bool AArch64InstructionSelector::select(MachineInstr & return false; } + // FIXME: PR36018: Volatile loads in some cases are incorrectly selected by + // folding with an extend. Until we have a G_SEXTLOAD solution bail out if + // we hit one. + if (Opcode == TargetOpcode::G_LOAD && MemOp.isVolatile()) + return false; + const unsigned PtrReg = I.getOperand(1).getReg(); #ifndef NDEBUG const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64Subtarget.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64Subtarget.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64Subtarget.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -189,15 +189,18 @@ AArch64Subtarget::ClassifyGlobalReference(const Global if (TM.getCodeModel() == CodeModel::Large && isTargetMachO()) return AArch64II::MO_GOT; + unsigned Flags = GV->hasDLLImportStorageClass() ? AArch64II::MO_DLLIMPORT + : AArch64II::MO_NO_FLAG; + if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) - return AArch64II::MO_GOT; + return AArch64II::MO_GOT | Flags; // The small code model's direct accesses use ADRP, which cannot // necessarily produce the value 0 (if the code is above 4GB). if (useSmallAddressing() && GV->hasExternalWeakLinkage()) - return AArch64II::MO_GOT; + return AArch64II::MO_GOT | Flags; - return AArch64II::MO_NO_FLAG; + return Flags; } unsigned char AArch64Subtarget::classifyGlobalFunctionReference( Modified: vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInsertSkips.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInsertSkips.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInsertSkips.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -210,65 +210,73 @@ void SIInsertSkips::kill(MachineInstr &MI) { switch (MI.getOperand(2).getImm()) { case ISD::SETOEQ: case ISD::SETEQ: - Opcode = AMDGPU::V_CMPX_EQ_F32_e32; + Opcode = AMDGPU::V_CMPX_EQ_F32_e64; break; case ISD::SETOGT: case ISD::SETGT: - Opcode = AMDGPU::V_CMPX_LT_F32_e32; + Opcode = AMDGPU::V_CMPX_LT_F32_e64; break; case ISD::SETOGE: case ISD::SETGE: - Opcode = AMDGPU::V_CMPX_LE_F32_e32; + Opcode = AMDGPU::V_CMPX_LE_F32_e64; break; case ISD::SETOLT: case ISD::SETLT: - Opcode = AMDGPU::V_CMPX_GT_F32_e32; + Opcode = AMDGPU::V_CMPX_GT_F32_e64; break; case ISD::SETOLE: case ISD::SETLE: - Opcode = AMDGPU::V_CMPX_GE_F32_e32; + Opcode = AMDGPU::V_CMPX_GE_F32_e64; break; case ISD::SETONE: case ISD::SETNE: - Opcode = AMDGPU::V_CMPX_LG_F32_e32; + Opcode = AMDGPU::V_CMPX_LG_F32_e64; break; case ISD::SETO: - Opcode = AMDGPU::V_CMPX_O_F32_e32; + Opcode = AMDGPU::V_CMPX_O_F32_e64; break; case ISD::SETUO: - Opcode = AMDGPU::V_CMPX_U_F32_e32; + Opcode = AMDGPU::V_CMPX_U_F32_e64; break; case ISD::SETUEQ: - Opcode = AMDGPU::V_CMPX_NLG_F32_e32; + Opcode = AMDGPU::V_CMPX_NLG_F32_e64; break; case ISD::SETUGT: - Opcode = AMDGPU::V_CMPX_NGE_F32_e32; + Opcode = AMDGPU::V_CMPX_NGE_F32_e64; break; case ISD::SETUGE: - Opcode = AMDGPU::V_CMPX_NGT_F32_e32; + Opcode = AMDGPU::V_CMPX_NGT_F32_e64; break; case ISD::SETULT: - Opcode = AMDGPU::V_CMPX_NLE_F32_e32; + Opcode = AMDGPU::V_CMPX_NLE_F32_e64; break; case ISD::SETULE: - Opcode = AMDGPU::V_CMPX_NLT_F32_e32; + Opcode = AMDGPU::V_CMPX_NLT_F32_e64; break; case ISD::SETUNE: - Opcode = AMDGPU::V_CMPX_NEQ_F32_e32; + Opcode = AMDGPU::V_CMPX_NEQ_F32_e64; break; default: llvm_unreachable("invalid ISD:SET cond code"); } - // TODO: Allow this: - if (!MI.getOperand(0).isReg() || - !TRI->isVGPR(MBB.getParent()->getRegInfo(), - MI.getOperand(0).getReg())) - llvm_unreachable("SI_KILL operand should be a VGPR"); + assert(MI.getOperand(0).isReg()); - BuildMI(MBB, &MI, DL, TII->get(Opcode)) - .add(MI.getOperand(1)) - .add(MI.getOperand(0)); + if (TRI->isVGPR(MBB.getParent()->getRegInfo(), + MI.getOperand(0).getReg())) { + Opcode = AMDGPU::getVOPe32(Opcode); + BuildMI(MBB, &MI, DL, TII->get(Opcode)) + .add(MI.getOperand(1)) + .add(MI.getOperand(0)); + } else { + BuildMI(MBB, &MI, DL, TII->get(Opcode)) + .addReg(AMDGPU::VCC, RegState::Define) + .addImm(0) // src0 modifiers + .add(MI.getOperand(1)) + .addImm(0) // src1 modifiers + .add(MI.getOperand(0)) + .addImm(0); // omod + } break; } case AMDGPU::SI_KILL_I1_TERMINATOR: { Modified: vendor/llvm/dist-release_60/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -39,11 +39,11 @@ void X86IntelInstPrinter::printInst(const MCInst *MI, const MCSubtargetInfo &STI) { const MCInstrDesc &Desc = MII.get(MI->getOpcode()); uint64_t TSFlags = Desc.TSFlags; + unsigned Flags = MI->getFlags(); - if (TSFlags & X86II::LOCK) + if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) OS << "\tlock\t"; - unsigned Flags = MI->getFlags(); if (Flags & X86::IP_HAS_REPEAT_NE) OS << "\trepne\t"; else if (Flags & X86::IP_HAS_REPEAT) Modified: vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -31776,9 +31776,10 @@ static SDValue combineSelect(SDNode *N, SelectionDAG & // Check all uses of the condition operand to check whether it will be // consumed by non-BLEND instructions. Those may require that all bits // are set properly. - for (SDNode *U : Cond->uses()) { + for (SDNode::use_iterator UI = Cond->use_begin(), UE = Cond->use_end(); + UI != UE; ++UI) { // TODO: Add other opcodes eventually lowered into BLEND. - if (U->getOpcode() != ISD::VSELECT) + if (UI->getOpcode() != ISD::VSELECT || UI.getOperandNo() != 0) return SDValue(); } Modified: vendor/llvm/dist-release_60/lib/Transforms/Scalar/CallSiteSplitting.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Transforms/Scalar/CallSiteSplitting.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Transforms/Scalar/CallSiteSplitting.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -142,10 +142,11 @@ recordConditions(const CallSite &CS, BasicBlock *Pred, recordCondition(CS, Pred, CS.getInstruction()->getParent(), Conditions); BasicBlock *From = Pred; BasicBlock *To = Pred; - SmallPtrSet Visited = {From}; + SmallPtrSet Visited; while (!Visited.count(From->getSinglePredecessor()) && (From = From->getSinglePredecessor())) { recordCondition(CS, From, To, Conditions); + Visited.insert(From); To = From; } } Modified: vendor/llvm/dist-release_60/lib/Transforms/Scalar/StructurizeCFG.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Transforms/Scalar/StructurizeCFG.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Transforms/Scalar/StructurizeCFG.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -14,6 +14,7 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Analysis/DivergenceAnalysis.h" +#include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/RegionInfo.h" #include "llvm/Analysis/RegionIterator.h" #include "llvm/Analysis/RegionPass.h" @@ -176,8 +177,9 @@ class StructurizeCFG : public RegionPass { Region *ParentRegion; DominatorTree *DT; + LoopInfo *LI; - std::deque Order; + SmallVector Order; BBSet Visited; BBPhiMap DeletedPhis; @@ -202,7 +204,7 @@ class StructurizeCFG : public RegionPass { void gatherPredicates(RegionNode *N); - void analyzeNode(RegionNode *N); + void collectInfos(); void insertConditions(bool Loops); @@ -256,6 +258,7 @@ class StructurizeCFG : public RegionPass { AU.addRequired(); AU.addRequiredID(LowerSwitchID); AU.addRequired(); + AU.addRequired(); AU.addPreserved(); RegionPass::getAnalysisUsage(AU); @@ -289,17 +292,55 @@ bool StructurizeCFG::doInitialization(Region *R, RGPas /// \brief Build up the general order of nodes void StructurizeCFG::orderNodes() { - assert(Visited.empty()); - assert(Predicates.empty()); - assert(Loops.empty()); - assert(LoopPreds.empty()); + ReversePostOrderTraversal RPOT(ParentRegion); + SmallDenseMap LoopBlocks; - // This must be RPO order for the back edge detection to work - for (RegionNode *RN : ReversePostOrderTraversal(ParentRegion)) { - // FIXME: Is there a better order to use for structurization? - Order.push_back(RN); - analyzeNode(RN); + // The reverse post-order traversal of the list gives us an ordering close + // to what we want. The only problem with it is that sometimes backedges + // for outer loops will be visited before backedges for inner loops. + for (RegionNode *RN : RPOT) { + BasicBlock *BB = RN->getEntry(); + Loop *Loop = LI->getLoopFor(BB); + ++LoopBlocks[Loop]; } + + unsigned CurrentLoopDepth = 0; + Loop *CurrentLoop = nullptr; + for (auto I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { + BasicBlock *BB = (*I)->getEntry(); + unsigned LoopDepth = LI->getLoopDepth(BB); + + if (is_contained(Order, *I)) + continue; + + if (LoopDepth < CurrentLoopDepth) { + // Make sure we have visited all blocks in this loop before moving back to + // the outer loop. + + auto LoopI = I; + while (unsigned &BlockCount = LoopBlocks[CurrentLoop]) { + LoopI++; + BasicBlock *LoopBB = (*LoopI)->getEntry(); + if (LI->getLoopFor(LoopBB) == CurrentLoop) { + --BlockCount; + Order.push_back(*LoopI); + } + } + } + + CurrentLoop = LI->getLoopFor(BB); + if (CurrentLoop) + LoopBlocks[CurrentLoop]--; + + CurrentLoopDepth = LoopDepth; + Order.push_back(*I); + } + + // This pass originally used a post-order traversal and then operated on + // the list in reverse. Now that we are using a reverse post-order traversal + // rather than re-working the whole pass to operate on the list in order, + // we just reverse the list and continue to operate on it in reverse. + std::reverse(Order.begin(), Order.end()); } /// \brief Determine the end of the loops @@ -425,19 +466,32 @@ void StructurizeCFG::gatherPredicates(RegionNode *N) { } /// \brief Collect various loop and predicate infos -void StructurizeCFG::analyzeNode(RegionNode *RN) { - DEBUG(dbgs() << "Visiting: " - << (RN->isSubRegion() ? "SubRegion with entry: " : "") - << RN->getEntry()->getName() << '\n'); +void StructurizeCFG::collectInfos() { + // Reset predicate + Predicates.clear(); - // Analyze all the conditions leading to a node - gatherPredicates(RN); + // and loop infos + Loops.clear(); + LoopPreds.clear(); - // Remember that we've seen this node - Visited.insert(RN->getEntry()); + // Reset the visited nodes + Visited.clear(); - // Find the last back edges - analyzeLoops(RN); + for (RegionNode *RN : reverse(Order)) { + DEBUG(dbgs() << "Visiting: " + << (RN->isSubRegion() ? "SubRegion with entry: " : "") + << RN->getEntry()->getName() << " Loop Depth: " + << LI->getLoopDepth(RN->getEntry()) << "\n"); + + // Analyze all the conditions leading to a node + gatherPredicates(RN); + + // Remember that we've seen this node + Visited.insert(RN->getEntry()); + + // Find the last back edges + analyzeLoops(RN); + } } /// \brief Insert the missing branch conditions @@ -610,7 +664,7 @@ void StructurizeCFG::changeExit(RegionNode *Node, Basi BasicBlock *StructurizeCFG::getNextFlow(BasicBlock *Dominator) { LLVMContext &Context = Func->getContext(); BasicBlock *Insert = Order.empty() ? ParentRegion->getExit() : - Order.front()->getEntry(); + Order.back()->getEntry(); BasicBlock *Flow = BasicBlock::Create(Context, FlowBlockName, Func, Insert); DT->addNewBlock(Flow, Dominator); @@ -690,8 +744,7 @@ bool StructurizeCFG::isPredictableTrue(RegionNode *Nod /// Take one node from the order vector and wire it up void StructurizeCFG::wireFlow(bool ExitUseAllowed, BasicBlock *LoopEnd) { - RegionNode *Node = Order.front(); - Order.pop_front(); + RegionNode *Node = Order.pop_back_val(); Visited.insert(Node->getEntry()); if (isPredictableTrue(Node)) { @@ -715,7 +768,7 @@ void StructurizeCFG::wireFlow(bool ExitUseAllowed, PrevNode = Node; while (!Order.empty() && !Visited.count(LoopEnd) && - dominatesPredicates(Entry, Order.front())) { + dominatesPredicates(Entry, Order.back())) { handleLoops(false, LoopEnd); } @@ -726,7 +779,7 @@ void StructurizeCFG::wireFlow(bool ExitUseAllowed, void StructurizeCFG::handleLoops(bool ExitUseAllowed, BasicBlock *LoopEnd) { - RegionNode *Node = Order.front(); + RegionNode *Node = Order.back(); BasicBlock *LoopStart = Node->getEntry(); if (!Loops.count(LoopStart)) { @@ -871,9 +924,10 @@ bool StructurizeCFG::runOnRegion(Region *R, RGPassMana ParentRegion = R; DT = &getAnalysis().getDomTree(); + LI = &getAnalysis().getLoopInfo(); orderNodes(); - + collectInfos(); createFlow(); insertConditions(false); insertConditions(true); Modified: vendor/llvm/dist-release_60/lib/Transforms/Utils/ValueMapper.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Transforms/Utils/ValueMapper.cpp Thu Feb 1 21:06:28 2018 (r328733) +++ vendor/llvm/dist-release_60/lib/Transforms/Utils/ValueMapper.cpp Thu Feb 1 21:07:55 2018 (r328734) @@ -25,6 +25,7 @@ #include "llvm/IR/CallSite.h" #include "llvm/IR/Constant.h" #include "llvm/IR/Constants.h" +#include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Function.h" #include "llvm/IR/GlobalAlias.h" @@ -536,13 +537,23 @@ Optional MDNodeMapper::tryToMapOperand(con return None; } +static Metadata *cloneOrBuildODR(const MDNode &N) { + auto *CT = dyn_cast(&N); + // If ODR type uniquing is enabled, we would have uniqued composite types + // with identifiers during bitcode reading, so we can just use CT. + if (CT && CT->getContext().isODRUniquingDebugTypes() && + CT->getIdentifier() != "") + return const_cast(CT); + return MDNode::replaceWithDistinct(N.clone()); +} + MDNode *MDNodeMapper::mapDistinctNode(const MDNode &N) { assert(N.isDistinct() && "Expected a distinct node"); assert(!M.getVM().getMappedMD(&N) && "Expected an unmapped node"); - DistinctWorklist.push_back(cast( - (M.Flags & RF_MoveDistinctMDs) - ? M.mapToSelf(&N) - : M.mapToMetadata(&N, MDNode::replaceWithDistinct(N.clone())))); + DistinctWorklist.push_back( + cast((M.Flags & RF_MoveDistinctMDs) + ? M.mapToSelf(&N) + : M.mapToMetadata(&N, cloneOrBuildODR(N)))); return DistinctWorklist.back(); } Added: vendor/llvm/dist-release_60/test/Analysis/ValueTracking/select-pattern.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_60/test/Analysis/ValueTracking/select-pattern.ll Thu Feb 1 21:07:55 2018 (r328734) @@ -0,0 +1,46 @@ +; RUN: opt -simplifycfg < %s -S | FileCheck %s + +; The dead code would cause a select that had itself +; as an operand to be analyzed. This would then cause +; infinite recursion and eventual crash. + +define void @PR36045(i1 %t, i32* %b) { +; CHECK-LABEL: @PR36045( +; CHECK-NEXT: entry: +; CHECK-NEXT: ret void +; +entry: + br i1 %t, label %if, label %end + +if: + br i1 %t, label %unreach, label %pre + +unreach: + unreachable + +pre: + %p = phi i32 [ 70, %if ], [ %sel, %for ] + br label %for + +for: + %cmp = icmp sgt i32 %p, 8 + %add = add i32 %p, 2 + %sel = select i1 %cmp, i32 %p, i32 %add + %cmp21 = icmp ult i32 %sel, 21 + br i1 %cmp21, label %pre, label %for.end + +for.end: + br i1 %t, label %unreach2, label %then12 + +then12: + store i32 0, i32* %b + br label %unreach2 + +unreach2: + %spec = phi i32 [ %sel, %for.end ], [ 42, %then12 ] + unreachable + +end: + ret void +} + Added: vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/fallback-nofastisel.ll Thu Feb 1 21:07:55 2018 (r328734) @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=aarch64_be-- %s -o /dev/null -debug-only=isel -O0 2>&1 | FileCheck %s +; REQUIRES: asserts + +; This test uses big endian in order to force an abort since it's not currently supported for GISel. +; The purpose is to check that we don't fall back to FastISel. Checking the pass structure is insufficient +; because the FastISel is set up in the SelectionDAGISel, so it doesn't appear on the pass structure. + +; CHECK-NOT: Enabling fast-ise +define void @empty() { + ret void +} Added: vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ vendor/llvm/dist-release_60/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll Thu Feb 1 21:07:55 2018 (r328734) @@ -0,0 +1,14 @@ +; RUN: llc -O0 -mtriple=aarch64-apple-ios -o - %s | FileCheck %s + +@g = global i16 0, align 2 +declare void @bar(i32) + *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***