Date: Wed, 20 Jan 2016 17:08:01 +0000 (UTC) From: Glen Barber <gjb@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r294448 - in projects/release-pkg: share/misc sys/arm/arm sys/arm/conf sys/arm/mv sys/arm/mv/armada38x sys/arm/mv/armadaxp sys/arm64/conf sys/boot/fdt/dts/arm sys/conf sys/dev/fdt sys/d... Message-ID: <201601201708.u0KH81x1036388@repo.freebsd.org>
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Author: gjb Date: Wed Jan 20 17:08:01 2016 New Revision: 294448 URL: https://svnweb.freebsd.org/changeset/base/294448 Log: MFH Sponsored by: The FreeBSD Foundation Added: projects/release-pkg/sys/arm/conf/ARMADA38X - copied unchanged from r294447, head/sys/arm/conf/ARMADA38X projects/release-pkg/sys/arm/mv/armada38x/ - copied from r294447, head/sys/arm/mv/armada38x/ projects/release-pkg/sys/boot/fdt/dts/arm/armada-380.dtsi - copied unchanged from r294447, head/sys/boot/fdt/dts/arm/armada-380.dtsi projects/release-pkg/sys/boot/fdt/dts/arm/armada-385.dtsi - copied unchanged from r294447, head/sys/boot/fdt/dts/arm/armada-385.dtsi projects/release-pkg/sys/boot/fdt/dts/arm/armada-388-gp.dts - copied unchanged from r294447, head/sys/boot/fdt/dts/arm/armada-388-gp.dts projects/release-pkg/sys/boot/fdt/dts/arm/armada-388.dtsi - copied unchanged from r294447, head/sys/boot/fdt/dts/arm/armada-388.dtsi projects/release-pkg/sys/boot/fdt/dts/arm/armada-38x.dtsi - copied unchanged from r294447, head/sys/boot/fdt/dts/arm/armada-38x.dtsi Modified: projects/release-pkg/share/misc/committers-src.dot projects/release-pkg/share/misc/organization.dot projects/release-pkg/sys/arm/arm/gic.c projects/release-pkg/sys/arm/conf/DB-78XXX projects/release-pkg/sys/arm/conf/DB-88F5XXX projects/release-pkg/sys/arm/conf/DB-88F6XXX projects/release-pkg/sys/arm/conf/DOCKSTAR projects/release-pkg/sys/arm/conf/DREAMPLUG-1001 projects/release-pkg/sys/arm/conf/SHEEVAPLUG projects/release-pkg/sys/arm/conf/TS7800 projects/release-pkg/sys/arm/mv/armadaxp/armadaxp.c projects/release-pkg/sys/arm/mv/files.mv projects/release-pkg/sys/arm/mv/mv_common.c projects/release-pkg/sys/arm/mv/mv_machdep.c projects/release-pkg/sys/arm/mv/mv_pci.c projects/release-pkg/sys/arm/mv/mvreg.h projects/release-pkg/sys/arm/mv/mvvar.h projects/release-pkg/sys/arm/mv/mvwin.h projects/release-pkg/sys/arm/mv/timer.c projects/release-pkg/sys/arm/mv/twsi.c projects/release-pkg/sys/arm64/conf/GENERIC projects/release-pkg/sys/boot/fdt/dts/arm/db78460.dts projects/release-pkg/sys/boot/fdt/dts/arm/rk3188.dtsi projects/release-pkg/sys/boot/fdt/dts/arm/sun4i-a10.dtsi projects/release-pkg/sys/boot/fdt/dts/arm/sun7i-a20.dtsi projects/release-pkg/sys/conf/options.arm projects/release-pkg/sys/dev/fdt/fdt_common.c projects/release-pkg/sys/dev/ofw/ofw_bus_subr.c projects/release-pkg/sys/dev/pci/pcireg.h projects/release-pkg/sys/dev/uart/uart_dev_ns8250.c projects/release-pkg/sys/dev/usb/controller/ehci_mv.c projects/release-pkg/sys/dev/xen/netfront/netfront.c projects/release-pkg/sys/modules/ix/Makefile projects/release-pkg/sys/modules/ixlv/Makefile projects/release-pkg/sys/modules/ixv/Makefile projects/release-pkg/sys/netinet6/ip6_forward.c projects/release-pkg/sys/sys/ttydevsw.h Directory Properties: projects/release-pkg/ (props changed) projects/release-pkg/share/ (props changed) projects/release-pkg/sys/ (props changed) projects/release-pkg/sys/boot/ (props changed) projects/release-pkg/sys/conf/ (props changed) Modified: projects/release-pkg/share/misc/committers-src.dot ============================================================================== --- projects/release-pkg/share/misc/committers-src.dot Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/share/misc/committers-src.dot Wed Jan 20 17:08:01 2016 (r294448) @@ -316,6 +316,7 @@ weongyo [label="Weongyo Jeong\nweongyo@F wes [label="Wes Peters\nwes@FreeBSD.org\n1998/11/25"] whu [label="Wei Hu\nwhu@FreeBSD.org\n2015/02/11"] wkoszek [label="Wojciech A. Koszek\nwkoszek@FreeBSD.org\n2006/02/21"] +wma [label="Wojciech Macek\nwma@FreeBSD.org\n2016/01/18"] wollman [label="Garrett Wollman\nwollman@FreeBSD.org\n????/??/??"] wsalamon [label="Wayne Salamon\nwsalamon@FreeBSD.org\n2005/06/25"] yongari [label="Pyun YongHyeon\nyongari@FreeBSD.org\n2004/08/01"] @@ -391,6 +392,7 @@ cognet -> jceel cognet -> kevlo cognet -> ian cognet -> wkoszek +cognet -> wma cognet -> zbb cperciva -> eadler Modified: projects/release-pkg/share/misc/organization.dot ============================================================================== --- projects/release-pkg/share/misc/organization.dot Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/share/misc/organization.dot Wed Jan 20 17:08:01 2016 (r294448) @@ -30,7 +30,7 @@ coresecretary [label="Core Team Secretar doccommitters [label="Doc/www Committers\ndoc-committers@FreeBSD.org"] doceng [label="Documentation Engineering Team\ndoceng@FreeBSD.org\ngjb, blackend,\ngabor, hrs"] portscommitters [label="Ports Committers\nports-committers@FreeBSD.org"] -portmgr [label="Port Management Team\nportmgr@FreeBSD.org\nantoine, bapt, bdrewery,\nerwin, mat, swills"] +portmgr [label="Port Management Team\nportmgr@FreeBSD.org\nantoine, bapt, bdrewery,\nerwin, mat, swills,\nmiwi"] portmgrsecretary [label="Port Management Team Secretary\nportmgr-secretary@FreeBSD.org\nculot"] re [label="Primary Release Engineering Team\nre@FreeBSD.org\nkib, blackend, jpaetzel, hrs, kensmith"] secteam [label="Security Team\nsecteam@FreeBSD.org\nsimon, qingli, delphij,\nremko, philip, stas, cperciva,\ncsjp, rwatson, miwi, bz"] Modified: projects/release-pkg/sys/arm/arm/gic.c ============================================================================== --- projects/release-pkg/sys/arm/arm/gic.c Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/arm/gic.c Wed Jan 20 17:08:01 2016 (r294448) @@ -336,9 +336,11 @@ gic_decode_fdt(phandle_t iparent, pcell_ * 2 = high-to-low edge triggered * 4 = active high level-sensitive * 8 = active low level-sensitive - * The hardware only supports active-high-level or rising-edge. + * The hardware only supports active-high-level or rising-edge + * for SPIs */ - if (fdt32_to_cpu(intr[2]) & 0x0a) { + if (*interrupt >= GIC_FIRST_SPI && + fdt32_to_cpu(intr[2]) & 0x0a) { printf("unsupported trigger/polarity configuration " "0x%02x\n", fdt32_to_cpu(intr[2]) & 0x0f); } Copied: projects/release-pkg/sys/arm/conf/ARMADA38X (from r294447, head/sys/arm/conf/ARMADA38X) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/release-pkg/sys/arm/conf/ARMADA38X Wed Jan 20 17:08:01 2016 (r294448, copy of r294447, head/sys/arm/conf/ARMADA38X) @@ -0,0 +1,84 @@ +# +# Kernel configuration for Marvell Armada38x +# +# $FreeBSD$ +# + +include "../mv/armada38x/std.armada38x" +include "std.armv6" + +ident ARMADA38X + +options SOC_MV_ARMADA38X + +makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols +makeoptions WERROR="-Werror" + +options MD_ROOT +#makeoptions MFS_IMAGE=/path/to/miniroot +#options ROOTDEVNAME=\"ufs:md0\" +options ROOTDEVNAME=\"/dev/da0s1a\" + +options SCHED_ULE # ULE scheduler +#options SCHED_4BSD # 4BSD scheduler + +options SMP + +# Debugging +#options DEBUG +#options VERBOSE_SYSINIT +options ALT_BREAK_TO_DEBUGGER +options DDB +#options GDB +#options DIAGNOSTIC +options INVARIANTS # Enable calls of extra sanity checking +options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS +options KDB +options KDB_TRACE +#options WITNESS # Enable checks to detect deadlocks and cycles +#options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed +#options WITNESS_KDB +#options BOOTVERBOSE + +# Pseudo devices +device random +device pty +device loop +device md + +# Serial ports +device uart +device uart_ns8250 + +# Network +device ether +device vlan +device mii +device bpf +device re + +# PCI +device pci + +# Interrupt controllers +device gic + +# Timers +device mpcore_timer + +# USB +device usb +device ehci +device umass +device scbus +device pass +device da + +# I2C +device iic +device iicbus + +#FDT +options FDT +options FDT_DTB_STATIC +makeoptions FDT_DTS_FILE=armada-388-gp.dts Modified: projects/release-pkg/sys/arm/conf/DB-78XXX ============================================================================== --- projects/release-pkg/sys/arm/conf/DB-78XXX Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/conf/DB-78XXX Wed Jan 20 17:08:01 2016 (r294448) @@ -90,6 +90,9 @@ device mvs # NAND device nand +# GPIO +device gpio + # Flattened Device Tree options FDT options FDT_DTB_STATIC Modified: projects/release-pkg/sys/arm/conf/DB-88F5XXX ============================================================================== --- projects/release-pkg/sys/arm/conf/DB-88F5XXX Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/conf/DB-88F5XXX Wed Jan 20 17:08:01 2016 (r294448) @@ -88,6 +88,9 @@ device da # SATA device mvs +# GPIO +device gpio + # Flattened Device Tree options FDT makeoptions FDT_DTS_FILE=db88f5281.dts Modified: projects/release-pkg/sys/arm/conf/DB-88F6XXX ============================================================================== --- projects/release-pkg/sys/arm/conf/DB-88F6XXX Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/conf/DB-88F6XXX Wed Jan 20 17:08:01 2016 (r294448) @@ -94,6 +94,9 @@ device mvs # NAND device nand +# GPIO +device gpio + # Flattened Device Tree options FDT # Configure using FDT/DTB data options FDT_DTB_STATIC Modified: projects/release-pkg/sys/arm/conf/DOCKSTAR ============================================================================== --- projects/release-pkg/sys/arm/conf/DOCKSTAR Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/conf/DOCKSTAR Wed Jan 20 17:08:01 2016 (r294448) @@ -148,6 +148,9 @@ device pf device pflog device pfsync +# GPIO +device gpio + # ALTQ, required for PF options ALTQ # Basic ALTQ support options ALTQ_CBQ # Class Based Queueing Modified: projects/release-pkg/sys/arm/conf/DREAMPLUG-1001 ============================================================================== --- projects/release-pkg/sys/arm/conf/DREAMPLUG-1001 Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/conf/DREAMPLUG-1001 Wed Jan 20 17:08:01 2016 (r294448) @@ -122,6 +122,9 @@ device u3g # USB-based 3G modems (O device iic device iicbus +# GPIO +device gpio + # SATA device mvs device ahci Modified: projects/release-pkg/sys/arm/conf/SHEEVAPLUG ============================================================================== --- projects/release-pkg/sys/arm/conf/SHEEVAPLUG Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/conf/SHEEVAPLUG Wed Jan 20 17:08:01 2016 (r294448) @@ -82,6 +82,9 @@ device da # NAND device nand +# GPIO +device gpio + # Flattened Device Tree options FDT # Configure using FDT/DTB data options FDT_DTB_STATIC Modified: projects/release-pkg/sys/arm/conf/TS7800 ============================================================================== --- projects/release-pkg/sys/arm/conf/TS7800 Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/conf/TS7800 Wed Jan 20 17:08:01 2016 (r294448) @@ -76,6 +76,9 @@ device da # SATA device ata +# GPIO +device gpio + # Flattened Device Tree options FDT options FDT_DTB_STATIC Modified: projects/release-pkg/sys/arm/mv/armadaxp/armadaxp.c ============================================================================== --- projects/release-pkg/sys/arm/mv/armadaxp/armadaxp.c Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/mv/armadaxp/armadaxp.c Wed Jan 20 17:08:01 2016 (r294448) @@ -86,13 +86,6 @@ int platform_get_ncpus(void); #define COHER_FABRIC_CFU 0x28 #define COHER_FABRIC_CIB_CTRL 0x80 -/* XXX Make gpio driver optional and remove it */ -struct resource_spec mv_gpio_res[] = { - { SYS_RES_MEMORY, 0, RF_ACTIVE }, - { SYS_RES_IRQ, 0, RF_ACTIVE }, - { -1, 0 } -}; - struct vco_freq_ratio { uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */ uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */ Modified: projects/release-pkg/sys/arm/mv/files.mv ============================================================================== --- projects/release-pkg/sys/arm/mv/files.mv Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/mv/files.mv Wed Jan 20 17:08:01 2016 (r294448) @@ -12,7 +12,7 @@ # - JTAG/ICE # - Vector Floating Point (VFP) unit # -arm/mv/gpio.c standard +arm/mv/gpio.c optional gpio arm/mv/mv_common.c standard arm/mv/mv_localbus.c standard arm/mv/mv_machdep.c standard Modified: projects/release-pkg/sys/arm/mv/mv_common.c ============================================================================== --- projects/release-pkg/sys/arm/mv/mv_common.c Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/mv/mv_common.c Wed Jan 20 17:08:01 2016 (r294448) @@ -46,6 +46,7 @@ __FBSDID("$FreeBSD$"); #include <machine/bus.h> #include <machine/fdt.h> #include <machine/vmparam.h> +#include <machine/intr.h> #include <arm/mv/mvreg.h> #include <arm/mv/mvvar.h> @@ -104,6 +105,10 @@ static void decode_win_idma_dump(u_long static void decode_win_xor_dump(u_long base); static int fdt_get_ranges(const char *, void *, int, int *, int *); +#ifdef SOC_MV_ARMADA38X +int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, + int *trig, int *pol); +#endif static int win_cpu_from_dt(void); static int fdt_win_setup(void); @@ -260,7 +265,7 @@ write_cpu_ctrl(uint32_t reg, uint32_t va bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); } -#if defined(SOC_MV_ARMADAXP) +#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) uint32_t read_cpu_mp_clocks(uint32_t reg) { @@ -294,7 +299,7 @@ void cpu_reset(void) { -#if defined(SOC_MV_ARMADAXP) +#if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X) write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN); write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST); #else @@ -442,6 +447,15 @@ soc_identify(void) else if (r == 1) rev = "A1"; break; + case MV_DEV_88F6828: + dev = "Marvell 88F6828"; + break; + case MV_DEV_88F6820: + dev = "Marvell 88F6820"; + break; + case MV_DEV_88F6810: + dev = "Marvell 88F6810"; + break; case MV_DEV_MV78100_Z0: dev = "Marvell MV78100 Z0"; break; @@ -719,6 +733,9 @@ win_cpu_can_remap(int i) (dev == MV_DEV_88F5281 && i < 4) || (dev == MV_DEV_88F6281 && i < 4) || (dev == MV_DEV_88F6282 && i < 4) || + (dev == MV_DEV_88F6828 && i < 20) || + (dev == MV_DEV_88F6820 && i < 20) || + (dev == MV_DEV_88F6810 && i < 20) || (dev == MV_DEV_88RC8180 && i < 2) || (dev == MV_DEV_88F6781 && i < 4) || (dev == MV_DEV_MV78100_Z0 && i < 8) || @@ -2055,7 +2072,7 @@ fdt_win_setup(void) */ child = OF_peer(child); if ((child == 0) && (node == OF_finddevice("/"))) { - node = fdt_find_compatible(node, "simple-bus", 1); + node = fdt_find_compatible(node, "simple-bus", 0); if (node == 0) return (ENXIO); child = OF_child(node); @@ -2181,6 +2198,9 @@ fdt_pic_decode_ic(phandle_t node, pcell_ } fdt_pic_decode_t fdt_pic_table[] = { +#ifdef SOC_MV_ARMADA38X + &gic_decode_fdt, +#endif &fdt_pic_decode_ic, NULL }; @@ -2195,6 +2215,10 @@ get_sar_value(void) SAMPLE_AT_RESET_HI); sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, SAMPLE_AT_RESET_LO); +#elif defined(SOC_MV_ARMADA38X) + sar_high = 0; + sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, + SAMPLE_AT_RESET); #else /* * TODO: Add getting proper values for other SoC configurations Modified: projects/release-pkg/sys/arm/mv/mv_machdep.c ============================================================================== --- projects/release-pkg/sys/arm/mv/mv_machdep.c Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/mv/mv_machdep.c Wed Jan 20 17:08:01 2016 (r294448) @@ -66,6 +66,11 @@ static int platform_mpp_init(void); void armadaxp_init_coher_fabric(void); void armadaxp_l2_init(void); #endif +#if defined(SOC_MV_ARMADA38X) +int armada38x_win_set_iosync_barrier(void); +int armada38x_scu_enable(void); +int armada38x_open_bootrom_win(void); +#endif #define MPP_PIN_MAX 68 #define MPP_PIN_CELLS 2 @@ -249,6 +254,19 @@ platform_late_init(void) #endif armadaxp_l2_init(); #endif + +#if defined(SOC_MV_ARMADA38X) + /* Set IO Sync Barrier bit for all Mbus devices */ + if (armada38x_win_set_iosync_barrier() != 0) + printf("WARNING: could not map CPU Subsystem registers\n"); + if (armada38x_scu_enable() != 0) + printf("WARNING: could not enable SCU\n"); +#ifdef SMP + /* Open window to bootROM memory - needed for SMP */ + if (armada38x_open_bootrom_win() != 0) + printf("WARNING: could not open window to bootROM\n"); +#endif +#endif } #define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2) Modified: projects/release-pkg/sys/arm/mv/mv_pci.c ============================================================================== --- projects/release-pkg/sys/arm/mv/mv_pci.c Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/mv/mv_pci.c Wed Jan 20 17:08:01 2016 (r294448) @@ -1,7 +1,7 @@ /*- * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. * Copyright (c) 2010 The FreeBSD Foundation - * Copyright (c) 2010-2012 Semihalf + * Copyright (c) 2010-2015 Semihalf * All rights reserved. * * Developed by Semihalf. @@ -1016,6 +1016,25 @@ mv_pcib_maxslots(device_t dev) return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); } +static int +mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func) +{ +#if defined(SOC_MV_ARMADA38X) + struct mv_pcib_softc *sc = device_get_softc(dev); + uint32_t vendor, device; + + vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR, + PCIR_VENDOR_LENGTH); + device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE, + PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK; + + return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X); +#else + /* On platforms other than Armada38x, root link is always at slot 0 */ + return (slot == 0); +#endif +} + static uint32_t mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int bytes) @@ -1024,7 +1043,7 @@ mv_pcib_read_config(device_t dev, u_int /* Return ~0 if link is inactive or trying to read from Root */ if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & - PCIE_STATUS_LINK_DOWN) || (slot == 0)) + PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) return (~0U); return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); @@ -1038,7 +1057,7 @@ mv_pcib_write_config(device_t dev, u_int /* Return if link is inactive or trying to write to Root */ if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & - PCIE_STATUS_LINK_DOWN) || (slot == 0)) + PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) return; mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); Modified: projects/release-pkg/sys/arm/mv/mvreg.h ============================================================================== --- projects/release-pkg/sys/arm/mv/mvreg.h Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/mv/mvreg.h Wed Jan 20 17:08:01 2016 (r294448) @@ -34,6 +34,8 @@ #ifndef _MVREG_H_ #define _MVREG_H_ +#include <arm/mv/mvwin.h> + #if defined(SOC_MV_DISCOVERY) #define IRQ_CAUSE_ERROR 0x0 #define IRQ_CAUSE 0x4 @@ -123,8 +125,9 @@ /* * System reset */ -#if defined(SOC_MV_ARMADAXP) +#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) #define RSTOUTn_MASK 0x60 +#define RSTOUTn_MASK_WD 0x400 #define SYSTEM_SOFT_RESET 0x64 #define WD_RSTOUTn_MASK 0x4 #define WD_GLOBAL_MASK 0x00000100 @@ -217,8 +220,10 @@ #define CPU_TIMER0_AUTO 0x00000002 #define CPU_TIMER1_EN 0x00000004 #define CPU_TIMER1_AUTO 0x00000008 -#define CPU_TIMER_WD_EN 0x00000010 -#define CPU_TIMER_WD_AUTO 0x00000020 +#define CPU_TIMER2_EN 0x00000010 +#define CPU_TIMER2_AUTO 0x00000020 +#define CPU_TIMER_WD_EN 0x00000100 +#define CPU_TIMER_WD_AUTO 0x00000200 /* 25MHz mode is Armada XP - specific */ #define CPU_TIMER_WD_25MHZ_EN 0x00000400 #define CPU_TIMER0_25MHZ_EN 0x00000800 @@ -346,6 +351,8 @@ #define SAMPLE_AT_RESET 0x30 #elif defined(SOC_MV_FREY) #define SAMPLE_AT_RESET 0x100 +#elif defined(SOC_MV_ARMADA38X) +#define SAMPLE_AT_RESET 0x400 #endif #if defined(SOC_MV_DISCOVERY) #define SAMPLE_AT_RESET_LO 0x30 @@ -370,6 +377,9 @@ #elif defined(SOC_MV_LOKIPLUS) #define TCLK_MASK 0x0000F000 #define TCLK_SHIFT 0x0C +#elif defined(SOC_MV_ARMADA38X) +#define TCLK_MASK 0x00008000 +#define TCLK_SHIFT 15 #endif #define TCLK_100MHZ 100000000 @@ -415,6 +425,9 @@ #define MV_DEV_88F6281 0x6281 #define MV_DEV_88F6282 0x6282 #define MV_DEV_88F6781 0x6781 +#define MV_DEV_88F6828 0x6828 +#define MV_DEV_88F6820 0x6820 +#define MV_DEV_88F6810 0x6810 #define MV_DEV_MV78100_Z0 0x6381 #define MV_DEV_MV78100 0x7810 #define MV_DEV_MV78130 0x7813 @@ -428,6 +441,7 @@ #define MV_DEV_FAMILY_MASK 0xff00 #define MV_DEV_DISCOVERY 0x7800 +#define MV_DEV_ARMADA38X 0x6800 /* * Doorbell register control @@ -444,4 +458,36 @@ #define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) #define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) #endif + +/* + * SCU + */ +#if defined(SOC_MV_ARMADA38X) +#define MV_SCU_BASE (MV_BASE + 0xc000) +#define MV_SCU_REGS_LEN 0x100 +#define MV_SCU_REG_CTRL 0x00 +#define MV_SCU_REG_CONFIG 0x04 +#define MV_SCU_ENABLE 1 +#define SCU_CFG_REG_NCPU_MASK 0x3 +#endif + +/* + * PMSU + */ +#if defined(SOC_MV_ARMADA38X) +#define MV_PMSU_BASE (MV_BASE + 0x22000) +#define MV_PMSU_REGS_LEN 0x1000 +#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) (((cpu) * 0x100) + 0x124) +#endif + +/* + * CPU RESET + */ +#if defined(SOC_MV_ARMADA38X) +#define MV_CPU_RESET_BASE (MV_BASE + 0x20800) +#define MV_CPU_RESET_REGS_LEN 0x8 +#define CPU_RESET_OFFSET(cpu) ((cpu) * 0x8) +#define CPU_RESET_ASSERT 0x1 +#endif + #endif /* _MVREG_H_ */ Modified: projects/release-pkg/sys/arm/mv/mvvar.h ============================================================================== --- projects/release-pkg/sys/arm/mv/mvvar.h Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/mv/mvvar.h Wed Jan 20 17:08:01 2016 (r294448) @@ -109,7 +109,7 @@ uint32_t get_l2clk(void); uint32_t read_cpu_ctrl(uint32_t); void write_cpu_ctrl(uint32_t, uint32_t); -#if defined(SOC_MV_ARMADAXP) +#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) uint32_t read_cpu_mp_clocks(uint32_t reg); void write_cpu_mp_clocks(uint32_t reg, uint32_t val); uint32_t read_cpu_misc(uint32_t reg); Modified: projects/release-pkg/sys/arm/mv/mvwin.h ============================================================================== --- projects/release-pkg/sys/arm/mv/mvwin.h Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/mv/mvwin.h Wed Jan 20 17:08:01 2016 (r294448) @@ -73,6 +73,8 @@ #define MV_PCI_PORTS 2 /* 2x PCIE */ #elif defined(SOC_MV_ARMADAXP) #define MV_PCI_PORTS 3 /* 3x PCIE */ +#elif defined(SOC_MV_ARMADA38X) +#define MV_PCI_PORTS 4 /* 4x PCIE */ #else #error "MV_PCI_PORTS not configured !" #endif @@ -122,14 +124,14 @@ #define MV_DDR_CADR_BASE (MV_AXI_BASE + 0x100) #elif defined(SOC_MV_LOKIPLUS) #define MV_DDR_CADR_BASE (MV_BASE + 0xF1500) -#elif defined(SOC_MV_ARMADAXP) +#elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) #define MV_DDR_CADR_BASE (MV_BASE + 0x20180) #else #define MV_DDR_CADR_BASE (MV_BASE + 0x1500) #endif #define MV_MPP_BASE (MV_BASE + 0x10000) -#if defined(SOC_MV_ARMADAXP) +#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) #define MV_MISC_BASE (MV_BASE + 0x18200) #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) @@ -148,6 +150,8 @@ #if defined(SOC_MV_FREY) #define MV_PCIE_BASE (MV_BASE + 0x8000) +#elif defined(SOC_MV_ARMADA38X) +#define MV_PCIE_BASE (MV_BASE + 0x80000) #else #define MV_PCIE_BASE (MV_BASE + 0x40000) #endif @@ -168,7 +172,7 @@ /* * Decode windows definitions and macros */ -#if defined(SOC_MV_ARMADAXP) +#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) #define MV_WIN_CPU_CTRL(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) #define MV_WIN_CPU_BASE(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4) #define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + 0x008) @@ -182,7 +186,7 @@ #if defined(SOC_MV_DISCOVERY) #define MV_WIN_CPU_MAX 14 -#elif defined(SOC_MV_ARMADAXP) +#elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) #define MV_WIN_CPU_MAX 20 #else #define MV_WIN_CPU_MAX 8 @@ -267,6 +271,10 @@ #define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2))) #define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2))) #define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2))) +#elif defined(SOC_MV_ARMADA38X) +#define MV_WIN_PCIE_TARGET(n) ((n) == 0 ? 8 : 4) +#define MV_WIN_PCIE_MEM_ATTR(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20))) +#define MV_WIN_PCIE_IO_ATTR(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20))) #elif defined(SOC_MV_ORION) #define MV_WIN_PCIE_TARGET(n) 4 #define MV_WIN_PCIE_MEM_ATTR(n) 0x59 @@ -303,6 +311,35 @@ #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) #define MV_WIN_SATA_MAX 4 +#if defined(SOC_MV_ARMADA38X) +#define MV_BOOTROM_MEM_ADDR 0xFFF00000 +#define MV_BOOTROM_WIN_SIZE 0xF +#define MV_CPU_SUBSYS_REGS_LEN 0x100 + +/* IO Window Control Register fields */ +#define IO_WIN_SIZE_SHIFT 16 +#define IO_WIN_SIZE_MASK 0xFFFF +#define IO_WIN_ATTR_SHIFT 8 +#define IO_WIN_ATTR_MASK 0xFF +#define IO_WIN_TGT_SHIFT 4 +#define IO_WIN_TGT_MASK 0xF +#define IO_WIN_SYNC_SHIFT 1 +#define IO_WIN_SYNC_MASK 0x1 +#define IO_WIN_ENA_SHIFT 0 +#define IO_WIN_ENA_MASK 0x1 + +#define IO_WIN_9_CTRL_OFFSET 0x98 +#define IO_WIN_9_BASE_OFFSET 0x9C + +/* Mbus decoding unit IDs and attributes */ +#define MBUS_BOOTROM_TGT_ID 0x1 +#define MBUS_BOOTROM_ATTR 0x1D + +/* Internal Units Sync Barrier Control Register */ +#define MV_SYNC_BARRIER_CTRL 0x84 +#define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF +#endif + #define WIN_REG_IDX_RD(pre,reg,off,base) \ static __inline uint32_t \ pre ## _ ## reg ## _read(int i) \ Modified: projects/release-pkg/sys/arm/mv/timer.c ============================================================================== --- projects/release-pkg/sys/arm/mv/timer.c Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/mv/timer.c Wed Jan 20 17:08:01 2016 (r294448) @@ -54,26 +54,44 @@ __FBSDID("$FreeBSD$"); #define INITIAL_TIMECOUNTER (0xffffffff) #define MAX_WATCHDOG_TICKS (0xffffffff) -#if defined(SOC_MV_ARMADAXP) +#define MV_TMR 0x1 +#define MV_WDT 0x2 +#define MV_NONE 0x0 + +#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) #define MV_CLOCK_SRC 25000000 /* Timers' 25MHz mode */ #else #define MV_CLOCK_SRC get_tclk() #endif +#if defined(SOC_MV_ARMADA38X) +#define WATCHDOG_TIMER 4 +#else +#define WATCHDOG_TIMER 2 +#endif + struct mv_timer_softc { struct resource * timer_res[2]; bus_space_tag_t timer_bst; bus_space_handle_t timer_bsh; struct mtx timer_mtx; struct eventtimer et; + boolean_t has_wdt; }; static struct resource_spec mv_timer_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, - { SYS_RES_IRQ, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, { -1, 0 } }; +/* Interrupt is not required by MV_WDT devices */ +static struct ofw_compat_data mv_timer_compat[] = { + {"mrvl,timer", MV_TMR | MV_WDT }, + {"marvell,armada-380-wdt", MV_WDT }, + {NULL, MV_NONE } +}; + static struct mv_timer_softc *timer_softc = NULL; static int timers_initialized = 0; @@ -111,7 +129,7 @@ mv_timer_probe(device_t dev) if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (!ofw_bus_is_compatible(dev, "mrvl,timer")) + if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_NONE) return (ENXIO); device_set_desc(dev, "Marvell CPU Timer"); @@ -124,7 +142,7 @@ mv_timer_attach(device_t dev) int error; void *ihl; struct mv_timer_softc *sc; -#if !defined(SOC_MV_ARMADAXP) +#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X) uint32_t irq_cause, irq_mask; #endif @@ -143,9 +161,26 @@ mv_timer_attach(device_t dev) sc->timer_bst = rman_get_bustag(sc->timer_res[0]); sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]); + sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt") || + ofw_bus_is_compatible(dev, "marvell,armada-380-wdt"); + mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF); - mv_watchdog_disable(); - EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); + + if (sc->has_wdt) { + mv_watchdog_disable(); + EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); + } + + if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data + == MV_WDT) { + /* Don't set timers for wdt-only entry. */ + device_printf(dev, "only watchdog attached\n"); + return (0); + } else if (sc->timer_res[1] == NULL) { + device_printf(dev, "no interrupt resource\n"); + bus_release_resources(dev, mv_timer_spec, sc->timer_res); + return (ENXIO); + } if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK, mv_hardclock, NULL, sc, &ihl) != 0) { @@ -155,7 +190,7 @@ mv_timer_attach(device_t dev) } mv_setup_timers(); -#if !defined(SOC_MV_ARMADAXP) +#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X) irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); irq_cause &= IRQ_TIMER0_CLR; @@ -294,7 +329,7 @@ static void mv_watchdog_enable(void) { uint32_t val, irq_cause; -#if !defined(SOC_MV_ARMADAXP) +#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X) uint32_t irq_mask; #endif @@ -302,10 +337,14 @@ mv_watchdog_enable(void) irq_cause &= IRQ_TIMER_WD_CLR; write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); -#if defined(SOC_MV_ARMADAXP) +#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); + + val = read_cpu_misc(RSTOUTn_MASK); + val &= ~RSTOUTn_MASK_WD; + write_cpu_misc(RSTOUTn_MASK, val); #else irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); irq_mask |= IRQ_TIMER_WD_MASK; @@ -317,9 +356,12 @@ mv_watchdog_enable(void) #endif val = mv_get_timer_control(); - val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO; -#if defined(SOC_MV_ARMADAXP) - val |= CPU_TIMER_WD_25MHZ_EN; +#if defined(SOC_MV_ARMADA38X) + val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN; +#elif defined(SOC_MV_ARMADAXP) + val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN; +#else + val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO; #endif mv_set_timer_control(val); } @@ -328,18 +370,26 @@ static void mv_watchdog_disable(void) { uint32_t val, irq_cause; -#if !defined(SOC_MV_ARMADAXP) +#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X) uint32_t irq_mask; #endif val = mv_get_timer_control(); +#if defined(SOC_MV_ARMADA38X) val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO); +#else + val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); +#endif mv_set_timer_control(val); -#if defined(SOC_MV_ARMADAXP) +#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); + + val = read_cpu_misc(RSTOUTn_MASK); + val |= RSTOUTn_MASK_WD; + write_cpu_misc(RSTOUTn_MASK, RSTOUTn_MASK_WD); #else val = read_cpu_ctrl(RSTOUTn_MASK); val &= ~WD_RST_OUT_EN; @@ -378,8 +428,7 @@ mv_watchdog_event(void *arg, unsigned in if (ticks > MAX_WATCHDOG_TICKS) mv_watchdog_disable(); else { - /* Timer 2 is the watchdog */ - mv_set_timer(2, ticks); + mv_set_timer(WATCHDOG_TIMER, ticks); mv_watchdog_enable(); *error = 0; } @@ -438,7 +487,7 @@ mv_setup_timers(void) val = mv_get_timer_control(); val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO; -#if defined(SOC_MV_ARMADAXP) +#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) /* Enable 25MHz mode */ val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN; #endif Modified: projects/release-pkg/sys/arm/mv/twsi.c ============================================================================== --- projects/release-pkg/sys/arm/mv/twsi.c Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm/mv/twsi.c Wed Jan 20 17:08:01 2016 (r294448) @@ -141,6 +141,12 @@ static struct resource_spec res_spec[] = { -1, 0 } }; +static struct ofw_compat_data compat_data[] = { + { "mrvl,twsi", true }, + { "marvell,mv64xxx-i2c", true }, + { NULL, false } +}; + static device_method_t mv_twsi_methods[] = { /* device interface */ DEVMETHOD(device_probe, mv_twsi_probe), @@ -308,7 +314,7 @@ mv_twsi_probe(device_t dev) if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (!ofw_bus_is_compatible(dev, "mrvl,twsi")) + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) return (ENXIO); device_set_desc(dev, "Marvell Integrated I2C Bus Controller"); Modified: projects/release-pkg/sys/arm64/conf/GENERIC ============================================================================== --- projects/release-pkg/sys/arm64/conf/GENERIC Wed Jan 20 17:07:13 2016 (r294447) +++ projects/release-pkg/sys/arm64/conf/GENERIC Wed Jan 20 17:08:01 2016 (r294448) @@ -66,7 +66,6 @@ options MAC # TrustedBSD MAC Framewor options KDTRACE_FRAME # Ensure frames are compiled in options KDTRACE_HOOKS # Kernel DTrace hooks options VFP # Floating-point support -options VFS_AIO # Real implementations of the aio_* system calls options RACCT # Resource accounting framework options RACCT_DEFAULT_TO_DISABLED # Set kern.racct.enable=0 by default options RCTL # Resource limits Copied: projects/release-pkg/sys/boot/fdt/dts/arm/armada-380.dtsi (from r294447, head/sys/boot/fdt/dts/arm/armada-380.dtsi) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/release-pkg/sys/boot/fdt/dts/arm/armada-380.dtsi Wed Jan 20 17:08:01 2016 (r294448, copy of r294447, head/sys/boot/fdt/dts/arm/armada-380.dtsi) @@ -0,0 +1,154 @@ +/* + * Device Tree Include file for Marvell Armada 380 SoC. + * + * Copyright (C) 2014 Marvell + * + * Lior Amsalem <alior@marvell.com> + * Gregory CLEMENT <gregory.clement@free-electrons.com> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * $FreeBSD$ + */ + +#include "armada-38x.dtsi" + +/ { + model = "Marvell Armada 380 family SoC"; + compatible = "marvell,armada380"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,armada-380-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + }; + + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6810-pinctrl"; + }; + }; + + pcie-controller { + compatible = "marvell,armada-370-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + msi-parent = <&mpic>; + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ + 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ + 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; + + /* x1 port */ + pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gateclk 8>; + status = "disabled"; + }; + + /* x1 port */ + pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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