From owner-svn-src-all@FreeBSD.ORG Sat Oct 1 05:56:26 2011 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 408741065922; Sat, 1 Oct 2011 05:56:26 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 302BA8FC2B; Sat, 1 Oct 2011 05:56:26 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id p915uQId003018; Sat, 1 Oct 2011 05:56:26 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id p915uQH6003016; Sat, 1 Oct 2011 05:56:26 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201110010556.p915uQH6003016@svn.freebsd.org> From: Adrian Chadd Date: Sat, 1 Oct 2011 05:56:26 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r225892 - head/sys/mips/mips X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Oct 2011 05:56:26 -0000 Author: adrian Date: Sat Oct 1 05:56:25 2011 New Revision: 225892 URL: http://svn.freebsd.org/changeset/base/225892 Log: Disable using wait in cpu_idle() until a better solution to timer and interrupt handling can be implemented. Modified: head/sys/mips/mips/machdep.c Modified: head/sys/mips/mips/machdep.c ============================================================================== --- head/sys/mips/mips/machdep.c Sat Oct 1 00:31:30 2011 (r225891) +++ head/sys/mips/mips/machdep.c Sat Oct 1 05:56:25 2011 (r225892) @@ -485,9 +485,24 @@ spinlock_exit(void) /* * call platform specific code to halt (until next interrupt) for the idle loop */ +/* + * This is disabled because of three issues: + * + * + By calling critical_enter(), any interrupt which occurs after that but + * before the wait instruction will be handled but not serviced (in the case + * of a netisr) because preemption is not allowed at this point; + * + Any fast interrupt handler which schedules an immediate or fast callout + * will not occur until the wait instruction is interrupted, as the clock + * has already been set by cpu_idleclock(); + * + There is currently no known way to atomically enable interrupts and call + * wait, which is how the i386/amd64 code gets around (1). Thus even if + * interrupts were disabled and reenabled just before the wait call, any + * interrupt that did occur may not interrupt wait. + */ void cpu_idle(int busy) { +#if 0 KASSERT((mips_rd_status() & MIPS_SR_INT_IE) != 0, ("interrupts disabled in idle process.")); KASSERT((mips_rd_status() & MIPS_INT_MASK) != 0, @@ -502,6 +517,7 @@ cpu_idle(int busy) cpu_activeclock(); critical_exit(); } +#endif } int