From owner-freebsd-stable@FreeBSD.ORG Sun Dec 2 23:37:14 2012 Return-Path: Delivered-To: freebsd-stable@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 9E1551E4; Sun, 2 Dec 2012 23:37:14 +0000 (UTC) (envelope-from longwitz@incore.de) Received: from dss.incore.de (dss.incore.de [195.145.1.138]) by mx1.freebsd.org (Postfix) with ESMTP id 53B5E8FC17; Sun, 2 Dec 2012 23:37:14 +0000 (UTC) Received: from inetmail.dmz (inetmail.dmz [10.3.0.3]) by dss.incore.de (Postfix) with ESMTP id 5DF755CFF9; Mon, 3 Dec 2012 00:37:07 +0100 (CET) X-Virus-Scanned: amavisd-new at incore.de Received: from dss.incore.de ([10.3.0.3]) by inetmail.dmz (inetmail.dmz [10.3.0.3]) (amavisd-new, port 10024) with LMTP id UGYFNAQyt5bM; Mon, 3 Dec 2012 00:37:06 +0100 (CET) Received: from mail.incore (fwintern.dmz [10.0.0.253]) by dss.incore.de (Postfix) with ESMTP id A6A655CFF8; Mon, 3 Dec 2012 00:37:06 +0100 (CET) Received: from bsdmhs.longwitz (unknown [192.168.99.6]) by mail.incore (Postfix) with ESMTP id 4CF4C5083F; Mon, 3 Dec 2012 00:37:06 +0100 (CET) Message-ID: <50BBE621.8050907@incore.de> Date: Mon, 03 Dec 2012 00:37:05 +0100 From: Andreas Longwitz User-Agent: Thunderbird 2.0.0.19 (X11/20090113) MIME-Version: 1.0 To: Andriy Gapon Subject: Re: page fault on verbose boot References: <50ABE8BC.1010904@incore.de> <50B8CD59.1050308@FreeBSD.org> <50B8DD1C.4010308@incore.de> <50B8ED1B.8080009@FreeBSD.org> <50B9463C.3090005@incore.de> <50BA4CC2.1010908@FreeBSD.org> In-Reply-To: <50BA4CC2.1010908@FreeBSD.org> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: freebsd-stable@FreeBSD.org X-BeenThere: freebsd-stable@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Production branch of FreeBSD source code List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 02 Dec 2012 23:37:14 -0000 >>> "Andriy Gapon wrote" >>> Looking at the code in ioapic_program_intpin() this seems to be possible indeed: >>> >>> /* Write the values to the APIC. */ >>> intpin->io_lowreg = low; >>> ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low); >>> >>> The line above reprograms vector number AND _unmasks_ the pin (which was >>> specifically masked before reprogramming in ioapic_assign_cpu). >>> The lines below reprogram the destination LAPIC/CPU: >>> >>> value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin)); >>> value &= ~IOART_DEST; >>> value |= high; >>> ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value); >>> >>> So a pending interrupt would be happily delivered to a wrong destination (new >>> vector + old lapic). >>> I am not sure if just swapping these two blocks of lines would fix the issue, but >>> I hope that it would. Could you please try that? >> Yes I did and the first bootverbose run with your block switching patch >> was ok. I will do some more expansive tests next week. > > Thank you very much. > I've committed this change to head. After several tests I can state: the patch is ok for me. Thanks for your quick help! -- Andreas Longwitz