Date: Mon, 12 Jul 1999 10:42:38 -0700 (PDT) From: Matthew Dillon <dillon@apollo.backplane.com> To: John-Mark Gurney <gurney_j@efn.org> Cc: Luoqi Chen <luoqi@watermarkgroup.com>, dfr@nlsystems.com, jeremyp@gsmx07.alcatel.com.au, freebsd-current@FreeBSD.ORG, mike@ducky.net Subject: Re: "objtrm" problem probably found (was Re: Stuck in "objtrm") Message-ID: <199907121742.KAA70526@apollo.backplane.com> References: <199907121032.GAA14268@lor.watermarkgroup.com> <199907121647.JAA70249@apollo.backplane.com> <19990712103845.39296@hydrogen.fircrest.net>
next in thread | previous in thread | raw e-mail | index | archive | help
:actually, I'm not so sure, it guarantees that NO other bus operation
:will succeed while this is happening... what happens if a pci bus
:mastering card makes a modification to this value? sure, it normally
:won't happen, but it can... and w/o the lock prefix, this CAN happen
:from what I understand of the architecture...
:
:so, it does have to lock even the memory bus, simply the cache isn't
:enough for the lock to do what it needs...
:
:--
: John-Mark Gurney Voice: +1 541 684 8449
: Cu Networking P.O. Box 5693, 97405
As I said, it depends what L1/L2 cache model intel is using. If they
are being smart it does *NOT* prevent other bus operations from occuring,
it simply locks the cache line containing the item for the duration of
the instruction. The worst case should be an extra snoop on the bus.
Hold on, I have some numbers.
-Matt
To Unsubscribe: send mail to majordomo@FreeBSD.org
with "unsubscribe freebsd-current" in the body of the message
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?199907121742.KAA70526>