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From: mouth@ibm.net (John Kelly)
To: Bruce Evans <bde@zeta.org.au>
Cc: hackers@FreeBSD.ORG
Subject: Re: Status of 650 UART support
Date: Sat, 15 Nov 1997 05:51:11 GMT
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References: <199711150423.PAA28278@godzilla.zeta.org.au>
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On Sat, 15 Nov 1997 15:23:09 +1100, Bruce Evans <bde@zeta.org.au>
wrote:

>>>>Edge triggered interrupts

>They force the interrupt handler to check all possible sources of the
>interrupt, although 90-99% of the times there will only be one interrupt
>source so returning after handling only one is best if checking the
>others is expensive (as it is for separate ISA devices).

Right.  And that brings up something I've been wondering about on my
8-port serial card with 650s.

Suppose I set all 8 ports to 460,800 bps and saturate them with
inbound data.  With the 32-byte FIFO I might set the trigger level to
16, giving 16 bytes of headroom in each UART, or possibly set the
trigger level to 8, giving 24 bytes of headroom.

Once I start draining the first UART, will I reach the eighth UART
before it's overrun, and if so, how much margin will I have?  I'm not
sure how to calculate the time required for the 8-bit bus cycles.

John