From owner-freebsd-alpha Wed Jun 13 11:22:49 2001 Delivered-To: freebsd-alpha@freebsd.org Received: from duke.cs.duke.edu (duke.cs.duke.edu [152.3.140.1]) by hub.freebsd.org (Postfix) with ESMTP id F2FFE37B401; Wed, 13 Jun 2001 11:22:46 -0700 (PDT) (envelope-from gallatin@cs.duke.edu) Received: from grasshopper.cs.duke.edu (grasshopper.cs.duke.edu [152.3.145.30]) by duke.cs.duke.edu (8.9.3/8.9.3) with ESMTP id OAA12573; Wed, 13 Jun 2001 14:22:45 -0400 (EDT) Received: (from gallatin@localhost) by grasshopper.cs.duke.edu (8.11.3/8.9.1) id f5DIMF319102; Wed, 13 Jun 2001 14:22:15 -0400 (EDT) (envelope-from gallatin@cs.duke.edu) From: Andrew Gallatin MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-ID: <15143.44887.290985.930683@grasshopper.cs.duke.edu> Date: Wed, 13 Jun 2001 14:22:15 -0400 (EDT) To: mjacob@feral.com Cc: John Baldwin , freebsd-alpha@FreeBSD.ORG, wilko@FreeBSD.ORG Subject: Re: followup on 8 way SMP pani In-Reply-To: References: X-Mailer: VM 6.75 under 21.1 (patch 12) "Channel Islands" XEmacs Lucid Sender: owner-freebsd-alpha@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.org Matthew Jacob writes: > > Hang on a second. Clock interrupts are used for _two_ different things > > here, which is where you are getting confused I think. One is > > timekeeping, another is to handle things like per-process statclock, etc. > > All that per-process stuff we do on _all_ cpu's when we get a clock > > interrupt. Alpha is nice in that it broadcasts clock interrupts for this > > purpose. On x86, for example, we only have one clock interrupt and we > > have to IPI all the other CPU's to get this info. > > But, in fact, in this case this is *not* a broadcast interrupt. Each TLSB CPU > board can have up to two CPUs. Each TLSB CPU board has an interval timer and a > Zilog duart. You use the TLINTRMASK{0,1} registers for each TLSB CPU board to > control whether one or both CPUs get DUART or Interval Timer or IPI (or any > other, for that matter) interrupt. > The Sable/Lynx family has a similar register (but per-cpu). It has bits which control if that cpu gets Interval Timer, IPI, etc interrupts. Also, from the docs & emperical evidence, it would appear that clock interrupts arrive at the same frequency, but cpu1 always interrupts 1/4 of a hz after cpu0, cpu2 is 1/2hz behind cpu0, etc. Drew To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-alpha" in the body of the message