From owner-p4-projects@FreeBSD.ORG Wed Jul 28 20:50:10 2004 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id C057916A4D0; Wed, 28 Jul 2004 20:50:09 +0000 (GMT) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 9D32E16A4CE for ; Wed, 28 Jul 2004 20:50:09 +0000 (GMT) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 76F1943D3F for ; Wed, 28 Jul 2004 20:50:09 +0000 (GMT) (envelope-from jhb@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.12.11/8.12.11) with ESMTP id i6SKo9vt010598 for ; Wed, 28 Jul 2004 20:50:09 GMT (envelope-from jhb@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.12.11/8.12.11/Submit) id i6SKo9ci010595 for perforce@freebsd.org; Wed, 28 Jul 2004 20:50:09 GMT (envelope-from jhb@freebsd.org) Date: Wed, 28 Jul 2004 20:50:09 GMT Message-Id: <200407282050.i6SKo9ci010595@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to jhb@freebsd.org using -f From: John Baldwin To: Perforce Change Reviews Subject: PERFORCE change 58403 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Jul 2004 20:50:10 -0000 http://perforce.freebsd.org/chv.cgi?CH=58403 Change 58403 by jhb@jhb_slimer on 2004/07/28 20:49:40 Prompted by some questions on IRC from gibbs@, scottl@, and others: atomic_store_rel() on ia32 does not actually need a lock, just a simple store via mov will do. Specifically, in section 7.2.2 of Volume 3: System Programming Guide of the IA32 Intel Arch Manuals, it states: * Writes by a single processor are observed in the same order by all processors. Affected files ... .. //depot/projects/smpng/sys/i386/include/atomic.h#13 edit Differences ... ==== //depot/projects/smpng/sys/i386/include/atomic.h#13 (text+ko) ==== @@ -180,7 +180,7 @@ * XXX: This is _NOT_ safe on a P6 or higher because it does not guarantee * memory ordering. These should only be used on a 386. */ -#define ATOMIC_STORE_LOAD(TYPE, LOP, SOP) \ +#define ATOMIC_STORE_LOAD(TYPE, LOP, SOP, SCONS) \ static __inline u_##TYPE \ atomic_load_acq_##TYPE(volatile u_##TYPE *p) \ { \ @@ -197,7 +197,7 @@ #else /* !defined(I386_CPU) */ -#define ATOMIC_STORE_LOAD(TYPE, LOP, SOP) \ +#define ATOMIC_STORE_LOAD(TYPE, LOP, SOP, SCONS) \ static __inline u_##TYPE \ atomic_load_acq_##TYPE(volatile u_##TYPE *p) \ { \ @@ -211,16 +211,13 @@ return (res); \ } \ \ -/* \ - * The XCHG instruction asserts LOCK automagically. \ - */ \ static __inline void \ atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\ { \ __asm __volatile(SOP \ - : "+m" (*p), /* 0 */ \ - "+r" (v) /* 1 */ \ - : : "memory"); \ + : "=m" (*p), /* 0 */ \ + : SCONS (v) /* 1 */ \ + : "memory"); \ } \ struct __hack @@ -230,7 +227,7 @@ extern int atomic_cmpset_int(volatile u_int *, u_int, u_int); -#define ATOMIC_STORE_LOAD(TYPE, LOP, SOP) \ +#define ATOMIC_STORE_LOAD(TYPE, LOP, SOP, SCONS) \ extern u_##TYPE atomic_load_acq_##TYPE(volatile u_##TYPE *p); \ extern void atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v) @@ -258,10 +255,10 @@ ATOMIC_ASM(add, long, "addl %1,%0", "ir", v); ATOMIC_ASM(subtract, long, "subl %1,%0", "ir", v); -ATOMIC_STORE_LOAD(char, "cmpxchgb %b0,%1", "xchgb %b1,%0"); -ATOMIC_STORE_LOAD(short,"cmpxchgw %w0,%1", "xchgw %w1,%0"); -ATOMIC_STORE_LOAD(int, "cmpxchgl %0,%1", "xchgl %1,%0"); -ATOMIC_STORE_LOAD(long, "cmpxchgl %0,%1", "xchgl %1,%0"); +ATOMIC_STORE_LOAD(char, "cmpxchgb %b0,%1", "movb %b1,%0", "iq"); +ATOMIC_STORE_LOAD(short,"cmpxchgw %w0,%1", "movw %w1,%0", "ir"); +ATOMIC_STORE_LOAD(int, "cmpxchgl %0,%1", "movl %1,%0", "ir"); +ATOMIC_STORE_LOAD(long, "cmpxchgl %0,%1", "movl %1,%0", "ir"); #undef ATOMIC_ASM #undef ATOMIC_STORE_LOAD