Date: Thu, 2 Aug 2018 19:11:56 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r337162 - in projects/clang700-import/usr.bin/clang: bugpoint llc lli llvm-ar llvm-as llvm-bcanalyzer llvm-cov llvm-diff llvm-dis llvm-dwarfdump llvm-extract llvm-link llvm-mca llvm-nm ... Message-ID: <201808021911.w72JBucm080612@repo.freebsd.org>
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Author: dim Date: Thu Aug 2 19:11:56 2018 New Revision: 337162 URL: https://svnweb.freebsd.org/changeset/base/337162 Log: Update llvm tool manpages, and llvm-mca.1. Added: projects/clang700-import/usr.bin/clang/llvm-mca/llvm-mca.1 (contents, props changed) Modified: projects/clang700-import/usr.bin/clang/bugpoint/bugpoint.1 projects/clang700-import/usr.bin/clang/llc/llc.1 projects/clang700-import/usr.bin/clang/lli/lli.1 projects/clang700-import/usr.bin/clang/llvm-ar/llvm-ar.1 projects/clang700-import/usr.bin/clang/llvm-as/llvm-as.1 projects/clang700-import/usr.bin/clang/llvm-bcanalyzer/llvm-bcanalyzer.1 projects/clang700-import/usr.bin/clang/llvm-cov/llvm-cov.1 projects/clang700-import/usr.bin/clang/llvm-diff/llvm-diff.1 projects/clang700-import/usr.bin/clang/llvm-dis/llvm-dis.1 projects/clang700-import/usr.bin/clang/llvm-dwarfdump/llvm-dwarfdump.1 projects/clang700-import/usr.bin/clang/llvm-extract/llvm-extract.1 projects/clang700-import/usr.bin/clang/llvm-link/llvm-link.1 projects/clang700-import/usr.bin/clang/llvm-mca/Makefile projects/clang700-import/usr.bin/clang/llvm-nm/llvm-nm.1 projects/clang700-import/usr.bin/clang/llvm-pdbutil/llvm-pdbutil.1 projects/clang700-import/usr.bin/clang/llvm-profdata/llvm-profdata.1 projects/clang700-import/usr.bin/clang/llvm-symbolizer/llvm-symbolizer.1 projects/clang700-import/usr.bin/clang/llvm-tblgen/llvm-tblgen.1 projects/clang700-import/usr.bin/clang/opt/opt.1 Modified: projects/clang700-import/usr.bin/clang/bugpoint/bugpoint.1 ============================================================================== --- projects/clang700-import/usr.bin/clang/bugpoint/bugpoint.1 Thu Aug 2 19:09:13 2018 (r337161) +++ projects/clang700-import/usr.bin/clang/bugpoint/bugpoint.1 Thu Aug 2 19:11:56 2018 (r337162) @@ -1,7 +1,7 @@ .\" $FreeBSD$ .\" Man page generated from reStructuredText. . -.TH "BUGPOINT" "1" "2017-12-24" "6" "LLVM" +.TH "BUGPOINT" "1" "2018-08-02" "7" "LLVM" .SH NAME bugpoint \- automatic test case reduction tool . @@ -304,6 +304,6 @@ opt|opt .SH AUTHOR Maintained by The LLVM Team (http://llvm.org/). .SH COPYRIGHT -2003-2017, LLVM Project +2003-2018, LLVM Project .\" Generated by docutils manpage writer. . Modified: projects/clang700-import/usr.bin/clang/llc/llc.1 ============================================================================== --- projects/clang700-import/usr.bin/clang/llc/llc.1 Thu Aug 2 19:09:13 2018 (r337161) +++ projects/clang700-import/usr.bin/clang/llc/llc.1 Thu Aug 2 19:11:56 2018 (r337162) @@ -1,7 +1,7 @@ .\" $FreeBSD$ .\" Man page generated from reStructuredText. . -.TH "LLC" "1" "2017-12-24" "6" "LLVM" +.TH "LLC" "1" "2018-08-02" "7" "LLVM" .SH NAME llc \- LLVM static compiler . @@ -186,7 +186,7 @@ Specify which EABI version should conform to. Valid E .TP .B \-stack\-size\-section Emit the .stack_sizes section which contains stack size metadata. The section -contains an array of pairs of function symbol references (8 byte) and stack +contains an array of pairs of function symbol values (pointer size) and stack sizes (unsigned LEB128). The stack size values only include the space allocated in the function prologue. Functions with dynamic stack allocations are not included. @@ -269,6 +269,6 @@ lli .SH AUTHOR Maintained by The LLVM Team (http://llvm.org/). .SH COPYRIGHT -2003-2017, LLVM Project +2003-2018, LLVM Project .\" Generated by docutils manpage writer. . Modified: projects/clang700-import/usr.bin/clang/lli/lli.1 ============================================================================== --- projects/clang700-import/usr.bin/clang/lli/lli.1 Thu Aug 2 19:09:13 2018 (r337161) +++ projects/clang700-import/usr.bin/clang/lli/lli.1 Thu Aug 2 19:11:56 2018 (r337162) @@ -1,7 +1,7 @@ .\" $FreeBSD$ .\" Man page generated from reStructuredText. . -.TH "LLI" "1" "2017-12-24" "6" "LLVM" +.TH "LLI" "1" "2018-08-02" "7" "LLVM" .SH NAME lli \- directly execute programs from LLVM bitcode . @@ -293,6 +293,6 @@ Otherwise, it will return the exit code of the program .SH AUTHOR Maintained by The LLVM Team (http://llvm.org/). .SH COPYRIGHT -2003-2017, LLVM Project +2003-2018, LLVM Project .\" Generated by docutils manpage writer. . Modified: projects/clang700-import/usr.bin/clang/llvm-ar/llvm-ar.1 ============================================================================== --- projects/clang700-import/usr.bin/clang/llvm-ar/llvm-ar.1 Thu Aug 2 19:09:13 2018 (r337161) +++ projects/clang700-import/usr.bin/clang/llvm-ar/llvm-ar.1 Thu Aug 2 19:11:56 2018 (r337162) @@ -1,7 +1,7 @@ .\" $FreeBSD$ .\" Man page generated from reStructuredText. . -.TH "LLVM-AR" "1" "2017-12-24" "6" "LLVM" +.TH "LLVM-AR" "1" "2018-08-02" "7" "LLVM" .SH NAME llvm-ar \- LLVM archiver . @@ -385,6 +385,6 @@ ar(1) .SH AUTHOR Maintained by The LLVM Team (http://llvm.org/). .SH COPYRIGHT -2003-2017, LLVM Project +2003-2018, LLVM Project .\" Generated by docutils manpage writer. . Modified: projects/clang700-import/usr.bin/clang/llvm-as/llvm-as.1 ============================================================================== --- projects/clang700-import/usr.bin/clang/llvm-as/llvm-as.1 Thu Aug 2 19:09:13 2018 (r337161) +++ projects/clang700-import/usr.bin/clang/llvm-as/llvm-as.1 Thu Aug 2 19:11:56 2018 (r337162) @@ -1,7 +1,7 @@ .\" $FreeBSD$ .\" Man page generated from reStructuredText. . -.TH "LLVM-AS" "1" "2017-12-24" "6" "LLVM" +.TH "LLVM-AS" "1" "2018-08-02" "7" "LLVM" .SH NAME llvm-as \- LLVM assembler . @@ -82,6 +82,6 @@ llvm\-dis|llvm\-dis, gccas|gccas .SH AUTHOR Maintained by The LLVM Team (http://llvm.org/). .SH COPYRIGHT -2003-2017, LLVM Project +2003-2018, LLVM Project .\" Generated by docutils manpage writer. . Modified: projects/clang700-import/usr.bin/clang/llvm-bcanalyzer/llvm-bcanalyzer.1 ============================================================================== --- projects/clang700-import/usr.bin/clang/llvm-bcanalyzer/llvm-bcanalyzer.1 Thu Aug 2 19:09:13 2018 (r337161) +++ projects/clang700-import/usr.bin/clang/llvm-bcanalyzer/llvm-bcanalyzer.1 Thu Aug 2 19:11:56 2018 (r337162) @@ -1,7 +1,7 @@ .\" $FreeBSD$ .\" Man page generated from reStructuredText. . -.TH "LLVM-BCANALYZER" "1" "2017-12-24" "6" "LLVM" +.TH "LLVM-BCANALYZER" "1" "2018-08-02" "7" "LLVM" .SH NAME llvm-bcanalyzer \- LLVM bitcode analyzer . @@ -471,6 +471,6 @@ Rate encoding scheme. The percentage is relative to # .SH AUTHOR Maintained by The LLVM Team (http://llvm.org/). .SH COPYRIGHT -2003-2017, LLVM Project +2003-2018, LLVM Project .\" Generated by docutils manpage writer. . Modified: projects/clang700-import/usr.bin/clang/llvm-cov/llvm-cov.1 ============================================================================== --- projects/clang700-import/usr.bin/clang/llvm-cov/llvm-cov.1 Thu Aug 2 19:09:13 2018 (r337161) +++ projects/clang700-import/usr.bin/clang/llvm-cov/llvm-cov.1 Thu Aug 2 19:11:56 2018 (r337162) @@ -1,7 +1,7 @@ .\" $FreeBSD$ .\" Man page generated from reStructuredText. . -.TH "LLVM-COV" "1" "2017-12-24" "6" "LLVM" +.TH "LLVM-COV" "1" "2018-08-02" "7" "LLVM" .SH NAME llvm-cov \- emit coverage information . @@ -271,6 +271,11 @@ Show code coverage only for functions that match the g .UNINDENT .INDENT 0.0 .TP +.B \-ignore\-filename\-regex=<PATTERN> +Skip source code files with file paths that match the given regular expression. +.UNINDENT +.INDENT 0.0 +.TP .B \-format=<FORMAT> Use the specified output format. The supported formats are: "text", "html". .UNINDENT @@ -347,8 +352,8 @@ the binaries \fIBIN\fP,... using the profile data \fIP filtered to only show the coverage for the files listed in \fISOURCES\fP\&. .sp If no source files are provided, a summary line is printed for each file in the -coverage data. If any files are provided, summaries are shown for each function -in the listed files instead. +coverage data. If any files are provided, summaries can be shown for each +function in the listed files if the \fB\-show\-functions\fP option is enabled. .sp For information on compiling programs for coverage and generating profile data, see \fI\%SHOW COMMAND\fP\&. @@ -376,15 +381,21 @@ Show coverage summaries for each function. Defaults to .B \-show\-instantiation\-summary Show statistics for all function instantiations. Defaults to false. .UNINDENT +.INDENT 0.0 +.TP +.B \-ignore\-filename\-regex=<PATTERN> +Skip source code files with file paths that match the given regular expression. +.UNINDENT .SH EXPORT COMMAND .SS SYNOPSIS .sp -\fBllvm\-cov export\fP [\fIoptions\fP] \-instr\-profile \fIPROFILE\fP \fIBIN\fP [\fI\-object BIN,...\fP] [[\fI\-object BIN\fP]] +\fBllvm\-cov export\fP [\fIoptions\fP] \-instr\-profile \fIPROFILE\fP \fIBIN\fP [\fI\-object BIN,...\fP] [[\fI\-object BIN\fP]] [\fISOURCES\fP] .SS DESCRIPTION .sp The \fBllvm\-cov export\fP command exports regions, functions, expansions, and summaries of the coverage of the binaries \fIBIN\fP,... using the profile data -\fIPROFILE\fP as JSON. +\fIPROFILE\fP as JSON. It can optionally be filtered to only export the coverage +for the files listed in \fISOURCES\fP\&. .sp For information on compiling programs for coverage and generating profile data, see \fI\%SHOW COMMAND\fP\&. @@ -405,9 +416,14 @@ will not export coverage information for smaller units functions or regions. The result will be the same as produced by :program: \fIllvm\-cov report\fP command, but presented in JSON format rather than text. .UNINDENT +.INDENT 0.0 +.TP +.B \-ignore\-filename\-regex=<PATTERN> +Skip source code files with file paths that match the given regular expression. +.UNINDENT .SH AUTHOR Maintained by The LLVM Team (http://llvm.org/). .SH COPYRIGHT -2003-2017, LLVM Project +2003-2018, LLVM Project .\" Generated by docutils manpage writer. . Modified: projects/clang700-import/usr.bin/clang/llvm-diff/llvm-diff.1 ============================================================================== --- projects/clang700-import/usr.bin/clang/llvm-diff/llvm-diff.1 Thu Aug 2 19:09:13 2018 (r337161) +++ projects/clang700-import/usr.bin/clang/llvm-diff/llvm-diff.1 Thu Aug 2 19:11:56 2018 (r337162) @@ -1,7 +1,7 @@ .\" $FreeBSD$ .\" Man page generated from reStructuredText. . -.TH "LLVM-DIFF" "1" "2017-12-24" "6" "LLVM" +.TH "LLVM-DIFF" "1" "2018-08-02" "7" "LLVM" .SH NAME llvm-diff \- LLVM structural 'diff' . @@ -72,6 +72,6 @@ massive detected differences in blocks. .SH AUTHOR Maintained by The LLVM Team (http://llvm.org/). .SH COPYRIGHT -2003-2017, LLVM Project +2003-2018, LLVM Project .\" Generated by docutils manpage writer. . Modified: projects/clang700-import/usr.bin/clang/llvm-dis/llvm-dis.1 ============================================================================== --- projects/clang700-import/usr.bin/clang/llvm-dis/llvm-dis.1 Thu Aug 2 19:09:13 2018 (r337161) +++ projects/clang700-import/usr.bin/clang/llvm-dis/llvm-dis.1 Thu Aug 2 19:11:56 2018 (r337162) @@ -1,7 +1,7 @@ .\" $FreeBSD$ .\" Man page generated from reStructuredText. . -.TH "LLVM-DIS" "1" "2017-12-24" "6" "LLVM" +.TH "LLVM-DIS" "1" "2018-08-02" "7" "LLVM" .SH NAME llvm-dis \- LLVM disassembler . @@ -83,6 +83,6 @@ llvm\-as|llvm\-as .SH AUTHOR Maintained by The LLVM Team (http://llvm.org/). .SH COPYRIGHT -2003-2017, LLVM Project +2003-2018, LLVM Project .\" Generated by docutils manpage writer. . Modified: projects/clang700-import/usr.bin/clang/llvm-dwarfdump/llvm-dwarfdump.1 ============================================================================== --- projects/clang700-import/usr.bin/clang/llvm-dwarfdump/llvm-dwarfdump.1 Thu Aug 2 19:09:13 2018 (r337161) +++ projects/clang700-import/usr.bin/clang/llvm-dwarfdump/llvm-dwarfdump.1 Thu Aug 2 19:11:56 2018 (r337162) @@ -1,7 +1,7 @@ .\" $FreeBSD$ .\" Man page generated from reStructuredText. . -.TH "LLVM-DWARFDUMP" "1" "2017-12-24" "6" "LLVM" +.TH "LLVM-DWARFDUMP" "1" "2018-08-02" "7" "LLVM" .SH NAME llvm-dwarfdump \- dump and verify DWARF debug information . @@ -184,6 +184,6 @@ successfully. Otherwise, it returns 1. .SH AUTHOR Maintained by The LLVM Team (http://llvm.org/). .SH COPYRIGHT -2003-2017, LLVM Project +2003-2018, LLVM Project .\" Generated by docutils manpage writer. . Modified: projects/clang700-import/usr.bin/clang/llvm-extract/llvm-extract.1 ============================================================================== --- projects/clang700-import/usr.bin/clang/llvm-extract/llvm-extract.1 Thu Aug 2 19:09:13 2018 (r337161) +++ projects/clang700-import/usr.bin/clang/llvm-extract/llvm-extract.1 Thu Aug 2 19:11:56 2018 (r337162) @@ -1,7 +1,7 @@ .\" $FreeBSD$ .\" Man page generated from reStructuredText. . -.TH "LLVM-EXTRACT" "1" "2017-12-24" "6" "LLVM" +.TH "LLVM-EXTRACT" "1" "2018-08-02" "7" "LLVM" .SH NAME llvm-extract \- extract a function from an LLVM module . @@ -124,6 +124,6 @@ bugpoint .SH AUTHOR Maintained by The LLVM Team (http://llvm.org/). .SH COPYRIGHT -2003-2017, LLVM Project +2003-2018, LLVM Project .\" Generated by docutils manpage writer. . Modified: projects/clang700-import/usr.bin/clang/llvm-link/llvm-link.1 ============================================================================== --- projects/clang700-import/usr.bin/clang/llvm-link/llvm-link.1 Thu Aug 2 19:09:13 2018 (r337161) +++ projects/clang700-import/usr.bin/clang/llvm-link/llvm-link.1 Thu Aug 2 19:11:56 2018 (r337162) @@ -1,7 +1,7 @@ .\" $FreeBSD$ .\" Man page generated from reStructuredText. . -.TH "LLVM-LINK" "1" "2017-12-24" "6" "LLVM" +.TH "LLVM-LINK" "1" "2018-08-02" "7" "LLVM" .SH NAME llvm-link \- LLVM bitcode linker . @@ -84,6 +84,6 @@ occurs, it will exit with a non\-zero value. .SH AUTHOR Maintained by The LLVM Team (http://llvm.org/). .SH COPYRIGHT -2003-2017, LLVM Project +2003-2018, LLVM Project .\" Generated by docutils manpage writer. . Modified: projects/clang700-import/usr.bin/clang/llvm-mca/Makefile ============================================================================== --- projects/clang700-import/usr.bin/clang/llvm-mca/Makefile Thu Aug 2 19:09:13 2018 (r337161) +++ projects/clang700-import/usr.bin/clang/llvm-mca/Makefile Thu Aug 2 19:11:56 2018 (r337162) @@ -1,7 +1,6 @@ # $FreeBSD$ PROG_CXX= llvm-mca -MAN= SRCDIR= tools/llvm-mca SRCS+= CodeRegion.cpp Added: projects/clang700-import/usr.bin/clang/llvm-mca/llvm-mca.1 ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/clang700-import/usr.bin/clang/llvm-mca/llvm-mca.1 Thu Aug 2 19:11:56 2018 (r337162) @@ -0,0 +1,886 @@ +.\" $FreeBSD$ +.\" Man page generated from reStructuredText. +. +.TH "LLVM-MCA" "1" "2018-08-02" "7" "LLVM" +.SH NAME +llvm-mca \- LLVM Machine Code Analyzer +. +.nr rst2man-indent-level 0 +. +.de1 rstReportMargin +\\$1 \\n[an-margin] +level \\n[rst2man-indent-level] +level margin: \\n[rst2man-indent\\n[rst2man-indent-level]] +- +\\n[rst2man-indent0] +\\n[rst2man-indent1] +\\n[rst2man-indent2] +.. +.de1 INDENT +.\" .rstReportMargin pre: +. RS \\$1 +. nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin] +. nr rst2man-indent-level +1 +.\" .rstReportMargin post: +.. +.de UNINDENT +. RE +.\" indent \\n[an-margin] +.\" old: \\n[rst2man-indent\\n[rst2man-indent-level]] +.nr rst2man-indent-level -1 +.\" new: \\n[rst2man-indent\\n[rst2man-indent-level]] +.in \\n[rst2man-indent\\n[rst2man-indent-level]]u +.. +.SH SYNOPSIS +.sp +\fBllvm\-mca\fP [\fIoptions\fP] [input] +.SH DESCRIPTION +.sp +\fBllvm\-mca\fP is a performance analysis tool that uses information +available in LLVM (e.g. scheduling models) to statically measure the performance +of machine code in a specific CPU. +.sp +Performance is measured in terms of throughput as well as processor resource +consumption. The tool currently works for processors with an out\-of\-order +backend, for which there is a scheduling model available in LLVM. +.sp +The main goal of this tool is not just to predict the performance of the code +when run on the target, but also help with diagnosing potential performance +issues. +.sp +Given an assembly code sequence, llvm\-mca estimates the Instructions Per Cycle +(IPC), as well as hardware resource pressure. The analysis and reporting style +were inspired by the IACA tool from Intel. +.sp +\fBllvm\-mca\fP allows the usage of special code comments to mark regions of +the assembly code to be analyzed. A comment starting with substring +\fBLLVM\-MCA\-BEGIN\fP marks the beginning of a code region. A comment starting with +substring \fBLLVM\-MCA\-END\fP marks the end of a code region. For example: +.INDENT 0.0 +.INDENT 3.5 +.sp +.nf +.ft C +# LLVM\-MCA\-BEGIN My Code Region + ... +# LLVM\-MCA\-END +.ft P +.fi +.UNINDENT +.UNINDENT +.sp +Multiple regions can be specified provided that they do not overlap. A code +region can have an optional description. If no user\-defined region is specified, +then \fBllvm\-mca\fP assumes a default region which contains every +instruction in the input file. Every region is analyzed in isolation, and the +final performance report is the union of all the reports generated for every +code region. +.sp +Inline assembly directives may be used from source code to annotate the +assembly text: +.INDENT 0.0 +.INDENT 3.5 +.sp +.nf +.ft C +int foo(int a, int b) { + __asm volatile("# LLVM\-MCA\-BEGIN foo"); + a += 42; + __asm volatile("# LLVM\-MCA\-END"); + a *= b; + return a; +} +.ft P +.fi +.UNINDENT +.UNINDENT +.sp +So for example, you can compile code with clang, output assembly, and pipe it +directly into llvm\-mca for analysis: +.INDENT 0.0 +.INDENT 3.5 +.sp +.nf +.ft C +$ clang foo.c \-O2 \-target x86_64\-unknown\-unknown \-S \-o \- | llvm\-mca \-mcpu=btver2 +.ft P +.fi +.UNINDENT +.UNINDENT +.sp +Or for Intel syntax: +.INDENT 0.0 +.INDENT 3.5 +.sp +.nf +.ft C +$ clang foo.c \-O2 \-target x86_64\-unknown\-unknown \-mllvm \-x86\-asm\-syntax=intel \-S \-o \- | llvm\-mca \-mcpu=btver2 +.ft P +.fi +.UNINDENT +.UNINDENT +.SH OPTIONS +.sp +If \fBinput\fP is "\fB\-\fP" or omitted, \fBllvm\-mca\fP reads from standard +input. Otherwise, it will read from the specified filename. +.sp +If the \fB\-o\fP option is omitted, then \fBllvm\-mca\fP will send its output +to standard output if the input is from standard input. If the \fB\-o\fP +option specifies "\fB\-\fP", then the output will also be sent to standard output. +.INDENT 0.0 +.TP +.B \-help +Print a summary of command line options. +.UNINDENT +.INDENT 0.0 +.TP +.B \-mtriple=<target triple> +Specify a target triple string. +.UNINDENT +.INDENT 0.0 +.TP +.B \-march=<arch> +Specify the architecture for which to analyze the code. It defaults to the +host default target. +.UNINDENT +.INDENT 0.0 +.TP +.B \-mcpu=<cpuname> +Specify the processor for which to analyze the code. By default, the cpu name +is autodetected from the host. +.UNINDENT +.INDENT 0.0 +.TP +.B \-output\-asm\-variant=<variant id> +Specify the output assembly variant for the report generated by the tool. +On x86, possible values are [0, 1]. A value of 0 (vic. 1) for this flag enables +the AT&T (vic. Intel) assembly format for the code printed out by the tool in +the analysis report. +.UNINDENT +.INDENT 0.0 +.TP +.B \-dispatch=<width> +Specify a different dispatch width for the processor. The dispatch width +defaults to field \(aqIssueWidth\(aq in the processor scheduling model. If width is +zero, then the default dispatch width is used. +.UNINDENT +.INDENT 0.0 +.TP +.B \-register\-file\-size=<size> +Specify the size of the register file. When specified, this flag limits how +many physical registers are available for register renaming purposes. A value +of zero for this flag means "unlimited number of physical registers". +.UNINDENT +.INDENT 0.0 +.TP +.B \-iterations=<number of iterations> +Specify the number of iterations to run. If this flag is set to 0, then the +tool sets the number of iterations to a default value (i.e. 100). +.UNINDENT +.INDENT 0.0 +.TP +.B \-noalias=<bool> +If set, the tool assumes that loads and stores don\(aqt alias. This is the +default behavior. +.UNINDENT +.INDENT 0.0 +.TP +.B \-lqueue=<load queue size> +Specify the size of the load queue in the load/store unit emulated by the tool. +By default, the tool assumes an unbound number of entries in the load queue. +A value of zero for this flag is ignored, and the default load queue size is +used instead. +.UNINDENT +.INDENT 0.0 +.TP +.B \-squeue=<store queue size> +Specify the size of the store queue in the load/store unit emulated by the +tool. By default, the tool assumes an unbound number of entries in the store +queue. A value of zero for this flag is ignored, and the default store queue +size is used instead. +.UNINDENT +.INDENT 0.0 +.TP +.B \-timeline +Enable the timeline view. +.UNINDENT +.INDENT 0.0 +.TP +.B \-timeline\-max\-iterations=<iterations> +Limit the number of iterations to print in the timeline view. By default, the +timeline view prints information for up to 10 iterations. +.UNINDENT +.INDENT 0.0 +.TP +.B \-timeline\-max\-cycles=<cycles> +Limit the number of cycles in the timeline view. By default, the number of +cycles is set to 80. +.UNINDENT +.INDENT 0.0 +.TP +.B \-resource\-pressure +Enable the resource pressure view. This is enabled by default. +.UNINDENT +.INDENT 0.0 +.TP +.B \-register\-file\-stats +Enable register file usage statistics. +.UNINDENT +.INDENT 0.0 +.TP +.B \-dispatch\-stats +Enable extra dispatch statistics. This view collects and analyzes instruction +dispatch events, as well as static/dynamic dispatch stall events. This view +is disabled by default. +.UNINDENT +.INDENT 0.0 +.TP +.B \-scheduler\-stats +Enable extra scheduler statistics. This view collects and analyzes instruction +issue events. This view is disabled by default. +.UNINDENT +.INDENT 0.0 +.TP +.B \-retire\-stats +Enable extra retire control unit statistics. This view is disabled by default. +.UNINDENT +.INDENT 0.0 +.TP +.B \-instruction\-info +Enable the instruction info view. This is enabled by default. +.UNINDENT +.INDENT 0.0 +.TP +.B \-all\-stats +Print all hardware statistics. This enables extra statistics related to the +dispatch logic, the hardware schedulers, the register file(s), and the retire +control unit. This option is disabled by default. +.UNINDENT +.INDENT 0.0 +.TP +.B \-all\-views +Enable all the view. +.UNINDENT +.INDENT 0.0 +.TP +.B \-instruction\-tables +Prints resource pressure information based on the static information +available from the processor model. This differs from the resource pressure +view because it doesn\(aqt require that the code is simulated. It instead prints +the theoretical uniform distribution of resource pressure for every +instruction in sequence. +.UNINDENT +.SH EXIT STATUS +.sp +\fBllvm\-mca\fP returns 0 on success. Otherwise, an error message is printed +to standard error, and the tool returns 1. +.SH HOW LLVM-MCA WORKS +.sp +\fBllvm\-mca\fP takes assembly code as input. The assembly code is parsed +into a sequence of MCInst with the help of the existing LLVM target assembly +parsers. The parsed sequence of MCInst is then analyzed by a \fBPipeline\fP module +to generate a performance report. +.sp +The Pipeline module simulates the execution of the machine code sequence in a +loop of iterations (default is 100). During this process, the pipeline collects +a number of execution related statistics. At the end of this process, the +pipeline generates and prints a report from the collected statistics. +.sp +Here is an example of a performance report generated by the tool for a +dot\-product of two packed float vectors of four elements. The analysis is +conducted for target x86, cpu btver2. The following result can be produced via +the following command using the example located at +\fBtest/tools/llvm\-mca/X86/BtVer2/dot\-product.s\fP: +.INDENT 0.0 +.INDENT 3.5 +.sp +.nf +.ft C +$ llvm\-mca \-mtriple=x86_64\-unknown\-unknown \-mcpu=btver2 \-iterations=300 dot\-product.s +.ft P +.fi +.UNINDENT +.UNINDENT +.INDENT 0.0 +.INDENT 3.5 +.sp +.nf +.ft C +Iterations: 300 +Instructions: 900 +Total Cycles: 610 +Dispatch Width: 2 +IPC: 1.48 +Block RThroughput: 2.0 + + +Instruction Info: +[1]: #uOps +[2]: Latency +[3]: RThroughput +[4]: MayLoad +[5]: MayStore +[6]: HasSideEffects (U) + +[1] [2] [3] [4] [5] [6] Instructions: + 1 2 1.00 vmulps %xmm0, %xmm1, %xmm2 + 1 3 1.00 vhaddps %xmm2, %xmm2, %xmm3 + 1 3 1.00 vhaddps %xmm3, %xmm3, %xmm4 + + +Resources: +[0] \- JALU0 +[1] \- JALU1 +[2] \- JDiv +[3] \- JFPA +[4] \- JFPM +[5] \- JFPU0 +[6] \- JFPU1 +[7] \- JLAGU +[8] \- JMul +[9] \- JSAGU +[10] \- JSTC +[11] \- JVALU0 +[12] \- JVALU1 +[13] \- JVIMUL + + +Resource pressure per iteration: +[0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] + \- \- \- 2.00 1.00 2.00 1.00 \- \- \- \- \- \- \- + +Resource pressure by instruction: +[0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: + \- \- \- \- 1.00 \- 1.00 \- \- \- \- \- \- \- vmulps %xmm0, %xmm1, %xmm2 + \- \- \- 1.00 \- 1.00 \- \- \- \- \- \- \- \- vhaddps %xmm2, %xmm2, %xmm3 + \- \- \- 1.00 \- 1.00 \- \- \- \- \- \- \- \- vhaddps %xmm3, %xmm3, %xmm4 +.ft P +.fi +.UNINDENT +.UNINDENT +.sp +According to this report, the dot\-product kernel has been executed 300 times, +for a total of 900 dynamically executed instructions. +.sp +The report is structured in three main sections. The first section collects a +few performance numbers; the goal of this section is to give a very quick +overview of the performance throughput. In this example, the two important +performance indicators are \fBIPC\fP and \fBBlock RThroughput\fP (Block Reciprocal +Throughput). +.sp +IPC is computed dividing the total number of simulated instructions by the total +number of cycles. A delta between Dispatch Width and IPC is an indicator of a +performance issue. In the absence of loop\-carried data dependencies, the +observed IPC tends to a theoretical maximum which can be computed by dividing +the number of instructions of a single iteration by the \fIBlock RThroughput\fP\&. +.sp +IPC is bounded from above by the dispatch width. That is because the dispatch +width limits the maximum size of a dispatch group. IPC is also limited by the +amount of hardware parallelism. The availability of hardware resources affects +the resource pressure distribution, and it limits the number of instructions +that can be executed in parallel every cycle. A delta between Dispatch +Width and the theoretical maximum IPC is an indicator of a performance +bottleneck caused by the lack of hardware resources. In general, the lower the +Block RThroughput, the better. +.sp +In this example, \fBInstructions per iteration/Block RThroughput\fP is 1.50. Since +there are no loop\-carried dependencies, the observed IPC is expected to approach +1.50 when the number of iterations tends to infinity. The delta between the +Dispatch Width (2.00), and the theoretical maximum IPC (1.50) is an indicator of +a performance bottleneck caused by the lack of hardware resources, and the +\fIResource pressure view\fP can help to identify the problematic resource usage. +.sp +The second section of the report shows the latency and reciprocal +throughput of every instruction in the sequence. That section also reports +extra information related to the number of micro opcodes, and opcode properties +(i.e., \(aqMayLoad\(aq, \(aqMayStore\(aq, and \(aqHasSideEffects\(aq). +.sp +The third section is the \fIResource pressure view\fP\&. This view reports +the average number of resource cycles consumed every iteration by instructions +for every processor resource unit available on the target. Information is +structured in two tables. The first table reports the number of resource cycles +spent on average every iteration. The second table correlates the resource +cycles to the machine instruction in the sequence. For example, every iteration +of the instruction vmulps always executes on resource unit [6] +(JFPU1 \- floating point pipeline #1), consuming an average of 1 resource cycle +per iteration. Note that on AMD Jaguar, vector floating\-point multiply can +only be issued to pipeline JFPU1, while horizontal floating\-point additions can +only be issued to pipeline JFPU0. +.sp +The resource pressure view helps with identifying bottlenecks caused by high +usage of specific hardware resources. Situations with resource pressure mainly +concentrated on a few resources should, in general, be avoided. Ideally, +pressure should be uniformly distributed between multiple resources. +.SS Timeline View +.sp +The timeline view produces a detailed report of each instruction\(aqs state +transitions through an instruction pipeline. This view is enabled by the +command line option \fB\-timeline\fP\&. As instructions transition through the +various stages of the pipeline, their states are depicted in the view report. +These states are represented by the following characters: +.INDENT 0.0 +.IP \(bu 2 +D : Instruction dispatched. +.IP \(bu 2 +e : Instruction executing. +.IP \(bu 2 +E : Instruction executed. +.IP \(bu 2 +R : Instruction retired. +.IP \(bu 2 += : Instruction already dispatched, waiting to be executed. +.IP \(bu 2 +\- : Instruction executed, waiting to be retired. +.UNINDENT +.sp +Below is the timeline view for a subset of the dot\-product example located in +\fBtest/tools/llvm\-mca/X86/BtVer2/dot\-product.s\fP and processed by +\fBllvm\-mca\fP using the following command: +.INDENT 0.0 +.INDENT 3.5 +.sp +.nf +.ft C +$ llvm\-mca \-mtriple=x86_64\-unknown\-unknown \-mcpu=btver2 \-iterations=3 \-timeline dot\-product.s +.ft P +.fi +.UNINDENT +.UNINDENT +.INDENT 0.0 +.INDENT 3.5 +.sp +.nf +.ft C +Timeline view: + 012345 +Index 0123456789 + +[0,0] DeeER. . . vmulps %xmm0, %xmm1, %xmm2 +[0,1] D==eeeER . . vhaddps %xmm2, %xmm2, %xmm3 +[0,2] .D====eeeER . vhaddps %xmm3, %xmm3, %xmm4 +[1,0] .DeeE\-\-\-\-\-R . vmulps %xmm0, %xmm1, %xmm2 +[1,1] . D=eeeE\-\-\-R . vhaddps %xmm2, %xmm2, %xmm3 +[1,2] . D====eeeER . vhaddps %xmm3, %xmm3, %xmm4 +[2,0] . DeeE\-\-\-\-\-R . vmulps %xmm0, %xmm1, %xmm2 +[2,1] . D====eeeER . vhaddps %xmm2, %xmm2, %xmm3 +[2,2] . D======eeeER vhaddps %xmm3, %xmm3, %xmm4 + + +Average Wait times (based on the timeline view): +[0]: Executions +[1]: Average time spent waiting in a scheduler\(aqs queue +[2]: Average time spent waiting in a scheduler\(aqs queue while ready +[3]: Average time elapsed from WB until retire stage + + [0] [1] [2] [3] +0. 3 1.0 1.0 3.3 vmulps %xmm0, %xmm1, %xmm2 +1. 3 3.3 0.7 1.0 vhaddps %xmm2, %xmm2, %xmm3 +2. 3 5.7 0.0 0.0 vhaddps %xmm3, %xmm3, %xmm4 +.ft P +.fi +.UNINDENT +.UNINDENT +.sp +The timeline view is interesting because it shows instruction state changes +during execution. It also gives an idea of how the tool processes instructions +executed on the target, and how their timing information might be calculated. +.sp +The timeline view is structured in two tables. The first table shows +instructions changing state over time (measured in cycles); the second table +(named \fIAverage Wait times\fP) reports useful timing statistics, which should +help diagnose performance bottlenecks caused by long data dependencies and +sub\-optimal usage of hardware resources. +.sp +An instruction in the timeline view is identified by a pair of indices, where +the first index identifies an iteration, and the second index is the +instruction index (i.e., where it appears in the code sequence). Since this +example was generated using 3 iterations: \fB\-iterations=3\fP, the iteration +indices range from 0\-2 inclusively. +.sp +Excluding the first and last column, the remaining columns are in cycles. +Cycles are numbered sequentially starting from 0. +.sp +From the example output above, we know the following: +.INDENT 0.0 +.IP \(bu 2 +Instruction [1,0] was dispatched at cycle 1. +.IP \(bu 2 +Instruction [1,0] started executing at cycle 2. +.IP \(bu 2 +Instruction [1,0] reached the write back stage at cycle 4. +.IP \(bu 2 +Instruction [1,0] was retired at cycle 10. +.UNINDENT +.sp +Instruction [1,0] (i.e., vmulps from iteration #1) does not have to wait in the +scheduler\(aqs queue for the operands to become available. By the time vmulps is +dispatched, operands are already available, and pipeline JFPU1 is ready to +serve another instruction. So the instruction can be immediately issued on the +JFPU1 pipeline. That is demonstrated by the fact that the instruction only +spent 1cy in the scheduler\(aqs queue. +.sp +There is a gap of 5 cycles between the write\-back stage and the retire event. +That is because instructions must retire in program order, so [1,0] has to wait +for [0,2] to be retired first (i.e., it has to wait until cycle 10). +.sp +In the example, all instructions are in a RAW (Read After Write) dependency +chain. Register %xmm2 written by vmulps is immediately used by the first +vhaddps, and register %xmm3 written by the first vhaddps is used by the second +vhaddps. Long data dependencies negatively impact the ILP (Instruction Level +Parallelism). +.sp +In the dot\-product example, there are anti\-dependencies introduced by +instructions from different iterations. However, those dependencies can be +removed at register renaming stage (at the cost of allocating register aliases, +and therefore consuming physical registers). +.sp +Table \fIAverage Wait times\fP helps diagnose performance issues that are caused by +the presence of long latency instructions and potentially long data dependencies +which may limit the ILP. Note that \fBllvm\-mca\fP, by default, assumes at +least 1cy between the dispatch event and the issue event. +.sp +When the performance is limited by data dependencies and/or long latency +instructions, the number of cycles spent while in the \fIready\fP state is expected +to be very small when compared with the total number of cycles spent in the +scheduler\(aqs queue. The difference between the two counters is a good indicator +of how large of an impact data dependencies had on the execution of the +instructions. When performance is mostly limited by the lack of hardware +resources, the delta between the two counters is small. However, the number of +cycles spent in the queue tends to be larger (i.e., more than 1\-3cy), +especially when compared to other low latency instructions. +.SS Extra Statistics to Further Diagnose Performance Issues +.sp +The \fB\-all\-stats\fP command line option enables extra statistics and performance +counters for the dispatch logic, the reorder buffer, the retire control unit, +and the register file. +.sp +Below is an example of \fB\-all\-stats\fP output generated by MCA for the +dot\-product example discussed in the previous sections. +.INDENT 0.0 +.INDENT 3.5 +.sp +.nf +.ft C +Dynamic Dispatch Stall Cycles: +RAT \- Register unavailable: 0 +RCU \- Retire tokens unavailable: 0 +SCHEDQ \- Scheduler full: 272 +LQ \- Load queue full: 0 +SQ \- Store queue full: 0 +GROUP \- Static restrictions on the dispatch group: 0 + + +Dispatch Logic \- number of cycles where we saw N instructions dispatched: +[# dispatched], [# cycles] + 0, 24 (3.9%) + 1, 272 (44.6%) + 2, 314 (51.5%) + + +Schedulers \- number of cycles where we saw N instructions issued: +[# issued], [# cycles] + 0, 7 (1.1%) + 1, 306 (50.2%) + 2, 297 (48.7%) + + +Scheduler\(aqs queue usage: +JALU01, 0/20 +JFPU01, 18/18 +JLSAGU, 0/12 + + +Retire Control Unit \- number of cycles where we saw N instructions retired: +[# retired], [# cycles] + 0, 109 (17.9%) + 1, 102 (16.7%) + 2, 399 (65.4%) + + +Register File statistics: +Total number of mappings created: 900 +Max number of mappings used: 35 + +* Register File #1 \-\- JFpuPRF: + Number of physical registers: 72 + Total number of mappings created: 900 + Max number of mappings used: 35 + +* Register File #2 \-\- JIntegerPRF: + Number of physical registers: 64 + Total number of mappings created: 0 + Max number of mappings used: 0 +.ft P +.fi +.UNINDENT +.UNINDENT +.sp +If we look at the \fIDynamic Dispatch Stall Cycles\fP table, we see the counter for +SCHEDQ reports 272 cycles. This counter is incremented every time the dispatch +logic is unable to dispatch a group of two instructions because the scheduler\(aqs +queue is full. +.sp +Looking at the \fIDispatch Logic\fP table, we see that the pipeline was only able +to dispatch two instructions 51.5% of the time. The dispatch group was limited +to one instruction 44.6% of the cycles, which corresponds to 272 cycles. The +dispatch statistics are displayed by either using the command option +\fB\-all\-stats\fP or \fB\-dispatch\-stats\fP\&. +.sp +The next table, \fISchedulers\fP, presents a histogram displaying a count, +representing the number of instructions issued on some number of cycles. In +this case, of the 610 simulated cycles, single +instructions were issued 306 times (50.2%) and there were 7 cycles where +no instructions were issued. +.sp +The \fIScheduler\(aqs queue usage\fP table shows that the maximum number of buffer +entries (i.e., scheduler queue entries) used at runtime. Resource JFPU01 +reached its maximum (18 of 18 queue entries). Note that AMD Jaguar implements +three schedulers: +.INDENT 0.0 +.IP \(bu 2 +JALU01 \- A scheduler for ALU instructions. +.IP \(bu 2 +JFPU01 \- A scheduler floating point operations. +.IP \(bu 2 +JLSAGU \- A scheduler for address generation. +.UNINDENT +.sp +The dot\-product is a kernel of three floating point instructions (a vector +multiply followed by two horizontal adds). That explains why only the floating +point scheduler appears to be used. +.sp +A full scheduler queue is either caused by data dependency chains or by a +sub\-optimal usage of hardware resources. Sometimes, resource pressure can be +mitigated by rewriting the kernel using different instructions that consume +different scheduler resources. Schedulers with a small queue are less resilient +to bottlenecks caused by the presence of long data dependencies. +The scheduler statistics are displayed by +using the command option \fB\-all\-stats\fP or \fB\-scheduler\-stats\fP\&. +.sp +The next table, \fIRetire Control Unit\fP, presents a histogram displaying a count, +representing the number of instructions retired on some number of cycles. In +this case, of the 610 simulated cycles, two instructions were retired during +the same cycle 399 times (65.4%) and there were 109 cycles where no +instructions were retired. The retire statistics are displayed by using the +command option \fB\-all\-stats\fP or \fB\-retire\-stats\fP\&. +.sp +The last table presented is \fIRegister File statistics\fP\&. Each physical register +file (PRF) used by the pipeline is presented in this table. In the case of AMD +Jaguar, there are two register files, one for floating\-point registers +(JFpuPRF) and one for integer registers (JIntegerPRF). The table shows that of +the 900 instructions processed, there were 900 mappings created. Since this +dot\-product example utilized only floating point registers, the JFPuPRF was +responsible for creating the 900 mappings. However, we see that the pipeline +only used a maximum of 35 of 72 available register slots at any given time. We +can conclude that the floating point PRF was the only register file used for +the example, and that it was never resource constrained. The register file +statistics are displayed by using the command option \fB\-all\-stats\fP or +\fB\-register\-file\-stats\fP\&. +.sp +In this example, we can conclude that the IPC is mostly limited by data +dependencies, and not by resource pressure. +.SS Instruction Flow +.sp +This section describes the instruction flow through MCA\(aqs default out\-of\-order +pipeline, as well as the functional units involved in the process. +.sp +The default pipeline implements the following sequence of stages used to +process instructions. +.INDENT 0.0 +.IP \(bu 2 +Dispatch (Instruction is dispatched to the schedulers). +.IP \(bu 2 +Issue (Instruction is issued to the processor pipelines). +.IP \(bu 2 +Write Back (Instruction is executed, and results are written back). *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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