Date: Sat, 01 Dec 2007 11:32:56 -0500 From: "Aryeh M. Friedman" <aryeh.friedman@gmail.com> To: d@delphij.net Cc: Joakim Fogelberg <joafog.lists@gmail.com>, freebsd-current@freebsd.org Subject: Re: 7.0-BETA3, Marvell 88SE6811, P35/ICH9, SATA Message-ID: <47518CB8.8090502@gmail.com> In-Reply-To: <4750A087.2000507@delphij.net> References: <e18c7cda0711301436r650d3fcdlbac00cd37a220cfe@mail.gmail.com> <4750A087.2000507@delphij.net>
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This is a multi-part message in MIME format. --------------060209010306000508080702 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Xin LI wrote: > Joakim Fogelberg wrote: >> I have a MSI P35 Neo2 (MS-7345) mainboard. On the mainboard there >> are two ATA controllers, one IHC9R SATA and one Marvel 88SE6811. >> I just noticed that the Marvel 88SE6811 ATA controller has got >> some kind of identification problems. It used to (beginning of >> november ?) be recognized as a generic ata controller, but now >> (7-beta3) only rubbish is printed in the system message buffer. Your re(4) will also have some issues... you can find the correct patch at: http://people.freebsd.org/~yongari/re/re.HEAD.patch (btw I have exactly the same mobo with 4gb and e6850) also in some cases (I don't know if Xin Li's just posted patch covers this) SATA and PATA will not live in peace together. You will also want some of the ata-id patchs posted earlier under "[ANNOUNCEMENT] Wiki for P35/IHC9(r) created" (or something close to that)... in addition if you have sata/300 drives they will be misreported as 150's (there are different claims on if this is anything beyond cosmetic)... I have attached the patches I use to fix this. The ahci.diff one has been unoffically superseeded (better code style is the only diff I think) but I can find the new one which was sent to me privately. - -- Aryeh M. Friedman FloSoft Systems Developer, not business, friendly http://www.flosoft-systems.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.4 (FreeBSD) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFHUYy4358R5LPuPvsRAr6NAJ9nNDeGoMQ5mQzzDdYonHxt2S2+ugCgsXce EeCxpzOlI4ZGaJMmof4aOpI= =rIRp -----END PGP SIGNATURE----- --------------060209010306000508080702 Content-Type: text/x-patch; name="ahci.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="ahci.diff" --- /usr/src/sys/dev/ata/ata-chipset.c 2007-11-22 10:24:03.000000000 +0300 +++ ata-chipset.c 2007-11-23 11:22:05.000000000 +0300 @@ -94,6 +94,7 @@ static int ata_highpoint_check_80pin(dev static int ata_intel_chipinit(device_t dev); static int ata_intel_allocate(device_t dev); static void ata_intel_reset(device_t dev); +static void ata_intel_setmode(device_t dev, int mode); static void ata_intel_old_setmode(device_t dev, int mode); static void ata_intel_new_setmode(device_t dev, int mode); static int ata_intel_31244_allocate(device_t dev); @@ -1850,6 +1851,7 @@ ata_intel_chipinit(device_t dev) ctlr->allocate = ata_intel_allocate; ctlr->reset = ata_intel_reset; + ctlr->setmode = ata_sata_setmode; /* * if we have AHCI capability and AHCI or RAID mode enabled @@ -1859,8 +1861,14 @@ ata_intel_chipinit(device_t dev) (pci_read_config(dev, 0x90, 1) & 0xc0) && (ata_ahci_chipinit(dev) != ENXIO)) return 0; - - ctlr->setmode = ata_sata_setmode; + else { + ctlr->r_type2 = SYS_RES_IOPORT; + ctlr->r_rid2 = PCIR_BAR(5); + if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, + &ctlr->r_rid2, RF_ACTIVE))) + return ENXIO; + ctlr->setmode = ata_intel_setmode; + } /* enable PCI interrupt */ pci_write_config(dev, PCIR_COMMAND, @@ -1872,6 +1880,7 @@ ata_intel_chipinit(device_t dev) static int ata_intel_allocate(device_t dev) { + struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); struct ata_channel *ch = device_get_softc(dev); /* setup the usual register normal pci style */ @@ -1879,10 +1888,47 @@ ata_intel_allocate(device_t dev) return ENXIO; ch->flags |= ATA_ALWAYS_DMASTAT; + if (ctlr->r_res2 != NULL) { + ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; + ch->r_io[ATA_IDX_ADDR].offset = 0; + ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; + ch->r_io[ATA_IDX_DATA].offset = 4; + } return 0; } static void +ata_intel_setmode(device_t dev, int mode) +{ + struct ata_device *atadev = device_get_softc(dev); + + if (atadev->param.satacapabilities != 0x0000 && + atadev->param.satacapabilities != 0xffff) { + struct ata_channel *ch = device_get_softc(device_get_parent(dev)); + uint32_t idx[] = {0x0000, 0x0200, 0x0100, 0x0300}; + + /* on some drives we need to set the transfer mode */ + ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, + ata_limit_mode(dev, mode, ATA_UDMA6)); + + /* Select channel and ATA_SSTATUS register */ + ATA_IDX_OUTL(ch, ATA_IDX_ADDR, idx[ch->unit]); + + /* query SATA STATUS for the speed */ + if ((ATA_IDX_INL(ch, ATA_IDX_DATA) & ATA_SS_CONWELL_MASK) == + ATA_SS_CONWELL_GEN2) + atadev->mode = ATA_SA300; + else + atadev->mode = ATA_SA150; + } + else { + mode = ata_limit_mode(dev, mode, ATA_UDMA5); + if (!ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode)) + atadev->mode = mode; + } +} + +static void ata_intel_reset(device_t dev) { device_t parent = device_get_parent(dev); --------------060209010306000508080702 Content-Type: text/x-patch; name="i82801-marvell.diff" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="i82801-marvell.diff" Index: ata-chipset.c =================================================================== RCS file: /home/ncvs/src/sys/dev/ata/ata-chipset.c,v retrieving revision 1.202.2.2 diff -u -p -r1.202.2.2 ata-chipset.c --- ata-chipset.c 31 Oct 2007 19:59:53 -0000 1.202.2.2 +++ ata-chipset.c 6 Nov 2007 02:23:57 -0000 @@ -1742,6 +1742,7 @@ ata_intel_ident(device_t dev) { ATA_I82801HB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH8" }, { ATA_I82801HBM_S1, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, { ATA_I82801HBM_S2, 0, AHCI, 0x00, ATA_SA300, "ICH8M" }, + { ATA_I82801HBM_HEM,0, 0, 0x00, ATA_UDMA5, "ICH8M" }, { ATA_I82801IB_S1, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, { ATA_I82801IB_S2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, { ATA_I82801IB_AH2, 0, AHCI, 0x00, ATA_SA300, "ICH9" }, @@ -2344,7 +2345,9 @@ ata_marvell_ident(device_t dev) { ATA_M88SX6041, 0, 4, MV60XX, ATA_SA300, "88SX6041" }, { ATA_M88SX6081, 0, 8, MV60XX, ATA_SA300, "88SX6081" }, { ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" }, - { ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" }, + { ATA_M88SX6121, 0, 1, MV61XX, ATA_SA300, "88SX6121" }, + { ATA_M88SX6141, 0, 1, MV61XX, ATA_SA300, "88SX6121" }, + { ATA_M88SX6145, 0, 2, MV61XX, ATA_SA300, "88SX6145" }, { 0, 0, 0, 0, 0, 0}}; char buffer[64]; Index: ata-pci.h =================================================================== RCS file: /home/ncvs/src/sys/dev/ata/ata-pci.h,v retrieving revision 1.81 diff -u -p -r1.81 ata-pci.h --- ata-pci.h 9 Oct 2007 20:15:09 -0000 1.81 +++ ata-pci.h 6 Nov 2007 02:22:36 -0000 @@ -168,6 +168,7 @@ struct ata_connect_task { #define ATA_I82801HB_S2 0x28258086 #define ATA_I82801HBM_S1 0x28298086 #define ATA_I82801HBM_S2 0x282a8086 +#define ATA_I82801HBM_HEM 0x28508086 #define ATA_I82801IB_S1 0x29208086 #define ATA_I82801IB_AH2 0x29218086 #define ATA_I82801IB_AH6 0x29228086 @@ -195,6 +196,8 @@ struct ata_connect_task { #define ATA_M88SX6041 0x604111ab #define ATA_M88SX6081 0x608111ab #define ATA_M88SX6101 0x610111ab +#define ATA_M88SX6121 0x612111ab +#define ATA_M88SX6141 0x614111ab #define ATA_M88SX6145 0x614511ab #define ATA_MICRON_ID 0x1042 --------------060209010306000508080702 Content-Type: application/octet-stream; name="ahci.diff.sig" Content-Transfer-Encoding: base64 Content-Disposition: attachment; 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