Date: Tue, 14 May 1996 15:34:37 -0700 From: Darryl Okahata <darrylo@hpnmhjw.sr.hp.com> To: hackers@freefall.freebsd.org Subject: Re: Triton chipset with 256k cache caches 32M only? Message-ID: <199605142234.AA067433277@hpnmhjw.sr.hp.com>
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> ECC has single bit error correction and 2 bit error detection. Better than
> parity no matter how you slice it.
The reports on the street say that enabling ECC with Triton II
motherboards involves a 10-15% performance hit, and so T2 ECC may not
always be better than parity. It really depends on your priorities. ;-)
-- Darryl Okahata
Internet: darrylo@sr.hp.com
DISCLAIMER: this message is the author's personal opinion and does not
constitute the support, opinion, or policy of Hewlett-Packard, or of the
little green men that have been following him all day.
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