From owner-freebsd-arm@FreeBSD.ORG Thu Jun 7 09:39:13 2007 Return-Path: X-Original-To: arm@freebsd.org Delivered-To: freebsd-arm@FreeBSD.ORG Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 36EAE16A46B for ; Thu, 7 Jun 2007 09:39:13 +0000 (UTC) (envelope-from nb@synthcom.com) Received: from synthcom.com (static-71-245-103-2.ptldor.fios.verizon.net [71.245.103.2]) by mx1.freebsd.org (Postfix) with ESMTP id 1562E13C43E for ; Thu, 7 Jun 2007 09:39:12 +0000 (UTC) (envelope-from nb@synthcom.com) Received: from static-71-245-103-2.ptldor.fios.verizon.net (static-71-245-103-2.ptldor.fios.verizon.net [71.245.103.2]) by synthcom.com (8.13.8/8.13.8) with ESMTP id l579dC09071037 for ; Thu, 7 Jun 2007 02:39:12 -0700 (PDT) (envelope-from nb@synthcom.com) Date: Thu, 7 Jun 2007 02:39:12 -0700 (PDT) From: Neil Bradley In-Reply-To: <53054.2001:6f8:101e:0:20e:cff:fe6d:6adb.1181203617.squirrel@webmail.alpha-tierchen.de> Message-ID: <20070607023728.X43808@synthcom.com> References: <50503.2001:6f8:101e:0:20e:cff:fe6d:6adb.1181202550.squirrel@webmail.alpha-tierchen.de> <20070607005128.T43808@synthcom.com> <53054.2001:6f8:101e:0:20e:cff:fe6d:6adb.1181203617.squirrel@webmail.alpha-tierchen.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-3.0 (synthcom.com [71.245.103.2]); Thu, 07 Jun 2007 02:39:12 -0700 (PDT) Cc: arm@freebsd.org Subject: Re: 4-bit SD Card mode X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Jun 2007 09:39:13 -0000 >> I've done SD drivers, both 1 and 4 bit, DMA and programmed I/O, on the >> PXA270, Atmel SAM7, Atmel SAM9, and Freescale MX31 CPUs. How may I be of >> assistance? > Actually the driver does the whole status and error handling using an > interrupt service routine. This is unsuitable in 4-bit mode because in > this mode the interrupt line is shared with a data line. So to get 4-bit > mode working it is necessary to know the complete definition of the > "interrupt period" - the period where it is allowed to enable the > interrupt during 4-bit mode. Hm... I haven't ever heard of nor needed to consider such a thing in any of my implementations. The controllers I've encountered all have a "1 bit/4 bit" mode setting, and as long as you tell the card to go in to 4 bit mode and set it in the hardware as well, the SD controller handles everything for you. What is the CPU in question? -->Neil ---------------------------------------------------------------------------- C. Neil Bradley - KE7IXP - The one eyed man in the land of the blind is not king. He's a prisoner.