From owner-freebsd-hardware Fri Aug 18 14:19:44 1995 Return-Path: hardware-owner Received: (from majordom@localhost) by freefall.FreeBSD.org (8.6.11/8.6.6) id OAA24560 for hardware-outgoing; Fri, 18 Aug 1995 14:19:44 -0700 Received: from gndrsh.aac.dev.com (gndrsh.aac.dev.com [198.145.92.241]) by freefall.FreeBSD.org (8.6.11/8.6.6) with ESMTP id OAA24552 for ; Fri, 18 Aug 1995 14:19:38 -0700 Received: (from rgrimes@localhost) by gndrsh.aac.dev.com (8.6.11/8.6.9) id OAA27717; Fri, 18 Aug 1995 14:18:38 -0700 From: "Rodney W. Grimes" Message-Id: <199508182118.OAA27717@gndrsh.aac.dev.com> Subject: Re: i82424ZX vs i82424TX cache dram controller To: pete@sms.fi (Petri Helenius) Date: Fri, 18 Aug 1995 14:18:38 -0700 (PDT) Cc: freebsd-hardware@freebsd.org In-Reply-To: <199508181503.SAA29469@silver.sms.fi> from "Petri Helenius" at Aug 18, 95 06:03:25 pm X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Length: 1111 Sender: hardware-owner@freebsd.org Precedence: bulk > > Rodney W. Grimes writes: > > > > > > > still no rev message--from looking at source that seems to be in > > > -current and 2.0.5R but not in 2.0R > > > > Oopss.. your running old code :-(... > > What one should enable to get the verbose probe in 2.2-CURRENT? I get only: boot with the -v flag. > chip0 rev 1 on pci0:0 > chip1 rev 2 on pci0:7 > > ...and I'm wondering whether there is any parity checking on the chipset. Intel Triton does NOT have parity checking logic in the memory controller circuits. There is not parity checking in the chip set. > (I've been told that it's unlikely) You've now been told it does not, plain and simple. [I would have done this a long time ago, but NDA's are nasty things, Intel made this public information 3 weeks ago with the release of the Triton data sheets to the public, then formally stated it just recently (week or so) in a press release. -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Reliable computers for FreeBSD