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Date:      13 Feb 2003 23:04:17 -0800
From:      Eric Anholt <eta@lclark.edu>
To:        Marcel Moolenaar <marcel@xcllnt.net>
Cc:        src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org
Subject:   Re: cvs commit: src/sys/modules Makefile
Message-ID:  <1045206256.84507.99.camel@leguin>
In-Reply-To: <20030214061708.GA2109@athlon.pn.xcllnt.net>
References:  <20030213223058.769DA2A8C1@canning.wemm.org> <1045185451.11981.17.camel@leguin> <20030214023218.GA1573@athlon.pn.xcllnt.net> <1045194133.11981.87.camel@leguin> <20030214043028.GA1797@athlon.pn.xcllnt.net> <1045200753.84507.54.camel@leguin> <20030214061708.GA2109@athlon.pn.xcllnt.net>

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On Thu, 2003-02-13 at 22:17, Marcel Moolenaar wrote:
> On Thu, Feb 13, 2003 at 09:32:33PM -0800, Eric Anholt wrote:
> > > 
> > > In that case, we'd better make sure there's cache coherency. Do we
> > > actually have the code structured in a way that allows having the
> > > flushing chipset dependent (not to mention dependent on the address)?
> > 
> > No, currently all the cache flushes (four in agp.c, three in i810 and
> > amd code) are unconditional agp_flush_cache calls after modifying the
> > gatt entries.  They aren't tied to a specific memory range, but could be
> > pretty easily, if not the most efficiently, by pushing some of them into
> > the (un)bind_pages.  There's probably a better way.
> 
> I wonder: do we actually need to flush at all? GART updates are PCI/AGP
> writes and should be coherent, right?
> Isn't updating the SGM (system graphics memory) itself that needs
> cache flushes to make sure the AGP device gets the right data?
> 
> Also, on ia64 bus I/O is done with a virtual address that has the
> non-cacheable property. Flushing would not be required irrespective.

Ack!  For the i810 case, that's true.  For some reason I had been
thinking that they were all acting like agp_amd.c, which just writes to
the vaddr of the malloced/busdma'ed gatt.  Maybe chipset-specific
flushing would be a good idea.

Not sure quite what you mean by SGM.  Are you referring to what the i810
does?  If so, that ought to be referenced through the (coherent)
aperture, I would think.  Also a little confused by the ia64 thing.  How
is that going to behave differently than an i386 then? Not reorder
writes to the bus?

> Anyway: the nit was about having conditional compilation based on the
> architecture, not whether the code was actually required. When in doubt,
> commit the code :-)

Committed the update, anyway.

-- 
Eric Anholt                                eta@lclark.edu          
http://people.freebsd.org/~anholt/         anholt@FreeBSD.org


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