Date: Mon, 28 Sep 1998 06:47:24 -0700 (PDT) From: Peter Wemm <peter@FreeBSD.ORG> To: cvs-committers@FreeBSD.ORG, cvs-all@FreeBSD.ORG Subject: cvs commit: src/sys/i386/i386 mpapic.c Message-ID: <199809281347.GAA14248@freefall.freebsd.org>
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peter 1998/09/28 06:47:24 PDT
Modified files:
sys/i386/i386 mpapic.c
Log:
Fix (?) EISA interrupt configuration based on observation of what we've
seen in practice. The MPspec is ambiguous and/or contradicts itself.
We now look at the ELCR to determine the trigger mode (edge/level) of an
interrupt tagged as "conforming" in the mptable. EISA interrupts appear
to be presented to the APIC as active high in all cases (they are level
inverted) that we've seen, so use this for the 'conforming' level case.
Of note, the system I'm using has 2 PCI cards in it, and the PCI cards
interrupts (5 and 9) appear in the ELCR register as level sensitive and the
mptable lists 5 and 9 as coming from the EISA bus. The PCI interrupts
are active-high by the time they reach the APIC even though they are
electrically active low at the slot.
We should still work should somebody implement this on motherboards
differently in the future as long as the mptable is clear about the
trigger/polarity.
Current should work on Holm Tiffe's machine now.
Based on code from: Tor.Egge@fast.no
Revision Changes Path
1.33 +9 -26 src/sys/i386/i386/mpapic.c
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