From owner-svn-src-stable-8@FreeBSD.ORG Thu Oct 29 23:10:12 2009 Return-Path: Delivered-To: svn-src-stable-8@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 076AD106566C; Thu, 29 Oct 2009 23:10:12 +0000 (UTC) (envelope-from thompsa@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id E74358FC19; Thu, 29 Oct 2009 23:10:11 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n9TNABeB013747; Thu, 29 Oct 2009 23:10:11 GMT (envelope-from thompsa@svn.freebsd.org) Received: (from thompsa@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n9TNABh3013745; Thu, 29 Oct 2009 23:10:11 GMT (envelope-from thompsa@svn.freebsd.org) Message-Id: <200910292310.n9TNABh3013745@svn.freebsd.org> From: Andrew Thompson Date: Thu, 29 Oct 2009 23:10:11 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org X-SVN-Group: stable-8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r198632 - in stable/8/sys: . amd64/include/xen cddl/contrib/opensolaris contrib/dev/acpica contrib/pf dev/usb/net dev/xen/xenpci X-BeenThere: svn-src-stable-8@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for only the 8-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Oct 2009 23:10:12 -0000 Author: thompsa Date: Thu Oct 29 23:10:11 2009 New Revision: 198632 URL: http://svn.freebsd.org/changeset/base/198632 Log: MFC r196491 We used force all of the GPIO pins low first and then enable the ones we want. This has been changed to better match the ADMtek's reference design to avoid setting the power-down configuration line of the PHY at the same time it is reset. Modified: stable/8/sys/ (props changed) stable/8/sys/amd64/include/xen/ (props changed) stable/8/sys/cddl/contrib/opensolaris/ (props changed) stable/8/sys/contrib/dev/acpica/ (props changed) stable/8/sys/contrib/pf/ (props changed) stable/8/sys/dev/usb/net/if_aue.c stable/8/sys/dev/xen/xenpci/ (props changed) Modified: stable/8/sys/dev/usb/net/if_aue.c ============================================================================== --- stable/8/sys/dev/usb/net/if_aue.c Thu Oct 29 23:09:37 2009 (r198631) +++ stable/8/sys/dev/usb/net/if_aue.c Thu Oct 29 23:10:11 2009 (r198632) @@ -484,7 +484,7 @@ aue_miibus_writereg(device_t dev, int ph } if (i == AUE_TIMEOUT) - device_printf(sc->sc_ue.ue_dev, "MII read timed out\n"); + device_printf(sc->sc_ue.ue_dev, "MII write timed out\n"); if (!locked) AUE_UNLOCK(sc); @@ -603,11 +603,14 @@ aue_reset(struct aue_softc *sc) * to set the GPIO pins high so that the PHY(s) will * be enabled. * - * Note: We force all of the GPIO pins low first, *then* - * enable the ones we want. + * NOTE: We used to force all of the GPIO pins low first and then + * enable the ones we want. This has been changed to better + * match the ADMtek's reference design to avoid setting the + * power-down configuration line of the PHY at the same time + * it is reset. */ - aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_OUT0|AUE_GPIO_SEL0); - aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_OUT0|AUE_GPIO_SEL0|AUE_GPIO_SEL1); + aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1); + aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1|AUE_GPIO_OUT0); if (sc->sc_flags & AUE_FLAG_LSYS) { /* Grrr. LinkSys has to be different from everyone else. */