From owner-p4-projects@FreeBSD.ORG Tue Jul 17 11:30:59 2012 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 407E41065676; Tue, 17 Jul 2012 11:30:57 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id DC5D01065673 for ; Tue, 17 Jul 2012 11:30:56 +0000 (UTC) (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:4f8:fff6::2d]) by mx1.freebsd.org (Postfix) with ESMTP id C2F5E8FC1D for ; Tue, 17 Jul 2012 11:30:56 +0000 (UTC) Received: from skunkworks.freebsd.org (localhost [127.0.0.1]) by skunkworks.freebsd.org (8.14.4/8.14.4) with ESMTP id q6HBUuRs046385 for ; Tue, 17 Jul 2012 11:30:56 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.4/8.14.4/Submit) id q6HBUuWJ046382 for perforce@freebsd.org; Tue, 17 Jul 2012 11:30:56 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Date: Tue, 17 Jul 2012 11:30:56 GMT Message-Id: <201207171130.q6HBUuWJ046382@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to bb+lists.freebsd.perforce@cyrus.watson.org using -f From: Robert Watson To: Perforce Change Reviews Precedence: bulk Cc: Subject: PERFORCE change 214509 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Jul 2012 11:30:59 -0000 http://p4web.freebsd.org/@@214509?ac=10 Change 214509 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/07/17 11:30:23 Catch up on CHERI kernel compilation following integration from the FreeBSD/BERI branch (adding options CAPABILITIES) and CHERI assembler changes: - Replace CHERI-level "struct capability" with "struct chericap" to avoid a collision with Capsicum. This may lead to further pondering. - Reorder arguments to CHERI load and store via capability instruction use to employ new indexed notation. - Prefer csetlen to removed cdecleng. Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.c#10 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#5 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheriasm.h#4 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cp2.c#10 (text+ko) ==== @@ -67,7 +67,7 @@ */ void -cp2_capability_set(struct capability *cp, uint32_t uperms, +cp2_capability_set(struct chericap *cp, uint32_t uperms, void *otypep /* eaddr */, void *basep, uint64_t length) { @@ -86,7 +86,7 @@ * contexts. */ void -cp2_capability_set_priv(struct capability *cp) +cp2_capability_set_priv(struct chericap *cp) { cp2_capability_set(cp, CHERI_CAP_PRIV_UPERMS, CHERI_CAP_PRIV_OTYPE, @@ -94,7 +94,7 @@ } void -cp2_capability_set_user(struct capability *cp) +cp2_capability_set_user(struct chericap *cp) { cp2_capability_set(cp, CHERI_CAP_USER_UPERMS, CHERI_CAP_USER_OTYPE, @@ -102,7 +102,7 @@ } void -cp2_capability_set_null(struct capability *cp) +cp2_capability_set_null(struct chericap *cp) { cp2_capability_set(cp, CHERI_CAP_NOPRIV_UPERMS, @@ -121,7 +121,7 @@ * XXXRW: Compiler should be providing us with the temporary register. */ void -cp2_capability_copy(struct capability *cp_to, struct capability *cp_from) +cp2_capability_copy(struct chericap *cp_to, struct chericap *cp_from) { cp2_capability_load(CHERI_CR_CT0, cp_from); @@ -488,7 +488,7 @@ #ifdef DDB #define DB_CP2_REG_PRINT_NUM(crn, num) do { \ - struct capability c; \ + struct chericap c; \ \ CP2_CR_GET((crn), c); \ db_printf("C%u perms %08jx otype %016jx\n", num, \ @@ -561,14 +561,14 @@ /* Laboriously load and print each capability. */ for (i = 0; i < 25; i++) { cp2_capability_load(CHERI_CR_CT0, - (struct capability *)&cfp->cf_c0 + i); + (struct chericap *)&cfp->cf_c0 + i); DB_CP2_REG_PRINT_NUM(CHERI_CR_CT0, i); } db_printf("\nTSC and PCC:\n"); - cp2_capability_load(CHERI_CR_CT0, (struct capability *)&cfp->cf_c0 + + cp2_capability_load(CHERI_CR_CT0, (struct chericap *)&cfp->cf_c0 + CHERI_CR_TSC_OFF); DB_CP2_REG_PRINT_NUM(CHERI_CR_CT0, CHERI_CR_TSC); - cp2_capability_load(CHERI_CR_CT0, (struct capability *)&cfp->cf_c0 + + cp2_capability_load(CHERI_CR_CT0, (struct chericap *)&cfp->cf_c0 + CHERI_CR_PCC_OFF); DB_CP2_REG_PRINT_NUM(CHERI_CR_CT0, CHERI_CR_EPCC); } ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#5 (text+ko) ==== @@ -41,7 +41,7 @@ * Canonical C-language representation of a capability. */ #define CAPABILITY_SIZE 32 -struct capability { +struct chericap { uint32_t c_uperms; uint32_t c_reserved; union { @@ -52,7 +52,7 @@ uint64_t c_length; } __packed __aligned(CAPABILITY_SIZE); #ifdef _KERNEL -CTASSERT(sizeof(struct capability) == CAPABILITY_SIZE); +CTASSERT(sizeof(struct chericap) == CAPABILITY_SIZE); #endif /* @@ -65,7 +65,7 @@ #ifdef _KERNEL struct cp2_frame { /* c0 has special properties for MIPS load/store instructions. */ - struct capability cf_c0; + struct chericap cf_c0; /* * General-purpose capabilities -- note, numbering is from v1.3 of @@ -73,21 +73,21 @@ * purpose capabilities to be at the bottom, rather than the top, of * the capability register space (per Ross Anderson's suggestion). */ - struct capability cf_c1, cf_c2, cf_c3, cf_c4; - struct capability cf_c5, cf_c6, cf_c7; - struct capability cf_c8, cf_c9, cf_c10, cf_c11, cf_c12; - struct capability cf_c13, cf_c14, cf_c15, cf_c16, cf_c17; - struct capability cf_c18, cf_c19, cf_c20, cf_c21, cf_c22; - struct capability cf_c23, cf_c24; + struct chericap cf_c1, cf_c2, cf_c3, cf_c4; + struct chericap cf_c5, cf_c6, cf_c7; + struct chericap cf_c8, cf_c9, cf_c10, cf_c11, cf_c12; + struct chericap cf_c13, cf_c14, cf_c15, cf_c16, cf_c17; + struct chericap cf_c18, cf_c19, cf_c20, cf_c21, cf_c22; + struct chericap cf_c23, cf_c24; /* * Special-purpose capability registers that must be preserved on a * user context switch. Note that KT0, KT1, KCC, and KDC are omitted. */ - struct capability cf_tsc; + struct chericap cf_tsc; /* Program counter capability. */ - struct capability cf_pcc; + struct chericap cf_pcc; }; CTASSERT(sizeof(struct cp2_frame) == (27 * CAPABILITY_SIZE)); #endif @@ -123,8 +123,8 @@ #define CP2_CR_STORE(crn_from, crn_base, offset) do { \ __asm__ __volatile__ ( \ - "cscr $c%0, $c%1, %2; " : \ - : "i" (crn_from), "i" (crn_base), "r" (offset)); \ + "cscr $c%0, %1($c%2); " : \ + : "i" (crn_from), "r" (offset), "i" (crn_base)); \ } while (0) /* @@ -188,36 +188,36 @@ #define CP2_CR_SET_LENGTH(crn_to, crn_from, v) do { \ if ((crn_to) == 0) \ __asm__ __volatile__ ( \ - "cdecleng $c%0, $c%1, %2; " : \ + "csetlen $c%0, $c%1, %2; " : \ : "i" (crn_to), "i" (crn_from), "r" (v) : \ "memory"); \ else \ __asm__ __volatile__ ( \ - "cdecleng $c%0, $c%1, %2; " : \ + "csetlen $c%0, $c%1, %2; " : \ : "i" (crn_to), "i" (crn_from), "r" (v)); \ } while (0) #define CP2_CR_LOAD(crn_to, crn_base, offset) do { \ if ((crn_to) == 0) \ __asm__ __volatile__ ( \ - "clcr $c%0, $c%1, %2; " : \ - : "i" (crn_to), "i" (crn_base), "r" (offset) : \ + "clcr $c%0, %1($c%2); " : \ + : "i" (crn_to), "r" (offset), "i" (crn_base) : \ "memory"); \ else \ __asm__ __volatile__ ( \ - "clcr $c%0, $c%1, %2; " : \ - : "i" (crn_to), "i" (crn_base), "r" (offset)); \ + "clcr $c%0, %1($c%2); " : \ + : "i" (crn_to), "r" (offset), "i" (crn_base)); \ } while (0) static inline void -cp2_capability_load(u_int crn_to, struct capability *cp) +cp2_capability_load(u_int crn_to, struct chericap *cp) { CP2_CR_LOAD(crn_to, CHERI_CR_KDC, cp); } static inline void -cp2_capability_store(u_int crn_from, struct capability *cp) +cp2_capability_store(u_int crn_from, struct chericap *cp) { CP2_CR_STORE(crn_from, CHERI_CR_KDC, cp); @@ -257,50 +257,50 @@ */ #define CP2_LOAD_BYTE_VIA(crn, offset, b) do { \ __asm__ __volatile__ ( \ - "clbr %0, $c%1, %2; " : \ - "=r" (b) : "i" (crn), "r" (offset) : "memory"); \ + "clbr %0, %1($c%2); " : \ + "=r" (b) : "r" (offset), "i" (crn) : "memory"); \ } while (0) #define CP2_LOAD_HWORD_VIA(crn, offset, h) do { \ __asm__ __volatile__ ( \ - "clhr %0, $c%1, %2; " : \ - "=r" (b) : "i" (crn), "r" (offset) : "memory"); \ + "clhr %0, %1($c%2); " : \ + "=r" (b) : "r" (offset), "i" (crn) : "memory"); \ } while (0) #define CP2_LOAD_WORD_VIA(crn, offset, w) do { \ __asm__ __volatile__ ( \ - "clwr %0, $c%1, %2; " : \ - "=r" (w) : "i" (crn), "r" (offset) : "memory"); \ + "clwr %0, %1($c%2); " : \ + "=r" (w) : "r" (offset), "i" (crn) : "memory"); \ } while (0) #define CP2_LOAD_DWORD_VIA(crn, offset, d) do { \ __asm__ __volatile__ ( \ - "cldr %0, $c%1, %2; " : \ - "=r" (d) : "i" (crn), "r" (offset) : "memory"); \ + "cldr %0, %1($c%2); " : \ + "=r" (d) : "r" (offset), "i" (crn) : "memory"); \ } while (0) #define CP2_STORE_BYTE_VIA(crn, offset, b) do { \ __asm__ __volatile__ ( \ - "csbr %0, $c%1, %2; " : \ - : "r" (b), "i" (crn), "r" (offset) : "memory"); \ + "csbr %0, %1($c%2); " : \ + : "r" (b), "r" (offset), "i" (crn) : "memory"); \ } while (0) #define CP2_STORE_HWORD_VIA(crn, offset, h) do { \ __asm__ __volatile__ ( \ - "cshr %0, $c%1, %2; " : \ - : "r" (h), "i" (crn), "r" (offset) : "memory"); \ + "cshr %0, %1($c%2); " : \ + : "r" (h), "r" (offset), "i" (crn) : "memory"); \ } while (0) #define CP2_STORE_WORD_VIA(crn, offset, w) do { \ __asm__ __volatile__ ( \ - "cswr %0, $c%1, %2; " : \ - : "r" (w), "i" (crn), "r" (offset) : "memory"); \ + "cswr %0, %1($c%2); " : \ + : "r" (w), "r" (offset), "i" (crn) : "memory"); \ } while (0) #define CP2_STORE_DWORD_VIA(crn, offset, d) do { \ __asm__ __volatile__ ( \ - "csdr %0, $c%1, %2; " : \ - : "r" (d), "i" (crn), "r" (offset) : "memory"); \ + "csdr %0, %1($c%2); " : \ + : "r" (d), "r" (offset), "i" (crn) : "memory"); \ } while (0) /* @@ -315,13 +315,12 @@ * APIs that act on C language representations of capabilities -- but not * capabilities themselves. */ -void cp2_capability_copy(struct capability *cp_to, - struct capability *cp_from); -void cp2_capability_set(struct capability *cp, uint32_t uperms, +void cp2_capability_copy(struct chericap *cp_to, struct chericap *cp_from); +void cp2_capability_set(struct chericap *cp, uint32_t uperms, void *otypep /* eaddr */, void *basep, uint64_t length); -void cp2_capability_set_priv(struct capability *cp); -void cp2_capability_set_user(struct capability *cp); -void cp2_capability_set_null(struct capability *cp); +void cp2_capability_set_priv(struct chericap *cp); +void cp2_capability_set_user(struct chericap *cp); +void cp2_capability_set_null(struct chericap *cp); #ifdef _KERNEL /* ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheriasm.h#4 (text+ko) ==== @@ -79,11 +79,11 @@ #define SZCAP 32 #define SAVE_U_PCB_CP2REG(treg, creg, offs, base) \ daddu treg, base, U_PCB_CP2FRAME + (SZCAP * offs); \ - cscr creg, $c30, treg + cscr creg, treg($c30) #define RESTORE_U_PCB_CP2REG(treg, creg, offs, base) \ daddu treg, base, U_PCB_CP2FRAME + (SZCAP * offs); \ - clcr creg, $c30, treg + clcr creg, treg($c30) /* * XXXRW: Update once the assembler supports reserved CP2 register names to