Date: Wed, 4 Apr 2007 00:18:46 +0200 From: Bernd Walter <ticso@cicely12.cicely.de> To: Warner Losh <imp@bsdimp.com> Cc: ticso@cicely12.cicely.de, freebsd-arm@FreeBSD.org, ticso@cicely.de Subject: Re: adding 16550 UART to RM9200 Message-ID: <20070403221846.GU80382@cicely12.cicely.de> In-Reply-To: <20070403.135419.74695322.imp@bsdimp.com> References: <20070403154858.GR80382@cicely12.cicely.de> <20070403.100732.74697496.imp@bsdimp.com> <20070403185553.GS80382@cicely12.cicely.de> <20070403.135419.74695322.imp@bsdimp.com>
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On Tue, Apr 03, 2007 at 01:54:19PM -0600, Warner Losh wrote: > > I might consider running only 3 boards on IRQ0 and the other 3 on IRQ3. > > Although the RM9200 has 7 external interrupts (not counting FIQ), the > > remaining IRQ* all collide :( > > - IRQ0 unshared > > - IRQ1 TWCK needed for my external RTC > > - IRQ2 TWD same as above > > - IRQ3 TXD2 I can easily accept loosing this UART with the new ones > > - IRQ4 SPCK needed for dataflash booting and I don't want to switch to > > iic-eeprom for booting > > - IRQ5 NPCS0 same as above > > - IRQ6 Ethernet MDIO > > > > I could free 2 IRQ if I either run without IIC or SPI, but this still > > wouldn't give me the ideal of 6 lines. > > Have you considered just using a GPIO pin for this and routing the > interrupt that way? There's code there now to cope with the change of > level in the GPIO pins. That way you'd only have to read one register > and mask out the pins you want. The only mild gotcha here is that the > interrupt is for signal change, not for a level, iirc. Surely you > haven't used up all the I/O lines. No - hadn't thought about it, but I've learned on 6502 and I love level based interrupts. You are right - only change interrupts are possible with PIO. Would have been a good idea, but 48 PIO lines for interrupt might be ok if I would do a complete board design, but I start with the existing board and handwire the new lines, so 48 lines are not an option. I'm happy that most needed lines are available on the low desity SDRAM chips, but the PIO are not... 6 PIO based interrupt lines with an ILR for each board is a problem as well as the UART can't easily share edged interrupts and I don't want to play tricks as done in the famous AST 4 port. I'll likely stay with 2 level interrupts shared over 3 boards each with an 8-source ILR. Asking the ILR is slower than PIO, but servicing the interrupt will do many more access than those 3 for the ILR group. The access time will be something around 70-100ns, which is not very fast, but match the worst case requirement between different UART vendors. > P.S. You never answered my question about giving me one :-) that's > OK, it was a joke anyway. I know :) But I don't build a 48 port device right from the start. Likely I will do a single extension board doing the SMC buffering plus 2 8-port boards to start with. There is nothing to give away at the beginning :( -- B.Walter http://www.bwct.de http://www.fizon.de bernd@bwct.de info@bwct.de support@fizon.de
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