Date: Sun, 18 Aug 1996 00:45:12 +0200 (MET DST) From: Thomas Sparrevohn <staff@kyklopen.ping.dk> To: freebsd-current@freebsd.org Subject: My Gumby 82439HX diffs Message-ID: <Pine.BSI.3.95.960818003546.491A-100000@kyklopen>
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Thanks to everybody that responded. But I must have hit my head with a
brick and the M_EN's was wrong. Please try this patch it contains the
registerdump for the 82439HX and the 82371SB. The only real difference
between the 82371SB and the 82371FB that concerns the registers dumped
is the APIC select field.
This is the new patch.
Regards
Thomas
*** pcisupport.c#ctm Thu Aug 15 21:42:23 1996
--- pcisupport.c Sun Aug 18 00:32:12 1996
***************
*** 131,136 ****
--- 131,140 ----
return ("Intel 82437 (Triton) PCI cache memory controller");
case 0x122e8086:
return ("Intel 82371 (Triton) PCI-ISA bridge");
+ case 0x12508086:
+ return ("Intel 82439HX (Triton II) PCI cache memory controller");
+ case 0x70008086:
+ return ("Intel 82371SB (Triton II) PCI-ISA bridge");
case 0x04961039:
return ("SiS 85c496");
case 0x04061039:
***************
*** 463,468 ****
--- 467,562 ----
{ 0 }
};
+ static const struct condmsg conf82439hx[] =
+ {
+ /* PCON -- PCI Control Register */
+ { 0x00, 0x00, 0x00, M_TR, "\tDRAM ECC/Parity:" },
+ { 0x50, 0x80, 0x80, M_EQ, " ECC" },
+ { 0x50, 0x80, 0x00, M_EQ, " Parity" },
+ { 0x00, 0x00, 0x00, M_TR, ", ECC Test " },
+ { 0x50, 0x40, 0x40, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tShutdown to Port 92 " },
+ { 0x50, 0x20, 0x20, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ", Dual Processor NA# " },
+ { 0x50, 0x10, 0x10, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tPeer Concurrency " },
+ { 0x50, 0x08, 0x08, M_EN, 0 },
+ /* XXX I am not sure thats the SERR# output type is usefull */
+ { 0x00, 0x00, 0x00, M_TR, ", SERR# Output Type:" },
+ { 0x50, 0x04, 0x04, M_EQ, " Normal output" },
+ { 0x50, 0x04, 0x00, M_EQ, " Open drain output" },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tGlobal TXC " },
+ { 0x50, 0x01, 0x01, M_EN, 0 },
+
+ /* CC -- Cache Control Regsiter */
+ { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" },
+ { 0x52, 0xc0, 0x80, M_EQ, " 512K" },
+ { 0x52, 0xc0, 0x40, M_EQ, " 256K" },
+ { 0x52, 0xc0, 0x00, M_EQ, " NO" },
+ { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" },
+ { 0x52, 0x30, 0x10, M_EQ, " reserved" },
+ { 0x52, 0x30, 0x20, M_EQ, " reserved" },
+ { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
+ { 0x00, 0x00, 0x00, M_TR, ", NA Disable: " },
+ { 0x52, 0x04, 0x04, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tExtended Cacheability " },
+ { 0x52, 0x04, 0x04, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ", SCFMI "},
+ { 0x52, 0x02, 0x02, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ", L1 " },
+ { 0x52, 0x01, 0x01, M_EN, 0 },
+
+ /* DRAMEC -- DRAM Extended Control Register */
+ { 0x00, 0x00, 0x00, M_TR, "\n\tSpeculative Leadoff " },
+ { 0x56, 0x10, 0x10, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ", Turn-around Insertion " },
+ { 0x56, 0x08, 0x08, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tMemory Address Drive Strength: " },
+ { 0x56, 0x06, 0x00, M_EQ, "8mA/8mA" },
+ { 0x56, 0x06, 0x02, M_EQ, "8mA/12mA" },
+ { 0x56, 0x06, 0x04, M_EQ, "12mA/8mA" },
+ { 0x56, 0x06, 0x06, M_EQ, "12mA/12mA" },
+ { 0x00, 0x00, 0x00, M_TR, ", 64 Mbit mode " },
+ { 0x56, 0x01, 0x01, M_EN, 0 },
+
+ /* DRAMC - DRAM Control Register */
+ { 0x00, 0x00, 0x00, M_TR, "\n\tHole: " },
+ { 0x57, 0xc0, 0x00, M_EQ, "None" },
+ { 0x57, 0xc0, 0x40, M_EQ, "512KB - 640KB" },
+ { 0x00, 0x00, 0x00, M_TR, ", EDO Detect mode " },
+ { 0x57, 0x04, 0x04, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tDRAM Refrest Rate " },
+ { 0x57, 0x07, 0x00, M_EQ, "Disabled" },
+ { 0x57, 0x07, 0x01, M_EQ, "50Mhz" },
+ { 0x57, 0x07, 0x02, M_EQ, "60Mhz" },
+ { 0x57, 0x07, 0x03, M_EQ, "66Mhz" },
+
+ /* DRAMT -- DRAM Timing Register */
+ { 0x00, 0x00, 0x00, M_TR, "\n\tTurbo Read Leadoff " },
+ { 0x58, 0x80, 0x80, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tDRAM Read Burst Timing: " },
+ { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" },
+ { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" },
+ { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tDRAM Write Burst Timing: " },
+ { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" },
+ { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" },
+ { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" },
+ { 0x00, 0x00, 0x00, M_TR, ",\n\tFast RAS to CAS Delay: " },
+ { 0x58, 0x04, 0x00, M_EQ, "3" },
+ { 0x58, 0x04, 0x04, M_EQ, "2" },
+ { 0x00, 0x00, 0x00, M_TR, " clocks,\n\tDRAM leadoff Timing: " },
+ { 0x58, 0x03, 0x00, M_EQ, "Read 7, Write 6, Precharge 3, Refresh 4" },
+ { 0x58, 0x03, 0x01, M_EQ, "Read 6, Write 5, Precharge 3, Refresh 4" },
+ { 0x58, 0x03, 0x02, M_EQ, "Read 7, Write 6, Precharge 4, Refresh 5" },
+ { 0x58, 0x03, 0x03, M_EQ, "Read 6, Write 5, Precharge 4, Refresh 5" },
+ { 0x00, 0x00, 0x00, M_TR, "\n" },
+
+ /* end marker */
+ { 0 }
+
+ };
+
static const struct condmsg conf82371fb[] =
{
/* IORT -- ISA I/O Recovery Timer Register */
***************
*** 528,533 ****
--- 622,707 ----
{ 0 }
};
+ /* The 82371fb and the 82371sb are allmost identical in
+ function 0, but a few registers values are different */
+
+ static const struct condmsg conf82371sb[] =
+ {
+ /* IORT -- ISA I/O Recovery Timer Register */
+ { 0x00, 0x00, 0x00, M_TR, "\tDMA Reserved Page Register Aliasing " },
+ { 0x4c, 0x80, 0x80, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, "\n\t8-Bit I/O Recovery: " },
+ { 0x4c, 0x40, 0x40, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, "\n\tI/O Recovery Timing: 8-bit " },
+ { 0x4c, 0x40, 0x00, M_EQ, "3.5" },
+ { 0x4c, 0x78, 0x48, M_EQ, "1" },
+ { 0x4c, 0x78, 0x50, M_EQ, "2" },
+ { 0x4c, 0x78, 0x58, M_EQ, "3" },
+ { 0x4c, 0x78, 0x60, M_EQ, "4" },
+ { 0x4c, 0x78, 0x68, M_EQ, "5" },
+ { 0x4c, 0x78, 0x70, M_EQ, "6" },
+ { 0x4c, 0x78, 0x78, M_EQ, "7" },
+ { 0x4c, 0x78, 0x40, M_EQ, "8" },
+ { 0x00, 0x00, 0x00, M_TR, " clocks, 16-bit " },
+ { 0x4c, 0x04, 0x00, M_EQ, "3.5" },
+ { 0x4c, 0x07, 0x05, M_EQ, "1" },
+ { 0x4c, 0x07, 0x06, M_EQ, "2" },
+ { 0x4c, 0x07, 0x07, M_EQ, "3" },
+ { 0x4c, 0x07, 0x04, M_EQ, "4" },
+ { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
+
+ /* XBCS -- X-Bus Chip Select Register 4e-4f in PIIX3 */
+ { 0x00, 0x00, 0x00, M_TR, "\tAPIC Chip Select: " },
+ { 0x4f, 0x01, 0x01, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, "\n\tExtended BIOS: " },
+ { 0x4e, 0x80, 0x80, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, "\n\tLower BIOS: " },
+ { 0x4e, 0x40, 0x40, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, "\n\tCoprocessor IRQ13: " },
+ { 0x4e, 0x20, 0x20, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, "\n\tMouse IRQ12: " },
+ { 0x4e, 0x10, 0x10, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, "\n\tBIOSCS# Write Protect: " },
+ { 0x4e, 0x04, 0x04, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, "\n\tKeyboard Controller Address Location: " },
+ { 0x4e, 0x02, 0x02, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, "\n\tRTC Address Location: " },
+ { 0x4e, 0x01, 0x01, M_EN, 0 },
+ { 0x00, 0x00, 0x00, M_TR, "\n" },
+
+ { 0x00, 0x00, 0x00, M_TR, "\tInterrupt Routing: " },
+ #define PIRQ(x, n) \
+ { 0x00, 0x00, 0x00, M_TR, n ": " }, \
+ { x, 0x80, 0x80, M_EQ, "disabled" }, \
+ { x, 0xc0, 0x40, M_EQ, "[shared] " }, \
+ { x, 0x8f, 0x03, M_EQ, "IRQ3" }, \
+ { x, 0x8f, 0x04, M_EQ, "IRQ4" }, \
+ { x, 0x8f, 0x05, M_EQ, "IRQ5" }, \
+ { x, 0x8f, 0x06, M_EQ, "IRQ6" }, \
+ { x, 0x8f, 0x07, M_EQ, "IRQ7" }, \
+ { x, 0x8f, 0x09, M_EQ, "IRQ9" }, \
+ { x, 0x8f, 0x0a, M_EQ, "IRQ10" }, \
+ { x, 0x8f, 0x0b, M_EQ, "IRQ11" }, \
+ { x, 0x8f, 0x0c, M_EQ, "IRQ12" }, \
+ { x, 0x8f, 0x0e, M_EQ, "IRQ14" }, \
+ { x, 0x8f, 0x0f, M_EQ, "IRQ15" }
+
+ /* Interrupt routing */
+ PIRQ(0x60, "A"),
+ PIRQ(0x61, ", B"),
+ PIRQ(0x62, ", C"),
+ PIRQ(0x63, ", D"),
+ PIRQ(0x70, "\n\t\tMB0"),
+ PIRQ(0x71, ", MB1"),
+
+ { 0x00, 0x00, 0x00, M_TR, "\n" },
+
+ #undef PIRQ
+
+ /* XXX - do DMA routing, too? */
+ { 0 }
+ };
+
#if 0 /* xxx not used */
static const struct condmsg conf82371fb2[] =
{
***************
*** 615,620 ****
--- 789,800 ----
break;
case 0x122e8086:
writeconfig (config_id, conf82371fb);
+ break;
+ case 0x12508086:
+ writeconfig (config_id, conf82439hx);
+ break;
+ case 0x70008086:
+ writeconfig (config_id, conf82371sb);
break;
#if 0
case 0x00011011: /* DEC 21050 */
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