Date: Thu, 2 Oct 1997 10:56:31 -0400 (EDT) From: Garrett Wollman <wollman@khavrinen.lcs.mit.edu> To: Luigi Rizzo <luigi@labinfo.iet.unipi.it> Cc: wollman@khavrinen.lcs.mit.edu (Garrett Wollman), ache@nagual.pp.ru, current@FreeBSD.ORG Subject: Re: Which PCI Ethernet card is best for FreeBSD-current? Message-ID: <199710021456.KAA22895@khavrinen.lcs.mit.edu> In-Reply-To: <199710021223.NAA12138@labinfo.iet.unipi.it> References: <199710021304.JAA22567@khavrinen.lcs.mit.edu> <199710021223.NAA12138@labinfo.iet.unipi.it>
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<<On Thu, 2 Oct 1997 13:23:52 +0100 (MET), Luigi Rizzo <luigi@labinfo.iet.unipi.it> said: > Secondly the 2114x is used by many many vendors so you can find > these cards very cheap. Well, the Intel chip is pretty cheap, and in our tests performed better (had a lower DMA overhead) than the DEC chip. The trades are advertising a retail price of $65 each for the Intels (in quantity 5), and I know I can get a discount off of that. What's more, a lot of motherboards are starting to come with built in Fast Ethernet, and many of those (including all of the Intel-OEMed motherboards) have the 82557 chip on them. We have indeed had some trouble getting the actual documentation out of Intel; they seem to be reluctant to give out documents for this whizzo updateable microcode feature, but we don't much care about that (although it might be nice if we could program the DMA engine to speak mbuf directly). The overall programming model for this thing is just like every other Intel Ethernet chip ever made; a colleague here was able to implement the multicast filtering by almost directly copying the code out of the `ie' (82586/82596) driver. DEC chips have the bug that the Ethernet header has to be aligned on a longword boundary, which means that the protocol header---i.e., the part that actually matters---is guaranteed unaligned, thus necessitating an expensive copy operation or expensive unaligned accesses, depending on the CPU architecture. For someone building a router-type box, the standard designs involving either one is really inappropriate. What we would have liked (I no longer work on that project) would be a board with several NIC chips, a PCI-to-PCI bridge, and (most importantly) a good chunk of memory, on the order of a megabyte. We were easily able to DMA-starve the systems we were using for testing at that time (with slow Orion chipsets) using the workstation-type cards, since all of the traffic had to transit the (only) PCI bus twice. With a shared-memory design, the NIC and the CPU no longer have to compete for bus bandwith, and in a single-copy network implementation this is a big win. (It probably would also be helpful for SMP.) -GAWollman -- Garrett A. Wollman | O Siem / We are all family / O Siem / We're all the same wollman@lcs.mit.edu | O Siem / The fires of freedom Opinions not those of| Dance in the burning flame MIT, LCS, CRS, or NSA| - Susan Aglukark and Chad Irschick
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