From owner-freebsd-usb@FreeBSD.ORG Tue Dec 18 11:17:36 2012 Return-Path: Delivered-To: freebsd-usb@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 6475A145; Tue, 18 Dec 2012 11:17:36 +0000 (UTC) (envelope-from andrew@fubar.geek.nz) Received: from smtp3.clear.net.nz (smtp3.clear.net.nz [203.97.33.64]) by mx1.freebsd.org (Postfix) with ESMTP id 20CF38FC14; Tue, 18 Dec 2012 11:17:34 +0000 (UTC) Received: from mxin3-orange.clear.net.nz (lb2-srcnat.clear.net.nz [203.97.32.237]) by smtp3.clear.net.nz (CLEAR Net Mail) with ESMTP id <0MF800AEP404MS00@smtp3.clear.net.nz>; Wed, 19 Dec 2012 00:02:28 +1300 (NZDT) Received: from 202-0-48-19.paradise.net.nz (HELO localhost) ([202.0.48.19]) by smtpin32.paradise.net.nz with ESMTP; Wed, 19 Dec 2012 00:02:27 +1300 Date: Wed, 19 Dec 2012 00:02:13 +1300 From: Andrew Turner Subject: Re: EHCI on armv6 with Write-Back caches In-reply-to: <201212180922.22217.hselasky@c2i.net> To: Hans Petter Selasky Message-id: <20121219000213.269b1371@fubar.geek.nz> MIME-version: 1.0 X-Mailer: Claws Mail 3.8.0 (GTK+ 2.24.6; i386-portbld-freebsd8.1) Content-type: text/plain; charset=US-ASCII Content-transfer-encoding: 7bit X-Pirate: Arrrr References: <20121218204931.5322922d@fubar.geek.nz> <201212180922.22217.hselasky@c2i.net> Cc: Oleksandr Tymoshenko , freebsd-usb@freebsd.org X-BeenThere: freebsd-usb@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: FreeBSD support for USB List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Dec 2012 11:17:36 -0000 On Tue, 18 Dec 2012 09:22:22 +0100 Hans Petter Selasky wrote: > On Tuesday 18 December 2012 08:49:31 Andrew Turner wrote: > > Hello, > > > > Oleksandr and myself have been looking into why when we enable the > > write-back cache on the PandaBoard there are kernel panics with > > USB. We have tracked it down to an issue appending the ehci_qh_t to > > the list at the end of ehci_setup_standard_chain(). > > > > I have a patch at [1] that allows me to run sha256 on a 40MB file > > over NSF using the built in smsc USB ethernet chip. The problem is > > I have had to place a call to DELAY before EHCI_APPEND_QH. This is > > obviously not the correct solution. > > > > Is anyone able to help me narrow down what is missing? It appears > > to be a missing cache invalidate or flush somewhere but I haven't > > been able to track down what cache function the DELAY is working > > around. > > > > Andrew > > > > [1] http://fubar.geek.nz/files/freebsd/ehci_4.diff > > Hi, > > Can you dump the DMA tag belonging to the QH via and check wether it > is mapped coherent or not. Thes QH- and TD- structures should not be > cache mapped. Else cache has not been disabled on those pages. > > qh->page_cache->tag The BUS_DMA_COHERENT flag does nothing on armv6 as we need the cache enabled for atomic operations to work correctly and we would have to disable the cache on the entire page. This is acceptable behaviour from the description of the flag in the busdma man page. Is there a reason the QH and TD structures shouldn't be cache mapped? Andrew