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From: Robert Watson <rwatson@FreeBSD.org>
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Subject: PERFORCE change 211945 for review
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http://p4web.freebsd.org/@@211945?ac=10

Change 211945 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/05/29 18:57:04

	Modify MIPS page table entry (PTE) initialisation so that
	cachability bits are set only once, using is_cacheable_mem()
	to determine what caching properties are required, rather
	than also unconditionally setting PTE_C_CACHE in
	init_pte_prot().  As PTE_C_CACHE | PTE_C_UNCACHED ==
	PTE_C_CACHE, this meant that all userspace memory mappings
	of device memory used caching TLB entries.
	
	This is arguably not quite what we want, even though it is
	consistent with the MIPS pmap design: PTE caching properties
	should be derived from machine-independent page table
	attributes, but this is a substantially more complex change
	as the MIPS pmap doesn't yet known about attributes.
	
	This may fix cacheability issues seen in memory mappings of
	MTL and DE4 device memory on CHERI MIPS.

Affected files ...

.. //depot/projects/ctsrd/beribsd/src/sys/mips/mips/pmap.c#2 edit

Differences ...

==== //depot/projects/ctsrd/beribsd/src/sys/mips/mips/pmap.c#2 (text+ko) ====

@@ -3144,16 +3144,16 @@
 	pt_entry_t rw;
 
 	if (!(prot & VM_PROT_WRITE))
-		rw =  PTE_V | PTE_RO | PTE_C_CACHE;
+		rw =  PTE_V | PTE_RO;
 	else if ((m->oflags & VPO_UNMANAGED) == 0) {
 		if ((m->md.pv_flags & PV_TABLE_MOD) != 0)
-			rw =  PTE_V | PTE_D | PTE_C_CACHE;
+			rw =  PTE_V | PTE_D;
 		else
-			rw = PTE_V | PTE_C_CACHE;
+			rw = PTE_V;
 		vm_page_aflag_set(m, PGA_WRITEABLE);
 	} else
 		/* Needn't emulate a modified bit for unmanaged pages. */
-		rw =  PTE_V | PTE_D | PTE_C_CACHE;
+		rw =  PTE_V | PTE_D;
 	return (rw);
 }