Date: Sat, 18 Nov 2000 22:05:01 -0700 From: "Justin T. Gibbs" <gibbs@scsiguy.com> To: jon@FreeBSD.org, imp@FreeBSD.org Cc: current@FreeBSD.org Subject: Cardbus fixes Message-ID: <200011190505.eAJ552428239@aslan.scsiguy.com>
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While working on getting the APA-1480 to work under FreeBSD's new
cardbus support, I ran into several issues.
1) When mucking with mapping registers, it is best to *not* have
io or memory space access enabled. This patch defers the setting
of these bits until after all of the mapping registers are probed.
It might be even better to defer this until a particular mapping
is activated and to disable that type of access when a new
register is activated.
2) The PCI spec is very explicit about how mapping registers and
the expansion ROM mapping register should be probed. This patch
makes cardbus_add_map() follow the spec.
3) The PCI spec allows a device to use the same address decoder for
expansion ROM access as is used for memory mapped register access.
This patch carefully enables and disables ROM access along with
resource (de)activiation.
4) The cardbus CIS code treats the CIS_PTR as a mapping register if
it is mentioned in the CIS. I don't have a spec handy to understand
why the CIS_PTR is mentioned in the CIS, but allocating a memory range
for it is certainly bogus. My patch ignores bar #6 to prevent the
mapping.
5) The CIS code allocated duplicate resources to those already found
by cardbus_add_resources(). The fix is to pass in the bar computed
from the CIS instead of the particular resource ID for that bar,
so bus_generic_alloc_resource succeeds in finding the old resource.
It seems somewhat strange that we have to have two methods for
finding and activating the mapping registers. Isn't one method
sufficient?
6) cardbus_read_exrom_cis() failed to advance correctly to higer rom
images. To effect the fix, the cis_ptr value must be provided to
the different CIS reading methods, unaltered.
7) The CIS code seems to use the wrong bit to determine rather a particular
register mapping is for I/O or memory space. From looking at the
two cards I have, it seems TPL_BAR_REG_AS should be 0x10 instead
of 0x08. Otherwise, all registers that should be I/O mapped gain
a second mapping in memory space.
8) The cardbus bridge code leaves memory space prefetching enabled.
Prefetching is only allowed if the target device indicates (through
its mapping register) that prefetching is allowable. My patch
simply disables prefetching and includes code to detect this capability
and pass an RF flag to enable it, but nothing more.
9) The pccbb code was impoperly handling the I/O and mem range limit
registers. The limit register indicates the highest valid address
in the window, not the first invalid address outside the window.
One last thing that is started here is an attempt to rely more heavily
on PCI register definitions and eventually functions, to get things
done. The cardbus code duplicates a lot of functionality that is
already available in the pci code (mapping register size/type detection).
One other thing that struck me while I was looking at this was that
the resource manager should be providing the "resource pooling"
that pccbb_cardbus_auto_open() emulates. Although the cardbus
bridges we support only provide 4K granularity for memory mapped
windows, things like external rom access often can be mapped on
2K boundaries. This could allow the resource manager to allocate
a range that doesn't appear to overlap with another allocation but
does due to the bridges constraints. I might look into adding the
concept of hierarchical resource pools to the resource manager so
that, for example, the cardbus bridges pool will always grow in
4K increments from its parent resource pool. The parent would then
grow according to its own requirements, etc.
--
Justin
Index: dev/cardbus/cardbus.c
===================================================================
RCS file: /usr/cvs/src/sys/dev/cardbus/cardbus.c,v
retrieving revision 1.2
diff -c -r1.2 cardbus.c
*** dev/cardbus/cardbus.c 2000/10/18 03:21:48 1.2
--- dev/cardbus/cardbus.c 2000/11/19 01:41:58
***************
*** 114,121 ****
int rid, u_long start, u_long count);
static int cardbus_get_resource_method(device_t dev, device_t child, int type,
int rid, u_long *startp, u_long *countp);
! static void cardbus_add_map(device_t bdev, device_t dev,
! pcicfgregs *cfg, int reg);
static void cardbus_add_resources(device_t dev, pcicfgregs* cfg);
static void cardbus_release_all_resources(device_t dev,
struct resource_list *rl);
--- 114,121 ----
int rid, u_long start, u_long count);
static int cardbus_get_resource_method(device_t dev, device_t child, int type,
int rid, u_long *startp, u_long *countp);
! static int cardbus_add_map(device_t bdev, device_t dev,
! pcicfgregs *cfg, int reg);
static void cardbus_add_resources(device_t dev, pcicfgregs* cfg);
static void cardbus_release_all_resources(device_t dev,
struct resource_list *rl);
***************
*** 162,172 ****
static void
device_setup_regs(device_t bdev, int b, int s, int f, pcicfgregs *cfg)
{
- PCIB_WRITE_CONFIG(bdev, b, s, f, PCIR_COMMAND,
- PCIB_READ_CONFIG(bdev, b, s, f, PCIR_COMMAND, 2) |
- PCIM_CMD_MEMEN|PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN,
- 2);
-
PCIB_WRITE_CONFIG(bdev, b, s, f, PCIR_INTLINE,
pci_get_irq(device_get_parent(bdev)), 1);
cfg->intline = PCIB_READ_CONFIG(bdev, b, s, f, PCIR_INTLINE, 1);
--- 162,167 ----
***************
*** 537,543 ****
struct cardbus_devinfo *dinfo = device_get_ivars(child);
struct resource_list *rl = &dinfo->resources;
resource_list_add(rl, type, rid, start, start + count - 1, count);
- if (rid == CARDBUS_ROM_REG) start |= 1;
if (device_get_parent(child) == dev)
pci_write_config(child, rid, start, 4);
return 0;
--- 532,537 ----
***************
*** 607,630 ****
BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
}
! static void
cardbus_add_map(device_t cbdev, device_t dev, pcicfgregs *cfg, int reg)
{
struct cardbus_devinfo *dinfo = device_get_ivars(dev);
struct resource_list *rl = &dinfo->resources;
struct resource_list_entry *rle;
device_t bdev = device_get_parent(cbdev);
! u_int32_t size;
! u_int32_t testval;
int type;
! struct resource *res;
PCIB_WRITE_CONFIG(bdev, cfg->bus, cfg->slot, cfg->func,
! reg, 0xfffffff0, 4);
testval = PCIB_READ_CONFIG(bdev, cfg->bus, cfg->slot, cfg->func,
reg, 4);
! if (testval == 0xfffffff0 || testval == 0) return;
if ((testval&1) == 0)
type = SYS_RES_MEMORY;
--- 601,630 ----
BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
}
! static int
cardbus_add_map(device_t cbdev, device_t dev, pcicfgregs *cfg, int reg)
{
struct cardbus_devinfo *dinfo = device_get_ivars(dev);
struct resource_list *rl = &dinfo->resources;
struct resource_list_entry *rle;
+ struct resource *res;
device_t bdev = device_get_parent(cbdev);
! uint32_t size;
! uint32_t testval;
int type;
! int prefetch;
+ if (reg == PCIR_ROM)
+ testval = PCIM_ROM_ADDR;
+ else
+ testval = ~0;
PCIB_WRITE_CONFIG(bdev, cfg->bus, cfg->slot, cfg->func,
! reg, testval, 4);
testval = PCIB_READ_CONFIG(bdev, cfg->bus, cfg->slot, cfg->func,
reg, 4);
! if (testval == ~0 || testval == 0)
! return (0);
if ((testval&1) == 0)
type = SYS_RES_MEMORY;
***************
*** 632,638 ****
--- 632,640 ----
type = SYS_RES_IOPORT;
size = CARDBUS_MAPREG_MEM_SIZE(testval);
+ prefetch = CARDBUS_MAPREG_MEM_PREFETCH(testval);
res = bus_generic_alloc_resource(cbdev, dev, type, ®, 0, ~0, size,
+ (prefetch ? RF_PREFETCH : 0) |
rman_make_alignment_flags(size));
if (res) {
u_int32_t start = rman_get_start(res);
***************
*** 642,672 ****
rle->res = res;
} else {
device_printf(dev, "Unable to add map %02x\n", reg);
}
}
static void
cardbus_add_resources(device_t dev, pcicfgregs* cfg)
{
device_t cbdev = device_get_parent(dev);
struct cardbus_devinfo *dinfo = device_get_ivars(dev);
struct resource_list *rl = &dinfo->resources;
struct cardbus_quirk *q;
struct resource_list_entry *rle;
struct resource *res;
int i;
for (i = 0; i < cfg->nummaps; i++) {
! cardbus_add_map(cbdev, dev, cfg, PCIR_MAPS + i*4);
}
! cardbus_add_map(cbdev, dev, cfg, CARDBUS_ROM_REG);
for (q = &cardbus_quirks[0]; q->devid; q++) {
if (q->devid == ((cfg->device << 16) | cfg->vendor)
! && q->type == CARDBUS_QUIRK_MAP_REG)
! cardbus_add_map(cbdev, dev, cfg, q->arg1);
}
res = bus_generic_alloc_resource(cbdev, dev, SYS_RES_IRQ,
0, 0, ~0, 1, RF_SHAREABLE);
--- 644,695 ----
rle->res = res;
} else {
device_printf(dev, "Unable to add map %02x\n", reg);
+ type = 0;
}
+ return (type);
}
static void
cardbus_add_resources(device_t dev, pcicfgregs* cfg)
{
device_t cbdev = device_get_parent(dev);
+ device_t bdev = device_get_parent(cbdev);
struct cardbus_devinfo *dinfo = device_get_ivars(dev);
struct resource_list *rl = &dinfo->resources;
struct cardbus_quirk *q;
struct resource_list_entry *rle;
struct resource *res;
+ u_int command;
+ int type;
+ int types;
int i;
+ types = 0;
for (i = 0; i < cfg->nummaps; i++) {
! type = cardbus_add_map(cbdev, dev, cfg, PCIR_MAPS + i*4);
! types |= 0x1 << type;
}
! type = cardbus_add_map(cbdev, dev, cfg, PCIR_ROM);
! types |= 0x1 << type;
for (q = &cardbus_quirks[0]; q->devid; q++) {
if (q->devid == ((cfg->device << 16) | cfg->vendor)
! && q->type == CARDBUS_QUIRK_MAP_REG) {
! type = cardbus_add_map(cbdev, dev, cfg, q->arg1);
! types |= 0x1 << type;
! }
}
+ command = PCIB_READ_CONFIG(bdev, cfg->bus, cfg->slot,
+ cfg->func, PCIR_COMMAND, 2);
+ if ((types & (0x1 << SYS_RES_MEMORY)) != 0)
+ command |= PCIM_CMD_MEMEN;
+ if ((types & (0x1 << SYS_RES_IOPORT)) != 0)
+ command |= PCIM_CMD_PORTEN;
+ command |= PCIM_CMD_BUSMASTEREN;
+ PCIB_WRITE_CONFIG(bdev, cfg->bus, cfg->slot, cfg->func,
+ PCIR_COMMAND, command, 2);
+
res = bus_generic_alloc_resource(cbdev, dev, SYS_RES_IRQ,
0, 0, ~0, 1, RF_SHAREABLE);
***************
*** 693,702 ****
}
}
! static struct
! resource* cardbus_alloc_resource(device_t self, device_t child, int type,
! int* rid, u_long start, u_long end,
! u_long count, u_int flags)
{
struct cardbus_devinfo *dinfo = device_get_ivars(child);
struct resource_list *rl = &dinfo->resources;
--- 716,725 ----
}
}
! static struct resource*
! cardbus_alloc_resource(device_t self, device_t child, int type,
! int* rid, u_long start, u_long end,
! u_long count, u_int flags)
{
struct cardbus_devinfo *dinfo = device_get_ivars(child);
struct resource_list *rl = &dinfo->resources;
***************
*** 706,716 ****
if (device_get_parent(child) == self || child == self)
rle = resource_list_find(rl, type, *rid);
if (rle) {
! if (flags & RF_ACTIVE)
if (bus_activate_resource(child, type, *rid,
rle->res)) {
return NULL;
}
return rle->res; /* XXX: check if range within start/end */
} else {
res = bus_generic_alloc_resource(self, child, type, rid,
--- 729,747 ----
if (device_get_parent(child) == self || child == self)
rle = resource_list_find(rl, type, *rid);
if (rle) {
! if (flags & RF_ACTIVE) {
if (bus_activate_resource(child, type, *rid,
rle->res)) {
return NULL;
}
+ if (*rid == PCIR_ROM) {
+ uint32_t rom_reg;
+
+ rom_reg = pci_read_config(child, *rid, 4);
+ rom_reg |= PCIM_ROM_ENABLE;
+ pci_write_config(child, *rid, rom_reg, 4);
+ }
+ }
return rle->res; /* XXX: check if range within start/end */
} else {
res = bus_generic_alloc_resource(self, child, type, rid,
***************
*** 734,739 ****
--- 765,783 ----
cardbus_release_resource(device_t dev, device_t child, int type, int rid,
struct resource *r)
{
+ /*
+ * According to the PCI 2.2 spec, devices may share an address
+ * decoder between memory mapped ROM access and memory
+ * mapped register access. To be safe, disable ROM access
+ * whenever it is released.
+ */
+ if (rid == PCIR_ROM) {
+ uint32_t rom_reg;
+
+ rom_reg = pci_read_config(child, rid, 4);
+ rom_reg &= ~PCIM_ROM_ENABLE;
+ pci_write_config(child, rid, rom_reg, 4);
+ }
return bus_deactivate_resource(child, type, rid, r);
}
Index: dev/cardbus/cardbus_cis.c
===================================================================
RCS file: /usr/cvs/src/sys/dev/cardbus/cardbus_cis.c,v
retrieving revision 1.1
diff -c -r1.1 cardbus_cis.c
*** dev/cardbus/cardbus_cis.c 2000/10/18 03:21:48 1.1
--- dev/cardbus/cardbus_cis.c 2000/11/19 00:04:55
***************
*** 44,49 ****
--- 44,50 ----
#include <sys/rman.h>
#include <pci/pcivar.h>
+ #include <pci/pcireg.h>
#include <dev/cardbus/cardbusreg.h>
#include <dev/cardbus/cardbus_cis.h>
***************
*** 258,263 ****
--- 259,266 ----
type = SYS_RES_MEMORY;
}
bar = (reg & TPL_BAR_REG_ASI_MASK) - 1;
+ if (bar == 6)
+ return EINVAL;
if (bar < 0 || bar > 6) {
device_printf(dev, "Invalid BAR number: %02x(%02x)\n",
reg, bar);
***************
*** 266,278 ****
bar = CARDBUS_BASE0_REG + bar * 4;
DEVPRINTF((dev, "Opening BAR: type=%s, bar=%02x, len=%04x\n",
(type==SYS_RES_MEMORY)?"MEM":"IO", bar, len));
! res = bus_generic_alloc_resource(child, child, type, ®, 0,
~0, len, rman_make_alignment_flags(len) | RF_ACTIVE);
if (res == NULL) {
device_printf(dev, "Cannot allocate BAR %02x\n", reg);
} else {
start = rman_get_start(res);
- if (reg == CARDBUS_ROM_REG) start |= 1;
pci_write_config(child, reg, start, 4);
}
}
--- 269,280 ----
bar = CARDBUS_BASE0_REG + bar * 4;
DEVPRINTF((dev, "Opening BAR: type=%s, bar=%02x, len=%04x\n",
(type==SYS_RES_MEMORY)?"MEM":"IO", bar, len));
! res = bus_generic_alloc_resource(child, child, type, &bar, 0,
~0, len, rman_make_alignment_flags(len) | RF_ACTIVE);
if (res == NULL) {
device_printf(dev, "Cannot allocate BAR %02x\n", reg);
} else {
start = rman_get_start(res);
pci_write_config(child, reg, start, 4);
}
}
***************
*** 290,297 ****
return -1;
}
! static int decode_tuples(device_t dev, device_t child,
! u_int8_t *tuples, int len)
{
int ret = 0;
if (CISTPL_LINKTARGET != *tuples) {
--- 292,299 ----
return -1;
}
! static int
! decode_tuples(device_t dev, device_t child, u_int8_t *tuples, int len)
{
int ret = 0;
if (CISTPL_LINKTARGET != *tuples) {
***************
*** 332,338 ****
#define READROM(rom, type, offset) \
(*((u_int ## type ##_t *)(((unsigned char*)rom) + offset)))
- u_int32_t addr = 0; /* offset of current rom image */
int romnum = 0;
unsigned char *data;
u_int32_t imagesize;
--- 334,339 ----
***************
*** 351,362 ****
data = image + READROM(image, 16, CARDBUS_EXROM_DATA_PTR);
imagesize = READROM(data, 16, CARDBUS_EXROM_DATA_IMAGE_LENGTH);
! if(imagesize == 0)
/*
* XXX some ROMs seem to have this as zero,
* can we assume this means 1 block?
*/
imagesize = 1;
imagesize <<= 9;
if (imagenum == romnum) {
--- 352,364 ----
data = image + READROM(image, 16, CARDBUS_EXROM_DATA_PTR);
imagesize = READROM(data, 16, CARDBUS_EXROM_DATA_IMAGE_LENGTH);
! if (imagesize == 0) {
/*
* XXX some ROMs seem to have this as zero,
* can we assume this means 1 block?
*/
imagesize = 1;
+ }
imagesize <<= 9;
if (imagenum == romnum) {
***************
*** 365,371 ****
return 0;
}
! addr += imagesize;
romnum++;
} while ((READROM(data, 8, CARDBUS_EXROM_DATA_INDICATOR) & 0x80) == 0);
device_printf(dev, "Cannot read CIS: Not enough images of rom\n");
--- 367,373 ----
return 0;
}
! image += imagesize;
romnum++;
} while ((READROM(data, 8, CARDBUS_EXROM_DATA_INDICATOR) & 0x80) == 0);
device_printf(dev, "Cannot read CIS: Not enough images of rom\n");
***************
*** 380,386 ****
int i, j;
DEVPRINTF((dev, "reading CIS data from configuration space\n"));
! for (i = cis_ptr, j = 0; i < len; i += 4) {
u_int32_t e = pci_read_config(child, i, 4);
tuples[j] = 0xff & e;
e >>= 8;
--- 382,388 ----
int i, j;
DEVPRINTF((dev, "reading CIS data from configuration space\n"));
! for (i = cis_ptr & CARDBUS_CIS_ADDRMASK, j = 0; i < len; i += 4) {
u_int32_t e = pci_read_config(child, i, 4);
tuples[j] = 0xff & e;
e >>= 8;
***************
*** 402,409 ****
int rid;
int ret;
! if(space == CARDBUS_CIS_ASI_ROM) {
! rid = CARDBUS_ROM_REG;
DEVPRINTF((dev, "reading CIS data from ROM\n"));
} else {
rid = CARDBUS_BASE0_REG + (space - 1) * 4;
--- 404,411 ----
int rid;
int ret;
! if (space == CARDBUS_CIS_ASI_ROM) {
! rid = PCIR_ROM;
DEVPRINTF((dev, "reading CIS data from ROM\n"));
} else {
rid = CARDBUS_BASE0_REG + (space - 1) * 4;
***************
*** 416,428 ****
return ENOMEM;
}
! if(space == CARDBUS_CIS_ASI_ROM) {
int s;
s = splhigh();
ret = cardbus_read_exrom_cis(dev, mem, cis_ptr, tuples, len);
splx(s);
} else {
/* XXX byte order? */
memcpy(tuples, (unsigned char*)rman_get_virtual(mem)+cis_ptr,
len);
ret = 0;
--- 418,431 ----
return ENOMEM;
}
! if (space == CARDBUS_CIS_ASI_ROM) {
int s;
s = splhigh();
ret = cardbus_read_exrom_cis(dev, mem, cis_ptr, tuples, len);
splx(s);
} else {
/* XXX byte order? */
+ cis_ptr &= CARDBUS_CIS_ADDRMASK;
memcpy(tuples, (unsigned char*)rman_get_virtual(mem)+cis_ptr,
len);
ret = 0;
***************
*** 437,443 ****
u_int32_t cis_ptr = pci_read_config(child, CARDBUS_CIS_REG, 4);
int cardbus_space = cis_ptr & CARDBUS_CIS_ASIMASK;
int ret = 0;
- cis_ptr = cis_ptr & CARDBUS_CIS_ADDRMASK;
switch(cardbus_space) {
case CARDBUS_CIS_ASI_TUPLE:
--- 440,445 ----
Index: dev/cardbus/cardbus_cis.h
===================================================================
RCS file: /usr/cvs/src/sys/dev/cardbus/cardbus_cis.h,v
retrieving revision 1.1
diff -c -r1.1 cardbus_cis.h
*** dev/cardbus/cardbus_cis.h 2000/10/18 03:21:48 1.1
--- dev/cardbus/cardbus_cis.h 2000/11/17 18:55:01
***************
*** 79,85 ****
/* BAR */
#define TPL_BAR_REG_ASI_MASK 0x07
! #define TPL_BAR_REG_AS 0x08
/* CISTPL_FUNC */
#define TPL_FUNC_MF 0 /* multi function tuple */
--- 79,85 ----
/* BAR */
#define TPL_BAR_REG_ASI_MASK 0x07
! #define TPL_BAR_REG_AS 0x10
/* CISTPL_FUNC */
#define TPL_FUNC_MF 0 /* multi function tuple */
Index: dev/cardbus/cardbusreg.h
===================================================================
RCS file: /usr/cvs/src/sys/dev/cardbus/cardbusreg.h,v
retrieving revision 1.2
diff -c -r1.2 cardbusreg.h
*** dev/cardbus/cardbusreg.h 2000/10/18 03:21:48 1.2
--- dev/cardbus/cardbusreg.h 2000/11/18 03:20:17
***************
*** 55,61 ****
# define CARDBUS_CIS_ASI_BAR4 0x05
# define CARDBUS_CIS_ASI_BAR5 0x06
# define CARDBUS_CIS_ASI_ROM 0x07
- #define CARDBUS_ROM_REG 0x30
/* EXROM offsets for reading CIS */
#define CARDBUS_EXROM_SIGNATURE 0x00
--- 55,60 ----
***************
*** 85,87 ****
--- 84,88 ----
((mr) & CARDBUS_MAPREG_MEM_ADDR_MASK)
#define CARDBUS_MAPREG_MEM_SIZE(mr) \
(CARDBUS_MAPREG_MEM_ADDR(mr) & -CARDBUS_MAPREG_MEM_ADDR(mr))
+ #define CARDBUS_MAPREG_MEM_PREFETCH(mr) \
+ ((mr) & PCIM_MAP_PREFETCHABLE)
Index: dev/pccbb/pccbb.c
===================================================================
RCS file: /usr/cvs/src/sys/dev/pccbb/pccbb.c,v
retrieving revision 1.5
diff -c -r1.5 pccbb.c
*** dev/pccbb/pccbb.c 2000/10/22 04:37:57 1.5
--- dev/pccbb/pccbb.c 2000/11/19 03:42:52
***************
*** 317,323 ****
/* Use PCI interrupt for interrupt routing */
PCI_MASK2_CONFIG(sc->sc_dev, PCCBBR_BRIDGECTRL,
& ~(PCCBBM_BRIDGECTRL_MASTER_ABORT |
! PCCBBM_BRIDGECTRL_INTR_IREQ_EN),
| PCCBBM_BRIDGECTRL_WRITE_POST_EN,
2);
--- 317,325 ----
/* Use PCI interrupt for interrupt routing */
PCI_MASK2_CONFIG(sc->sc_dev, PCCBBR_BRIDGECTRL,
& ~(PCCBBM_BRIDGECTRL_MASTER_ABORT |
! PCCBBM_BRIDGECTRL_INTR_IREQ_EN |
! PCCBBM_BRIDGECTRL_PREFETCH_0 |
! PCCBBM_BRIDGECTRL_PREFETCH_1),
| PCCBBM_BRIDGECTRL_WRITE_POST_EN,
2);
***************
*** 910,917 ****
SLIST_FOREACH(rle, &sc->rl, entries) {
if (rle->type != type)
! ;
! else if (starts[0] == 0xffffffff) {
starts[0] = rle->start;
ends[0] = rle->end;
rle->win = 0;
--- 912,919 ----
SLIST_FOREACH(rle, &sc->rl, entries) {
if (rle->type != type)
! continue;
! if (starts[0] == 0xffffffff) {
starts[0] = rle->start;
ends[0] = rle->end;
rle->win = 0;
***************
*** 969,978 ****
starts[0] -= starts[0] % align;
if (starts[1] != 0xffffffff)
starts[1] -= starts[1] % align;
! if (ends[0] % align != 0)
ends[0] += align - ends[0]%align;
! if (ends[1] % align != 0)
ends[1] += align - ends[1]%align;
if (type == SYS_RES_MEMORY) {
pccbb_cardbus_mem_open(sc->sc_dev, 0, starts[0], ends[0]);
--- 971,984 ----
starts[0] -= starts[0] % align;
if (starts[1] != 0xffffffff)
starts[1] -= starts[1] % align;
! if (ends[0] % align != 0) {
ends[0] += align - ends[0]%align;
! ends[0]--;
! }
! if (ends[1] % align != 0) {
ends[1] += align - ends[1]%align;
+ ends[1]--;
+ }
if (type == SYS_RES_MEMORY) {
pccbb_cardbus_mem_open(sc->sc_dev, 0, starts[0], ends[0]);
Index: pci/if_dc.c
===================================================================
RCS file: /usr/cvs/src/sys/pci/if_dc.c,v
retrieving revision 1.38
diff -c -r1.38 if_dc.c
*** pci/if_dc.c 2000/11/14 19:35:22 1.38
--- pci/if_dc.c 2000/11/17 19:33:11
***************
*** 119,125 ****
#include <pci/pcireg.h>
#include <pci/pcivar.h>
- #define DC_USEIOSPACE
#ifdef __alpha__
#define SRM_MEDIA
#endif
--- 119,124 ----
Index: pci/if_fxp.c
===================================================================
RCS file: /usr/cvs/src/sys/pci/if_fxp.c,v
retrieving revision 1.99
diff -c -r1.99 if_fxp.c
*** pci/if_fxp.c 2000/10/22 06:41:46 1.99
--- pci/if_fxp.c 2000/11/19 01:41:01
***************
*** 491,497 ****
for (i=0; i<5; i++)
sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i*4, 4);
! sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
--- 491,497 ----
for (i=0; i<5; i++)
sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i*4, 4);
! sc->saved_biosaddr = pci_read_config(dev, PCIR_ROM, 4);
sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
***************
*** 521,527 ****
/* better way to do this? */
for (i=0; i<5; i++)
pci_write_config(dev, PCIR_MAPS + i*4, sc->saved_maps[i], 4);
! pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
--- 521,527 ----
/* better way to do this? */
for (i=0; i<5; i++)
pci_write_config(dev, PCIR_MAPS + i*4, sc->saved_maps[i], 4);
! pci_write_config(dev, PCIR_ROM, sc->saved_biosaddr, 4);
pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
Index: pci/pcireg.h
===================================================================
RCS file: /usr/cvs/src/sys/pci/pcireg.h,v
retrieving revision 1.27
diff -c -r1.27 pcireg.h
*** pci/pcireg.h 2000/10/02 00:41:43 1.27
--- pci/pcireg.h 2000/11/18 03:19:43
***************
*** 69,79 ****
/* config registers for header type 0 devices */
#define PCIR_MAPS 0x10
#define PCIR_CARDBUSCIS 0x28
#define PCIR_SUBVEND_0 0x2c
#define PCIR_SUBDEV_0 0x2e
! #define PCIR_BIOS 0x30
! #define PCIM_BIOS_ENABLE 0x01
#define PCIR_INTLINE 0x3c
#define PCIR_INTPIN 0x3d
#define PCIR_MINGNT 0x3e
--- 69,82 ----
/* config registers for header type 0 devices */
#define PCIR_MAPS 0x10
+ #define PCIM_MAP_PREFETCHABLE 0x08
#define PCIR_CARDBUSCIS 0x28
#define PCIR_SUBVEND_0 0x2c
#define PCIR_SUBDEV_0 0x2e
! #define PCIR_ROM 0x30
! #define PCIM_ROM_ENABLE 0x01
! #define PCIM_ROM_ADDR 0xFFFFF800
! #define PCIR_CAP_PTR 0x34
#define PCIR_INTLINE 0x3c
#define PCIR_INTPIN 0x3d
#define PCIR_MINGNT 0x3e
Index: sys/rman.h
===================================================================
RCS file: /usr/cvs/src/sys/sys/rman.h,v
retrieving revision 1.12
diff -c -r1.12 rman.h
*** sys/rman.h 2000/11/09 15:42:05 1.12
--- sys/rman.h 2000/11/18 03:09:52
***************
*** 42,47 ****
--- 42,48 ----
#define RF_TIMESHARE 0x0008 /* resource permits time-division sharing */
#define RF_WANTED 0x0010 /* somebody is waiting for this resource */
#define RF_FIRSTSHARE 0x0020 /* first in sharing list */
+ #define RF_PREFETCH 0x0040 /* resource allows prefetching */
#define RF_ALIGNMENT_SHIFT 10 /* alignment size bit starts bit 10 */
#define RF_ALIGNMENT_MASK (0x003F << RF_ALIGNMENT_SHIFT)
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