Date: Fri, 28 Jul 95 15:38:04 MDT From: terry@cs.weber.edu (Terry Lambert) To: eyfarris@gdwest.gd.com (Eblan Y Farris) Cc: nik@blueberry.co.uk, questions@freebsd.org Subject: Re: Pentiums and cache problems Message-ID: <9507282138.AA00804@cs.weber.edu> In-Reply-To: <9507281039.AA01849@gdwest.gd.com> from "Eblan Y Farris" at Jul 28, 95 03:39:26 am
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> -------------------Previous EMAIL---------------------- > The other is a larger chip, roughly 1.5in square, with the text > > OPTi > Viper > 82C557 > Tawain 951215TE > > ------------------------------------------------------- > > This is your problem - Not all chipsets are created > equal - and not all motherboards are created equal. This chip does not support cache update or invalidate on non-processor main memory writes, leaving the cache contents incorrect but still in cache. Non-processor main memory writes occur as a result of bus mastering devices getting a bus grant and writing main memory using on board logic rather than involving the system processor. A system which fails in this way can not be claimed to comply with either the EISA or the PCI standards. While cache implementation on PCI is optional (PCI local bus specification, rev 2.0, section 3.8), it is only its implementation on the PCI bus itself which is optional. If the processor has cache on the other side of the PCI bridge (ie: a design wherein the native system bus is not PCI and PCI devices are bridged onto the system bus, then cache coherency is required). PCI r2.0 S3.8 P3: Any PCI target that supports cacheable memory must monitor the PCI cache support pins and respond apropriately. Targets configured to be non-cacheable may ignore SDONE and SB0#, as this may save a little access latency, depending on configuration. PCI r2.0 S2.2.7: A cacheable PCI memory should implement both cache support pins as inputs, to allow it to work with either write-through or write-back caches. If cacheable memory is located on PCI, a bridge connecting a write-back cache to PCI must implement both pins as outputs; a bridge connecting to a write-through cache may only implement one pin as described in Section 3.8. I read this as saying that the target must be configured to be non-cacheable if the option to omit cache support is taken by the manufacturer. Unless a written exception has been granted, claims of compliance are in violation of the manufacturers license agreement and should be brought to the attention of the licensing authorities. For PCI, this is: PCI Special Interest Group M/S HF3-15A 5200 NE Elam Young Parkway Hillsboro, OR 97124-6497 Phone: +1 (503) 696-2000 Fax: +1 (503) 693-0920 Additional PCI notes: Other than the DEC Alpha 21066/21066A and Motorolla PPC bridges (and possibly the new Macs) -- basically all non-Intel hardware other than the Triton chipset -- most PCI implementations do not support bus arbitration signals for more than 2 bus masters; this is a well known limitation for which written exceptions exist. Terry Lambert terry@cs.weber.edu --- Any opinions in this posting are my own and not those of my present or previous employers.
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