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Date:      Thu, 16 Nov 2000 22:07:14 +0100 (CET)
From:      Robert Drehmel <robd@gmx.net>
To:        FreeBSD-gnats-submit@freebsd.org
Subject:   i386/22900: patch: Adds Brand ID support to identcpu.c 
Message-ID:  <200011162107.eAGL7EJ01130@gizmo.quizbot.org>

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>Number:         22900
>Category:       i386
>Synopsis:       patch: Adds Brand ID support to src/sys/i386/i386/identcpu.c
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    freebsd-bugs
>State:          open
>Quarter:        
>Keywords:       
>Date-Required:
>Class:          change-request
>Submitter-Id:   current-users
>Arrival-Date:   Thu Nov 16 13:10:01 PST 2000
>Closed-Date:
>Last-Modified:
>Originator:     Robert Drehmel
>Release:        FreeBSD 5.0-CURRENT i386
>Organization:
>Environment:

	FreeBSD 5.0-CURRENT from about 18:00 CET.

>Description:

	This patch adds some P6 signature checks, written
	according to Intel's AP-485, including Brand ID
	support for Intel model 8 CPU's.
	Additionally, it moves the i486-signature check in
	a better position.
	Unfortunately, I couldn't test it.

>How-To-Repeat:

>Fix:

(Apply in src/sys/i386/i386)

Index: identcpu.c
===================================================================
RCS file: /home/ncvs/src/sys/i386/i386/identcpu.c,v
retrieving revision 1.88
diff -c -r1.88 identcpu.c
*** identcpu.c	2000/10/29 13:56:41	1.88
--- identcpu.c	2000/11/16 20:37:31
***************
*** 88,93 ****
--- 88,100 ----
  SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 
      cpu_model, 0, "Machine model");
  
+ char *intel_bids[] = {
+ 	"?",
+ 	"Celeron (model 8)"
+ 	"Pentium III (model 8)",
+ 	"Pentium III Xeon (model 8)",
+ };
+ 
  static struct cpu_nameclass i386_cpus[] = {
  	{ "Intel 80286",	CPUCLASS_286 },		/* CPU_286   */
  	{ "i386SX",		CPUCLASS_386 },		/* CPU_386SX */
***************
*** 153,158 ****
--- 160,189 ----
  			switch (cpu_id & 0xf00) {
  			case 0x400:
  				strcat(cpu_model, "i486 ");
+ 				switch (cpu_id & 0xf0) {
+ 				case 0x00:
+ 				case 0x10:
+ 					strcat(cpu_model, "DX");
+ 					break;
+ 				case 0x20:
+ 					strcat(cpu_model, "SX");
+ 					break;
+ 				case 0x30:
+ 					strcat(cpu_model, "SX2");
+ 					break;
+ 				case 0x40:
+ 					strcat(cpu_model, "SL");
+ 					break;
+ 				case 0x50:
+ 					strcat(cpu_model, "SX2");
+ 					break;
+ 				case 0x70:
+ 					strcat(cpu_model, "DX2 Write-Back Enhanced");
+ 					break;
+ 				case 0x80:
+ 					strcat(cpu_model, "DX4");
+ 					break;
+ 				}
  				break;
  			case 0x500:
  			        /* Check the particular flavor of 586 */
***************
*** 202,218 ****
  				        strcat(cpu_model, "Pentium Pro");
  					break;
  				case 0x30:
  				case 0x50:
  				case 0x60:
! 				        strcat(cpu_model,
! 				"Pentium II/Pentium II Xeon/Celeron");
  					cpu = CPU_PII;
  					break;
  				case 0x70:
  				case 0x80:
  				case 0xa0:
! 				        strcat(cpu_model,
! 					"Pentium III/Pentium III Xeon/Celeron");
  					cpu = CPU_PIII;
  					break;
  				default:
--- 233,262 ----
  				        strcat(cpu_model, "Pentium Pro");
  					break;
  				case 0x30:
+ 					strcat(cpu_model, "Pentium II (model 3)");
+ 					cpu = CPU_PII;
+ 					break;
  				case 0x50:
+ 					/* These (and 0x70) can be differentiated
+ 					 * by looking at the cache descriptors.
+ 					 */
+ 					strcat(cpu_model, "Pentium II/Pentium II Xeon/Celeron (model 5)");
+ 					cpu = CPU_PII;
+ 					break;
  				case 0x60:
! 				        strcat(cpu_model, "Celeron (model 6)");
  					cpu = CPU_PII;
  					break;
  				case 0x70:
+ 					strcat(cpu_model, "Pentium III/Pentium III Xeon/Celeron (model 7)");
+ 					cpu = CPU_PIII;
+ 					break;
  				case 0x80:
+ 					strcat(cpu_model, intel_bids[cpu_bid]);
+ 					cpu = CPU_PIII;
+ 					break;
  				case 0xa0:
! 				        strcat(cpu_model, "Pentium III XEON (model A)");
  					cpu = CPU_PIII;
  					break;
  				default:
***************
*** 228,254 ****
  				strcat(cpu_model, "unknown");
  				break;
  			}
- 
- 			switch (cpu_id & 0xff0) {
- 			case 0x400:
- 				strcat(cpu_model, "DX"); break;
- 			case 0x410:
- 				strcat(cpu_model, "DX"); break;
- 			case 0x420:
- 				strcat(cpu_model, "SX"); break;
- 			case 0x430:
- 				strcat(cpu_model, "DX2"); break;
- 			case 0x440:
- 				strcat(cpu_model, "SL"); break;
- 			case 0x450:
- 				strcat(cpu_model, "SX2"); break;
- 			case 0x470:
- 				strcat(cpu_model, "DX2 Write-Back Enhanced");
- 				break;
- 			case 0x480:
- 				strcat(cpu_model, "DX4"); break;
- 				break;
- 			}
  		}
  	} else if (strcmp(cpu_vendor,"AuthenticAMD") == 0) {
  		/*
--- 272,277 ----
***************
*** 534,539 ****
--- 557,564 ----
  		printf("  Origin = \"%s\"",cpu_vendor);
  	if(cpu_id)
  		printf("  Id = 0x%x", cpu_id);
+ 	if (strcmp(cpu_vendor, "GenuineIntel") == 0 && cpu_id != 0x0)
+ 		printf("  Brand Id = 0x%x", cpu_bid);
  
  	if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  	    strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
Index: locore.s
===================================================================
RCS file: /home/ncvs/src/sys/i386/i386/locore.s,v
retrieving revision 1.138
diff -c -r1.138 locore.s
*** locore.s	2000/09/13 14:08:50	1.138
--- locore.s	2000/11/16 20:37:37
***************
*** 95,105 ****
  
  	.globl	_boothowto,_bootdev
  
! 	.globl	_cpu,_cpu_vendor,_cpu_id,_bootinfo
  	.globl	_cpu_high, _cpu_feature
  
  _cpu:		.long	0			/* are we 386, 386sx, or 486 */
  _cpu_id:	.long	0			/* stepping ID */
  _cpu_high:	.long	0			/* highest arg to CPUID */
  _cpu_feature:	.long	0			/* features */
  _cpu_vendor:	.space	20			/* CPU origin code */
--- 95,106 ----
  
  	.globl	_boothowto,_bootdev
  
! 	.globl	_cpu,_cpu_vendor,_cpu_id,_cpu_bid,_bootinfo
  	.globl	_cpu_high, _cpu_feature
  
  _cpu:		.long	0			/* are we 386, 386sx, or 486 */
  _cpu_id:	.long	0			/* stepping ID */
+ _cpu_bid:	.long	0			/* branch ID */
  _cpu_high:	.long	0			/* highest arg to CPUID */
  _cpu_feature:	.long	0			/* features */
  _cpu_vendor:	.space	20			/* CPU origin code */
***************
*** 672,677 ****
--- 673,680 ----
  	.byte	0x0f,0xa2			# cpuid 1
  	movl	%eax,R(_cpu_id)			# store cpu_id
  	movl	%edx,R(_cpu_feature)		# store cpu_feature
+ 	andl	$0xff,%ebx			# clear reserved bits
+ 	movl	%ebx,R(_cpu_bid)		# store cpu_bid
  	rorl	$8,%eax				# extract family type
  	andl	$15,%eax
  	cmpl	$5,%eax
Index: ../include/asnames.h
===================================================================
RCS file: /home/ncvs/src/sys/i386/include/asnames.h,v
retrieving revision 1.48
diff -c -r1.48 asnames.h
*** asnames.h	2000/10/06 02:20:13	1.48
--- asnames.h	2000/11/16 20:45:57
***************
*** 194,199 ****
--- 194,200 ----
  #define _cpu_feature			cpu_feature
  #define _cpu_high			cpu_high
  #define _cpu_id				cpu_id
+ #define	_cpu_bid			cpu_bid
  #define _cpu_num_to_apic_id		cpu_num_to_apic_id
  #define _cpu_switch			cpu_switch
  #define _cpu_vendor			cpu_vendor
Index: ../include/md_var.h
===================================================================
RCS file: /home/ncvs/src/sys/i386/include/md_var.h,v
retrieving revision 1.38
diff -c -r1.38 md_var.h
*** md_var.h	2000/10/25 05:19:35	1.38
--- md_var.h	2000/11/16 20:46:02
***************
*** 47,52 ****
--- 47,53 ----
  extern	u_int	cpu_feature;
  extern	u_int	cpu_high;
  extern	u_int	cpu_id;
+ extern	u_int	cpu_bid;
  extern	char	cpu_vendor[];
  extern	u_int	cyrix_did;
  extern	char	kstack[];

>Release-Note:
>Audit-Trail:
>Unformatted:


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