Date: Tue, 21 Mar 1995 21:32:34 -0800 From: David Greenman <davidg@Root.COM> To: "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com> Cc: CVS-commiters@freefall.cdrom.com, cvs-sys@freefall.cdrom.com Subject: Re: cvs commit: src/sys/i386/isa wd.c wdreg.h Message-ID: <199503220532.VAA12851@corbin.Root.COM> In-Reply-To: Your message of "Tue, 21 Mar 95 21:28:48 PST." <199503220528.VAA07316@gndrsh.aac.dev.com>
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>> >> davidg 95/03/21 21:23:03 >> >> Modified: sys/i386/isa wd.c wdreg.h >> Log: >> Fixes and improvements from John Dyson: >> >> Fixed the I/O statistics >> Allow WD1007 type controllers to work >> Support MULTI-BLOCK I/O >> Correct delay to use port 0x84, reading the status register >> might not be a long enough delay. > >Port 0x84 will not cause the 1.25uS delay on some PCI motherboards, >I beleive all Intel Neptune and Triton based boards know that this >is not an ISA address and end up running only a PCI I/O cycle for >it. ...John thinks it's more likely going to work than reading the status register. I suppose that a calibrated delay loop is what is really needed. Making DELAY() accurate below 15us would be the place to do this. -DG
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