From owner-freebsd-stable@FreeBSD.ORG Fri Jul 16 06:46:35 2010 Return-Path: Delivered-To: freebsd-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 9254D106564A; Fri, 16 Jul 2010 06:46:35 +0000 (UTC) (envelope-from olli@lurza.secnetix.de) Received: from lurza.secnetix.de (lurza.secnetix.de [IPv6:2a01:170:102f::2]) by mx1.freebsd.org (Postfix) with ESMTP id 0FE0F8FC08; Fri, 16 Jul 2010 06:46:34 +0000 (UTC) Received: from lurza.secnetix.de (localhost [127.0.0.1]) by lurza.secnetix.de (8.14.3/8.14.3) with ESMTP id o6G6kIWu014458; Fri, 16 Jul 2010 08:46:33 +0200 (CEST) (envelope-from oliver.fromme@secnetix.de) Received: (from olli@localhost) by lurza.secnetix.de (8.14.3/8.14.3/Submit) id o6G6kI1H014456; Fri, 16 Jul 2010 08:46:18 +0200 (CEST) (envelope-from olli) From: Oliver Fromme Message-Id: <201007160646.o6G6kI1H014456@lurza.secnetix.de> To: davidxu@freebsd.org (David Xu) Date: Fri, 16 Jul 2010 08:46:18 +0200 (CEST) In-Reply-To: <4C3FB73F.7070502@freebsd.org> X-Mailer: ELM [version 2.5 PL8] MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.3.4 (lurza.secnetix.de [127.0.0.1]); Fri, 16 Jul 2010 08:46:34 +0200 (CEST) Cc: freebsd-stable@freebsd.org, Andriy Gapon , Jung-uk Kim , ivoras@freebsd.org Subject: Re: 8.1-PRERELEASE: CPU packages not detected correctly X-BeenThere: freebsd-stable@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Production branch of FreeBSD source code List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Jul 2010 06:46:35 -0000 David Xu wrote: > Do you have patch for i386 branch ? I want to test. > On my Pentium-D machine: > > $ sysctl kern.sched.topology_spec > kern.sched.topology_spec: > > 0, 1 > > > > 0, 1 > > > > > > > it seems the kernel thinks that the Pentuim-D is sharing L2 cache, > but in fact, the design of the Pentium Ds was simply two P4 cores > sitting side by side. They do not share anything and they basically work > independently. Same thing on my intel Atom 330 board at home: 0, 1, 2, 3 0, 1, 2, 3 0, 1 HTT group 2, 3 HTT group The intel Atom 330 consists of two "Diamondville" dies on one package, each with its own 512 KB of L2 cache. There is no L3 cache, or any other shared cache. (Or maybe I misinterpret the XML output; I think that the "level" and "cache-level" numbers are confusing.) BTW, I noticed that the indentation problem (newline before "") is already fixed in -current, 5 weeks ago. Any plan to MFC this? Best regards Oliver -- Oliver Fromme, secnetix GmbH & Co. KG, Marktplatz 29, 85567 Grafing b. M. Handelsregister: Registergericht Muenchen, HRA 74606, Geschäftsfuehrung: secnetix Verwaltungsgesellsch. mbH, Handelsregister: Registergericht Mün- chen, HRB 125758, Geschäftsführer: Maik Bachmann, Olaf Erb, Ralf Gebhart FreeBSD-Dienstleistungen, -Produkte und mehr: http://www.secnetix.de/bsd "Python tricks" is a tough one, cuz the language is so clean. E.g., C makes an art of confusing pointers with arrays and strings, which leads to lotsa neat pointer tricks; APL mistakes everything for an array, leading to neat one-liners; and Perl confuses everything period, making each line a joyous adventure . -- Tim Peters