Date: Tue, 21 Mar 1995 22:13:44 -0800 (PST) From: "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com> To: bde@zeta.org.au (Bruce Evans) Cc: CVS-commiters@freefall.cdrom.com, cvs-sys@freefall.cdrom.com, davidg@freefall.cdrom.com Subject: Re: cvs commit: src/sys/i386/isa wd.c wdreg.h Message-ID: <199503220613.WAA07554@gndrsh.aac.dev.com> In-Reply-To: <199503220604.QAA04399@godzilla.zeta.org.au> from "Bruce Evans" at Mar 22, 95 04:04:06 pm
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> > > Modified: sys/i386/isa wd.c wdreg.h > > Log: > > Fixes and improvements from John Dyson: > > > > Fixed the I/O statistics > > Allow WD1007 type controllers to work > > Support MULTI-BLOCK I/O > > Correct delay to use port 0x84, reading the status register > > might not be a long enough delay. > > Changed probe message to match SCSI type devices. > > Please don't fix or improve wd.c or sd.c any more until the sliced > versions are committed. > > I've fixed the I/O statistics too. > > I used a WD1007 for 2 years. Who broke the support for it? :-). > > The delay needs to be done better. First, 1.x usec for an inb() is at > least (0.550 + 0.x) usec wasted. Second, some machines are reported > to optimize some motherboard inb()s. I think reading the status register > is more likely to give a long enough delay since the register is (much) > more likely to be on the bus. But this will not be near as long as you think it is if the IDE controller is on the PCI bus. It will be something like 8 clock ticks at 60Mhz, or about 120nS. Remeber we now have PCI IDE controllers, and lots of them. If you want I can time a few million INB's to the status register of a PCI EIDE controller and tell you how fast they are... > I've fixed the probe message too, but not to match the recently censored > SCSI messages. It was broken with the help of bogus indentation in > revision 1.31. > > Bruce > -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Custom computers for FreeBSD
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