Date: Wed, 26 Apr 2006 01:43:39 GMT From: Marcel Moolenaar <marcel@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 96121 for review Message-ID: <200604260143.k3Q1hdbC037414@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=96121 Change 96121 by marcel@marcel_nfs on 2006/04/26 01:42:39 Various preparatory changes: o Rename puc_query() to puc_config() as it's going to be used for more than just querying. o Pass a pointer to struct puc_softc instead of a pointer to struct puc_cfg to puc_config(), so that the config function can get to PCI config space and/or bus space. o Add sc_cfg_data to the softc so that puc_config() can store data. Its size is intptr_t so that it can also hold a pointer to a bigger blob of memory. o Get the port's clock. o Add a PUC_CFG_SETUP command so that hardware can be configured before use. o Add puc_config_quatech for Quatech boards. Affected files ... .. //depot/projects/uart/dev/puc/puc.c#34 edit .. //depot/projects/uart/dev/puc/puc_bfe.h#2 edit .. //depot/projects/uart/dev/puc/puc_cfg.c#2 edit .. //depot/projects/uart/dev/puc/puc_cfg.h#2 edit .. //depot/projects/uart/dev/puc/pucdata.c#26 edit Differences ... ==== //depot/projects/uart/dev/puc/puc.c#34 (text+ko) ==== @@ -206,7 +206,7 @@ return (error); } - error = puc_query(sc->sc_cfg, PUC_QUERY_NPORTS, 0, &res); + error = puc_config(sc, PUC_CFG_GET_NPORTS, 0, &res); KASSERT(error == 0, ("%s %d", __func__, __LINE__)); sc->sc_nports = (int)res; sc->sc_port = malloc(sc->sc_nports * sizeof(struct puc_port), @@ -216,14 +216,18 @@ if (error) goto fail; + error = puc_config(sc, PUC_CFG_SETUP, 0, &res); + if (error) + goto fail; + for (idx = 0; idx < sc->sc_nports; idx++) { port = &sc->sc_port[idx]; port->p_nr = idx + 1; - error = puc_query(sc->sc_cfg, PUC_QUERY_TYPE, idx, &res); + error = puc_config(sc, PUC_CFG_GET_TYPE, idx, &res); if (error) goto fail; port->p_type = res; - error = puc_query(sc->sc_cfg, PUC_QUERY_RID, idx, &res); + error = puc_config(sc, PUC_CFG_GET_RID, idx, &res); if (error) goto fail; bar = puc_get_bar(sc, res); @@ -233,11 +237,11 @@ } port->p_bar = bar; start = rman_get_start(bar->b_res); - error = puc_query(sc->sc_cfg, PUC_QUERY_OFS, idx, &res); + error = puc_config(sc, PUC_CFG_GET_OFS, idx, &res); if (error) goto fail; ofs = res; - error = puc_query(sc->sc_cfg, PUC_QUERY_LEN, idx, &res); + error = puc_config(sc, PUC_CFG_GET_LEN, idx, &res); if (error) goto fail; size = res; @@ -254,8 +258,14 @@ } port->p_ires = rman_reserve_resource(&sc->sc_irq, port->p_nr, port->p_nr, 1, 0, sc->sc_dev); - if (port->p_ires == NULL) + if (port->p_ires == NULL) { + error = ENXIO; + goto fail; + } + error = puc_config(sc, PUC_CFG_GET_CLOCK, idx, &res); + if (error) goto fail; + port->p_rclk = res; port->p_dev = device_add_child(dev, NULL, -1); if (port->p_dev != NULL) @@ -391,7 +401,7 @@ /* We don't attach to single-port serial cards. */ if (cfg->ports == PUC_PORT_1S || cfg->ports == PUC_PORT_1P) return (EDOOFUS); - error = puc_query(cfg, PUC_QUERY_NPORTS, 0, &res); + error = puc_config(sc, PUC_CFG_GET_NPORTS, 0, &res); if (error) return (error); ==== //depot/projects/uart/dev/puc/puc_bfe.h#2 (text+ko) ==== @@ -48,6 +48,7 @@ device_t sc_dev; const struct puc_cfg *sc_cfg; + intptr_t sc_cfg_data; struct puc_bar sc_bar[PUC_PCI_BARS]; struct rman sc_ioport; @@ -58,8 +59,8 @@ void *sc_icookie; int sc_irid; + int sc_nports; struct puc_port *sc_port; - int sc_nports; int sc_fastintr:1; int sc_leaving:1; ==== //depot/projects/uart/dev/puc/puc_cfg.c#2 (text+ko) ==== @@ -30,33 +30,36 @@ #include <sys/param.h> #include <sys/systm.h> #include <sys/bus.h> +#include <sys/rman.h> +#include <dev/puc/puc_bfe.h> #include <dev/puc/puc_bus.h> #include <dev/puc/puc_cfg.h> int -puc_query(const struct puc_cfg *cfg, enum puc_query q, int port, intptr_t *r) +puc_config(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, intptr_t *r) { + const struct puc_cfg *cfg = sc->sc_cfg; int error; - if (cfg->query_function != NULL) { - error = cfg->query_function(cfg, q, port, r); + if (cfg->config_function != NULL) { + error = cfg->config_function(sc, cmd, port, r); if (!error) return (0); } else error = EDOOFUS; - switch (q) { - case PUC_QUERY_CLOCK: + switch (cmd) { + case PUC_CFG_GET_CLOCK: if (cfg->clock < 0) return (error); *r = cfg->clock; return (0); - case PUC_QUERY_LEN: + case PUC_CFG_GET_LEN: /* The length of bus space needed by the port. */ *r = 8; return (0); - case PUC_QUERY_NPORTS: + case PUC_CFG_GET_NPORTS: /* The number of ports on this card. */ switch (cfg->ports) { case PUC_PORT_NONSTANDARD: @@ -92,13 +95,13 @@ return (0); } break; - case PUC_QUERY_OFS: + case PUC_CFG_GET_OFS: /* The offset relative to the RID. */ if (cfg->d_ofs < 0) return (error); *r = port * cfg->d_ofs; return (0); - case PUC_QUERY_RID: + case PUC_CFG_GET_RID: /* The RID for this port. */ if (port == 0) { if (cfg->rid < 0) @@ -109,14 +112,14 @@ if (cfg->d_rid < 0) return (error); if (cfg->rid < 0) { - error = puc_query(cfg, PUC_QUERY_RID, 0, r); + error = puc_config(sc, PUC_CFG_GET_RID, 0, r); if (error) return (error); } else *r = cfg->rid; *r += port * cfg->d_rid; return (0); - case PUC_QUERY_TYPE: + case PUC_CFG_GET_TYPE: /* The type of this port. */ if (cfg->ports == PUC_PORT_NONSTANDARD) return (error); @@ -152,6 +155,9 @@ } *r = PUC_TYPE_SERIAL; return (0); + case PUC_CFG_SETUP: + *r = ENXIO; + return (0); } return (ENXIO); ==== //depot/projects/uart/dev/puc/puc_cfg.h#2 (text+ko) ==== @@ -51,19 +51,19 @@ #define PUC_ILR_TYPE_DIGI 1 /* Configuration queries. */ -enum puc_query { - PUC_QUERY_CLOCK, - PUC_QUERY_LEN, - PUC_QUERY_NPORTS, - PUC_QUERY_OFS, - PUC_QUERY_RID, - PUC_QUERY_TYPE +enum puc_cfg_cmd { + PUC_CFG_GET_CLOCK, + PUC_CFG_GET_LEN, + PUC_CFG_GET_NPORTS, + PUC_CFG_GET_OFS, + PUC_CFG_GET_RID, + PUC_CFG_GET_TYPE, + PUC_CFG_SETUP }; -struct puc_cfg; +struct puc_softc; -typedef int puc_query_f(const struct puc_cfg *, enum puc_query, int, - intptr_t *); +typedef int puc_config_f(struct puc_softc *, enum puc_cfg_cmd, int, intptr_t *); struct puc_cfg { uint16_t vendor; @@ -76,9 +76,9 @@ int8_t rid; /* Rid of first port */ int8_t d_rid; /* Delta rid of next ports */ int8_t d_ofs; /* Delta offset of next ports */ - puc_query_f *query_function; + puc_config_f *config_function; }; -puc_query_f puc_query; +puc_config_f puc_config; #endif /* _DEV_PUC_CFG_H_ */ ==== //depot/projects/uart/dev/puc/pucdata.c#26 (text+ko) ==== @@ -42,12 +42,13 @@ #include <dev/puc/puc_cfg.h> -static puc_query_f puc_query_cronyx; -static puc_query_f puc_query_diva; -static puc_query_f puc_query_icbook; -static puc_query_f puc_query_syba; -static puc_query_f puc_query_siig; -static puc_query_f puc_query_titan; +static puc_config_f puc_config_cronyx; +static puc_config_f puc_config_diva; +static puc_config_f puc_config_icbook; +static puc_config_f puc_config_quatech; +static puc_config_f puc_config_syba; +static puc_config_f puc_config_siig; +static puc_config_f puc_config_titan; const struct puc_cfg puc_pci_devices[] = { @@ -61,7 +62,7 @@ "Diva Serial [GSP] Multiport UART", DEFAULT_RCLK, PUC_PORT_3S, 0x10, 0, -1, - .query_function = puc_query_diva + .config_function = puc_config_diva }, { 0x10b5, 0x1076, 0x10b5, 0x1076, @@ -311,21 +312,21 @@ "SIIG Cyber 2P1S PCI 16C550 (20x family)", DEFAULT_RCLK, PUC_PORT_1S2P, 0x10, -1, 0, - .query_function = puc_query_siig + .config_function = puc_config_siig }, { 0x131f, 0x2041, 0xffff, 0, "SIIG Cyber 2P1S PCI 16C650 (20x family)", DEFAULT_RCLK, PUC_PORT_1S2P, 0x10, -1, 0, - .query_function = puc_query_siig + .config_function = puc_config_siig }, { 0x131f, 0x2042, 0xffff, 0, "SIIG Cyber 2P1S PCI 16C850 (20x family)", DEFAULT_RCLK, PUC_PORT_1S2P, 0x10, -1, 0, - .query_function = puc_query_siig + .config_function = puc_config_siig }, { 0x131f, 0x2050, 0xffff, 0, @@ -368,60 +369,70 @@ "Quatech - QSC-100", DEFAULT_RCLK, PUC_PORT_4S, 0x14, 0, 8, + .config_function = puc_config_quatech }, { 0x135c, 0x0020, 0xffff, 0, "Quatech - DSC-100", DEFAULT_RCLK, PUC_PORT_2S, 0x14, 0, 8, + .config_function = puc_config_quatech }, { 0x135c, 0x0030, 0xffff, 0, "Quatech - DSC-200/300", DEFAULT_RCLK, PUC_PORT_2S, 0x14, 0, 8, + .config_function = puc_config_quatech }, { 0x135c, 0x0040, 0xffff, 0, "Quatech - QSC-200/300", DEFAULT_RCLK, PUC_PORT_4S, 0x14, 0, 8, + .config_function = puc_config_quatech }, { 0x135c, 0x0050, 0xffff, 0, "Quatech - ESC-100D", DEFAULT_RCLK, PUC_PORT_8S, 0x14, 0, 8, + .config_function = puc_config_quatech }, { 0x135c, 0x0060, 0xffff, 0, "Quatech - ESC-100M", DEFAULT_RCLK, PUC_PORT_8S, 0x14, 0, 8, + .config_function = puc_config_quatech }, { 0x135c, 0x0170, 0xffff, 0, "Quatech - QSCLP-100", DEFAULT_RCLK, PUC_PORT_4S, 0x18, 0, 8, - }, + .config_function = puc_config_quatech + }, { 0x135c, 0x0180, 0xffff, 0, "Quatech - DSCLP-100", DEFAULT_RCLK, PUC_PORT_2S, 0x18, 0, 8, + .config_function = puc_config_quatech }, { 0x135c, 0x01b0, 0xffff, 0, "Quatech - DSCLP-200/300", DEFAULT_RCLK, PUC_PORT_2S, 0x18, 0, 8, + .config_function = puc_config_quatech }, { 0x135c, 0x01e0, 0xffff, 0, "Quatech - ESCLP-100", DEFAULT_RCLK, PUC_PORT_8S, 0x10, 0, 8, + .config_function = puc_config_quatech }, { 0x1393, 0x1040, 0xffff, 0, @@ -458,7 +469,7 @@ "Cronyx Omega2-PCI", DEFAULT_RCLK * 8, PUC_PORT_8S, 0x10, 0, -1, - .query_function = puc_query_cronyx + .config_function = puc_config_cronyx }, { 0x1407, 0x0100, 0xffff, 0, /* MASK */ @@ -542,7 +553,7 @@ "Titan VScom PCI-800L", DEFAULT_RCLK * 8, PUC_PORT_8S, 0x14, -1, -1, - .query_function = puc_query_titan + .config_function = puc_config_titan }, /* @@ -589,7 +600,7 @@ "Syba Tech Ltd. PCI-4S2P-550-ECP", DEFAULT_RCLK, PUC_PORT_4S1P, 0x10, 0, -1, - .query_function = puc_query_syba + .config_function = puc_config_syba }, { 0x6666, 0x0001, 0xffff, 0, @@ -620,42 +631,42 @@ "IC Book Labs Gunboat x4 Lite", DEFAULT_RCLK, PUC_PORT_4S, 0x10, 0, 8, - .query_function = puc_query_icbook + .config_function = puc_config_icbook }, { 0xb00c, 0x031c, 0xffff, 0, "IC Book Labs Gunboat x4 Pro", DEFAULT_RCLK, PUC_PORT_4S, 0x10, 0, 8, - .query_function = puc_query_icbook + .config_function = puc_config_icbook }, { 0xb00c, 0x041c, 0xffff, 0, "IC Book Labs Ironclad x8 Lite", DEFAULT_RCLK, PUC_PORT_8S, 0x10, 0, 8, - .query_function = puc_query_icbook + .config_function = puc_config_icbook }, { 0xb00c, 0x051c, 0xffff, 0, "IC Book Labs Ironclad x8 Pro", DEFAULT_RCLK, PUC_PORT_8S, 0x10, 0, 8, - .query_function = puc_query_icbook + .config_function = puc_config_icbook }, { 0xb00c, 0x081c, 0xffff, 0, "IC Book Labs Dreadnought x16 Pro", DEFAULT_RCLK * 8, PUC_PORT_16S, 0x10, 0, 8, - .query_function = puc_query_icbook + .config_function = puc_config_icbook }, { 0xb00c, 0x091c, 0xffff, 0, "IC Book Labs Dreadnought x16 Lite", DEFAULT_RCLK, PUC_PORT_16S, 0x10, 0, 8, - .query_function = puc_query_icbook + .config_function = puc_config_icbook }, { 0xb00c, 0x0a1c, 0xffff, 0, @@ -668,39 +679,46 @@ "IC Book Labs Gunboat x4 Low Profile", DEFAULT_RCLK, PUC_PORT_4S, 0x10, 0, 8, - .query_function = puc_query_icbook + .config_function = puc_config_icbook }, { 0xffff, 0, 0xffff, 0, NULL, 0 } }; static int -puc_query_cronyx(const struct puc_cfg *cfg, enum puc_query q, int port, +puc_config_cronyx(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, + intptr_t *res) +{ + return (ENXIO); +} + +static int +puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, intptr_t *res) { return (ENXIO); } static int -puc_query_diva(const struct puc_cfg *cfg, enum puc_query q, int port, +puc_config_icbook(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, intptr_t *res) { return (ENXIO); } static int -puc_query_icbook(const struct puc_cfg *cfg, enum puc_query q, int port, +puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, intptr_t *res) { return (ENXIO); } static int -puc_query_syba(const struct puc_cfg *cfg, enum puc_query q, int port, +puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, intptr_t *res) { - switch (q) { - case PUC_QUERY_OFS: + switch (cmd) { + case PUC_CFG_GET_OFS: switch (port) { case 0: *res = 0x3f8; @@ -726,14 +744,14 @@ } static int -puc_query_siig(const struct puc_cfg *cfg, enum puc_query q, int port, +puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, intptr_t *res) { return (ENXIO); } static int -puc_query_titan(const struct puc_cfg *cfg, enum puc_query q, int port, +puc_config_titan(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, intptr_t *res) { return (ENXIO);
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