From owner-freebsd-mips@FreeBSD.ORG Mon Dec 13 14:51:26 2010 Return-Path: Delivered-To: mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id AD51D106564A for ; Mon, 13 Dec 2010 14:51:26 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id 6BA158FC0A for ; Mon, 13 Dec 2010 14:51:26 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by harmony.bsdimp.com (8.14.3/8.14.1) with ESMTP id oBDEmXmM038535; Mon, 13 Dec 2010 07:48:33 -0700 (MST) (envelope-from imp@bsdimp.com) Message-ID: <4D063241.4030800@bsdimp.com> Date: Mon, 13 Dec 2010 07:48:33 -0700 From: Warner Losh User-Agent: Mozilla/5.0 (X11; U; FreeBSD amd64; en-US; rv:1.9.2.12) Gecko/20101029 Thunderbird/3.1.6 MIME-Version: 1.0 To: Tijl Coosemans References: <201012121417.28343.tijl@coosemans.org> <4D05084C.10308@bsdimp.com> <201012131506.45650.tijl@coosemans.org> In-Reply-To: <201012131506.45650.tijl@coosemans.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: Kostik Belousov , mips@freebsd.org, Bruce Evans Subject: Re: mips sig_atomic_t X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 13 Dec 2010 14:51:26 -0000 On 12/13/2010 07:06, Tijl Coosemans wrote: > On Sunday 12 December 2010 18:37:16 Warner Losh wrote: >> On 12/12/2010 06:17, Tijl Coosemans wrote: >>> In mips/include/signal.h sig_atomic_t is defined as int. Do you know if >>> this can be 64 bit on the N64 ABI like on other 64 bit archs? How about >>> N32? For reference, the POSIX definition of sig_atomic_t states: possibly >>> volatile-qualified integer type of an object that can be accessed as an >>> atomic entity, even in the presence of asynchronous interrupts. >> LD and SD can be used to load/store an aligned 64-bit word in a >> mips64-like ISA. For mips32 ISAs, a 64-bit quantity is loaded/stored >> with two LW/SW instructions. >> >> N64 and N32 can load/store these. However, N32 has an int set to >> 32-bits. I think this is OK. > I'm still not sure if I understand the relations between the different > acronyms correctly. Are these statements correct? > > There's a MIPS32 ISA and a MIPS64 ISA. > Among others, but these are the two big families. Also, it may be better to view things as running in 32-bit mode and 64-bit mode... > The O32 ABI is ILP32 running on MIPS32. Like any ordinary 32 bit arch. > It can run on MIPS64 ISA also in 32-bit mode. > The N64 ABI is LP64 running on MIPS64. Like any ordinary 64 bit arch. Correct. > The N32 ABI is ILP32 running on MIPS64. It's pure MIPS64 not a > compatibility mode or something like i386 code running on amd64. It has > 64 bit registers and can do 64 bit load/store. It is ILP32 on top of 64-bit registers. The difference between 32-bit and 64-bit modes in MIPS is much smaller than the i386/amd64 differences. 64-bit mode just has a few extra instructions and operates generally on 64-bit registers rather than 32-bit registers. The only weird thing is that 32-bit mode on a 64-bit computer sign-extends the 32-bit addresses to 64-bits. Warner