From owner-freebsd-alpha Thu Jul 19 12:30:54 2001 Delivered-To: freebsd-alpha@freebsd.org Received: from meow.osd.bsdi.com (meow.osd.bsdi.com [204.216.28.88]) by hub.freebsd.org (Postfix) with ESMTP id 6088537B401 for ; Thu, 19 Jul 2001 12:30:50 -0700 (PDT) (envelope-from jhb@FreeBSD.org) Received: from laptop.baldwin.cx (john@jhb-laptop.osd.bsdi.com [204.216.28.241]) by meow.osd.bsdi.com (8.11.4/8.11.2) with ESMTP id f6JJUhv33341; Thu, 19 Jul 2001 12:30:43 -0700 (PDT) (envelope-from jhb@FreeBSD.org) Message-ID: X-Mailer: XFMail 1.4.0 on FreeBSD X-Priority: 3 (Normal) Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 8bit MIME-Version: 1.0 In-Reply-To: <20010719120433.D50024-100000@wonky.feral.com> Date: Thu, 19 Jul 2001 12:30:52 -0700 (PDT) From: John Baldwin To: Matthew Jacob Subject: RE: multiple cpus on an 8200... Cc: alpha@FreeBSD.org Sender: owner-freebsd-alpha@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.org On 19-Jul-01 Matthew Jacob wrote: > No, actually there's a TLSB register bit for this: > >#define TLINTRMASK0 0x1100 /* C: Interrupt Mask Register CPU 0 */ >#define TLINTRMASK1 0x1140 /* C: Interrupt Mask Register CPU 1 */ > > .... > /* > * CPU Interrupt Mask Register > * > * The PAL code reads this register for each CPU on a TLSB CPU board > * to see what is or isn't enabled. > */ >#define TLINTRMASK_CONHALT 0x100 /* Enable ^P Halt */ >#define TLINTRMASK_HALT 0x080 /* Enable Halt */ >#define TLINTRMASK_CLOCK 0x040 /* Enable Clock Interrupts */ >#define TLINTRMASK_XCALL 0x020 /* Enable Interprocessor Interrupts */ >#define TLINTRMASK_IPL17 0x010 /* Enable IPL 17 Interrupts */ >#define TLINTRMASK_IPL16 0x008 /* Enable IPL 16 Interrupts */ >#define TLINTRMASK_IPL15 0x004 /* Enable IPL 15 Interrupts */ >#define TLINTRMASK_IPL14 0x002 /* Enable IPL 14 Interrupts */ >#define TLINTRMASK_DUART 0x001 /* Enable GBUS Duart0 Interrupts */ > > It turns out that the XCALL (IPI) is enabled on both CPUs on jules: > > TLINTRMASK0 1ff TLINTRMASK1 fe > > That is, CPU0 has ^P halt set, while CPU1 doesn't have GBUS zs interrupts > set. > > Interestingly enough, both have clock interrupts enabled- I might try fixing > that. No, please leave that on. Having the system broadcast clock interrupts is much nice than us having to IPI all the other CPU's when a clock interrupt comes in, and this is how all the other alpha SMP systems seem to be working (and is how the port assumes alpha SMP handles clock interrupts). > It's wierd- I had left jules booting yesterday- I was able to log in and run > everything up until a ps (see below), whereupon it hangs for a while. > > -matt Did it eventually unhang? -- John Baldwin -- http://www.FreeBSD.org/~jhb/ PGP Key: http://www.baldwin.cx/~john/pgpkey.asc "Power Users Use the Power to Serve!" - http://www.FreeBSD.org/ To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-alpha" in the body of the message