From owner-svn-src-head@FreeBSD.ORG Fri Apr 3 19:21:40 2009 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 2352F106566B; Fri, 3 Apr 2009 19:21:40 +0000 (UTC) (envelope-from rnoland@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 0F8908FC1A; Fri, 3 Apr 2009 19:21:40 +0000 (UTC) (envelope-from rnoland@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n33JLdCo030831; Fri, 3 Apr 2009 19:21:39 GMT (envelope-from rnoland@svn.freebsd.org) Received: (from rnoland@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n33JLdtJ030829; Fri, 3 Apr 2009 19:21:39 GMT (envelope-from rnoland@svn.freebsd.org) Message-Id: <200904031921.n33JLdtJ030829@svn.freebsd.org> From: Robert Noland Date: Fri, 3 Apr 2009 19:21:39 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r190674 - head/sys/dev/drm X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Apr 2009 19:21:43 -0000 Author: rnoland Date: Fri Apr 3 19:21:39 2009 New Revision: 190674 URL: http://svn.freebsd.org/changeset/base/190674 Log: A little more cleanup from AMD, if we don't have the right microcode there is no reason to mess with the chip. MFC after: 3 days Modified: head/sys/dev/drm/r600_cp.c head/sys/dev/drm/radeon_cp.c Modified: head/sys/dev/drm/r600_cp.c ============================================================================== --- head/sys/dev/drm/r600_cp.c Fri Apr 3 19:17:23 2009 (r190673) +++ head/sys/dev/drm/r600_cp.c Fri Apr 3 19:21:39 2009 (r190674) @@ -286,20 +286,6 @@ static void r600_cp_load_microcode(drm_r const u32 *pfp; int i; - r600_do_cp_stop(dev_priv); - - RADEON_WRITE(R600_CP_RB_CNTL, - R600_RB_NO_UPDATE | - R600_RB_BLKSZ(15) | - R600_RB_BUFSZ(3)); - - RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); - RADEON_READ(R600_GRBM_SOFT_RESET); - DRM_UDELAY(15000); - RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); - - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - switch (dev_priv->flags & RADEON_FAMILY_MASK) { case CHIP_R600: DRM_INFO("Loading R600 Microcode\n"); @@ -337,19 +323,32 @@ static void r600_cp_load_microcode(drm_r pfp = RS780_pfp_microcode; break; default: - goto no_microcode; + return; } - for (i = 0; i != PM4_UCODE_SIZE; i++) { + r600_do_cp_stop(dev_priv); + + RADEON_WRITE(R600_CP_RB_CNTL, + R600_RB_NO_UPDATE | + R600_RB_BLKSZ(15) | + R600_RB_BUFSZ(3)); + + RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); + RADEON_READ(R600_GRBM_SOFT_RESET); + DRM_UDELAY(15000); + RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); + + RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); + + for (i = 0; i < PM4_UCODE_SIZE; i++) { RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]); RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]); RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]); } RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - for (i = 0; i != PFP_UCODE_SIZE; i++) + for (i = 0; i < PFP_UCODE_SIZE; i++) RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]); -no_microcode:; RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); @@ -415,21 +414,9 @@ static void r700_cp_load_microcode(drm_r const u32 *cp; int i; - r600_do_cp_stop(dev_priv); - - RADEON_WRITE(R600_CP_RB_CNTL, - R600_RB_NO_UPDATE | - (15 << 8) | - (3 << 0)); - - RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); - RADEON_READ(R600_GRBM_SOFT_RESET); - DRM_UDELAY(15000); - RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); - switch (dev_priv->flags & RADEON_FAMILY_MASK) { case CHIP_RV770: - DRM_INFO("Loading RV770 Microcode\n"); + DRM_INFO("Loading RV770/RV790 Microcode\n"); pfp = RV770_pfp_microcode; cp = RV770_cp_microcode; break; @@ -444,19 +431,30 @@ static void r700_cp_load_microcode(drm_r cp = RV710_cp_microcode; break; default: - goto no_microcode; + return; } + r600_do_cp_stop(dev_priv); + + RADEON_WRITE(R600_CP_RB_CNTL, + R600_RB_NO_UPDATE | + (15 << 8) | + (3 << 0)); + + RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); + RADEON_READ(R600_GRBM_SOFT_RESET); + DRM_UDELAY(15000); + RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); + RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - for (i = 0; i != R700_PFP_UCODE_SIZE; i++) + for (i = 0; i < R700_PFP_UCODE_SIZE; i++) RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]); RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - for (i = 0; i != R700_PM4_UCODE_SIZE; i++) + for (i = 0; i < R700_PM4_UCODE_SIZE; i++) RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]); RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); -no_microcode:; RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); Modified: head/sys/dev/drm/radeon_cp.c ============================================================================== --- head/sys/dev/drm/radeon_cp.c Fri Apr 3 19:17:23 2009 (r190673) +++ head/sys/dev/drm/radeon_cp.c Fri Apr 3 19:21:39 2009 (r190674) @@ -460,9 +460,6 @@ static void radeon_cp_load_microcode(drm DRM_DEBUG("\n"); - radeon_do_wait_for_idle(dev_priv); - - RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); switch (dev_priv->flags & RADEON_FAMILY_MASK) { case CHIP_R100: case CHIP_RV100: @@ -516,6 +513,10 @@ static void radeon_cp_load_microcode(drm return; } + radeon_do_wait_for_idle(dev_priv); + + RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); + for (i = 0; i != 256; i++) { RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]); RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]);