From owner-freebsd-arm@freebsd.org Sat Sep 15 02:26:32 2018 Return-Path: Delivered-To: freebsd-arm@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 50E16109A0F6 for ; Sat, 15 Sep 2018 02:26:32 +0000 (UTC) (envelope-from marklmi@yahoo.com) Received: from sonic303-20.consmr.mail.ne1.yahoo.com (sonic303-20.consmr.mail.ne1.yahoo.com [66.163.188.146]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id D8A307B36D for ; Sat, 15 Sep 2018 02:26:31 +0000 (UTC) (envelope-from marklmi@yahoo.com) X-YMail-OSG: NB71J_QVM1lHaYTMyEZ8Mu9klXBp3SIhoNvvv3fvqw1CTxi0XluNIS4hPhgm.zB F6hEZ6IfCpY8cROszfmdpJAqDyoGboXVIC4za8RYuGV6KiGVU0SvuWAxTODi6aKPfAwpVoKYoS1w e4qGhWJpWFx3n9S_gI2qKoviP3mWFQ7cECKlMl8HPLfcPeFh5RiAsPQk8vLL1hhksWGD3IQqq8FX CIH4tNbDqnywBfwVRKmqUBM6KrlvwrWZL2rmMZk7LM45u0Ygz.FNv8gRbhQh19bFFL4KHDpAWTal XPGHgrjt_BzPX563u5RsoeH6jgLpbjhSSA_PvZcn29_XQRIDURR06_.1Xecpf7fjujLtONFBy0cX NpZdDvGEn9w3MCifJh12uzGHD6wDdWnYux6CxP31U68py6Njh4Q2LHroxkWBKBzj_4cDiUxyPmp4 2M8x1.EsDo48H7Iqga7ha3vJcYvnL7eVrfkeTInnEHTBeCOW3Q2n0.Kf5IyIhZ8sOOd86mBXT.Ft eAqtcgdADkbAl9pPyUUs0AwsZcxH0ekmXEKxEnMhffemtNu0_u5sn4OqDayuGFdkK08K9pkQB0xL H_S4PyKlxsjgY7r8y0JED0MrTR3qmKUa15XP4JJ2MoPwdc1IuS7zX2NjAofCj1q6WvJ9avB2NlwO nGCuu_7YosLinQei5vQQ1p03dmmpbBhlgaSK1RIsYajIjvM7w34aqeiOmSJrtTHing6XFnoMKZpU BfNociTIWvF.kTnAlPi6squItRP82gNE_FIt2CzwUJ3QfZ7nDv_75I5t59bIqwJ7S8.VIVN_dkUP B.M7zlWeqMsYQJtYj.1zSOKQCNWl9wxItV.PcBG8l0SdBP7YS_mXB23HKlEFGbWzqQ7j26LkwESU Wo4T10fGAoPBZNBirhYADrd_lLYKWijTnjG5c.njPKIQSguvZ6eETC_5HDnw.z_Y6MVAs0WauvFj .vuJCKAaHmU9gpe1IMgHqLAMLx89q7GiK8vA2FuansHTdzytwgtOz.fYawgrAQejj19ScLrSEkhN hTOQSm1pPAX1q Received: from sonic.gate.mail.ne1.yahoo.com by sonic303.consmr.mail.ne1.yahoo.com with HTTP; Sat, 15 Sep 2018 02:26:24 +0000 Received: from ip70-189-131-151.lv.lv.cox.net (EHLO [192.168.0.105]) ([70.189.131.151]) by smtp405.mail.ne1.yahoo.com (Oath Hermes SMTP Server) with ESMTPA ID 5e7b754f31acfc8d4eeb553d17f279ee; Sat, 15 Sep 2018 02:16:17 +0000 (UTC) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.1\)) Subject: Re: An experimental hack that makes head -r338518 boot from e.MMC via an microsd card adapter, in DDR52 mode at that From: Mark Millard In-Reply-To: <6D375D5B-34E2-4124-9A32-92C320AD6A54@yahoo.com> Date: Fri, 14 Sep 2018 19:16:15 -0700 Cc: Emmanuel Vadot , Marius Strobl Content-Transfer-Encoding: quoted-printable Message-Id: <9C3963A6-5786-4755-9C4F-6F75FFFFDEE5@yahoo.com> References: <6D375D5B-34E2-4124-9A32-92C320AD6A54@yahoo.com> To: freebsd-arm X-Mailer: Apple Mail (2.3445.9.1) X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 15 Sep 2018 02:26:32 -0000 [I'm replacing the original hack with something that is less of one. But this is just investigatory, based on my limited testing context (just a Pine64+ 2GB) and lack of a general background in the source code and its criteria. Hopefully the material is of some use.] The following adjustments track the lack of wanting to support 1.8V because of other restrictions and so lead to the use of the e.MMC DDR52 using the range around 3V for the Pine64+ 2GB. (I expect A64 generality but have only one test context.) # svnlite diff /usr/src/sys//dev/mmc/ /usr/src/sys/arm/allwinner/ = = Index: = /usr/src/sys/dev/mmc/mmc.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- /usr/src/sys/dev/mmc/mmc.c (revision 338675) +++ /usr/src/sys/dev/mmc/mmc.c (working copy) @@ -1814,10 +1814,10 @@ setbit(&ivar->timings, = bus_timing_mmc_ddr52); setbit(&ivar->vccq_120, = bus_timing_mmc_ddr52); } - if ((card_type & EXT_CSD_CARD_TYPE_DDR_52_1_8V) = !=3D 0 && - (host_caps & MMC_CAP_SIGNALING_180) !=3D 0) = { + if ((card_type & = EXT_CSD_CARD_TYPE_DDR_52_3V_OR_1_8V) !=3D 0) { setbit(&ivar->timings, = bus_timing_mmc_ddr52); - setbit(&ivar->vccq_180, = bus_timing_mmc_ddr52); + if ((host_caps & MMC_CAP_SIGNALING_180) = !=3D 0) + setbit(&ivar->vccq_180, = bus_timing_mmc_ddr52); } if ((card_type & EXT_CSD_CARD_TYPE_HS200_1_2V) = !=3D 0 && (host_caps & MMC_CAP_SIGNALING_120) !=3D 0) = { Index: /usr/src/sys/dev/mmc/mmcreg.h =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- /usr/src/sys/dev/mmc/mmcreg.h (revision 338675) +++ /usr/src/sys/dev/mmc/mmcreg.h (working copy) @@ -463,7 +463,7 @@ =20 #define EXT_CSD_CARD_TYPE_HS_26 0x0001 #define EXT_CSD_CARD_TYPE_HS_52 0x0002 -#define EXT_CSD_CARD_TYPE_DDR_52_1_8V 0x0004 +#define EXT_CSD_CARD_TYPE_DDR_52_3V_OR_1_8V 0x0004 #define EXT_CSD_CARD_TYPE_DDR_52_1_2V 0x0008 #define EXT_CSD_CARD_TYPE_HS200_1_8V 0x0010 #define EXT_CSD_CARD_TYPE_HS200_1_2V 0x0020 Index: /usr/src/sys/arm/allwinner/aw_mmc.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- /usr/src/sys/arm/allwinner/aw_mmc.c (revision 338675) +++ /usr/src/sys/arm/allwinner/aw_mmc.c (working copy) @@ -509,7 +509,7 @@ MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_MMC_DDR52; =20 - sc->aw_host.caps |=3D MMC_CAP_SIGNALING_330 | = MMC_CAP_SIGNALING_180; + sc->aw_host.caps |=3D MMC_CAP_SIGNALING_330; // | = MMC_CAP_SIGNALING_180; not used on Pine64+ 2GB =20 if (bus_width >=3D 4) sc->aw_host.caps |=3D MMC_CAP_4_BIT_DATA; @@ -1308,17 +1308,20 @@ =20 sc =3D device_get_softc(bus); =20 - if (sc->aw_reg_vqmmc =3D=3D NULL) - return EOPNOTSUPP; - switch (sc->aw_host.ios.vccq) { case vccq_180: + if (sc->aw_reg_vqmmc =3D=3D NULL) + return EOPNOTSUPP; uvolt =3D 1800000; break; case vccq_330: + if (sc->aw_reg_vqmmc =3D=3D NULL) // implicitly already = stuck at vccq_330 + return 0; // avoid calling code treating the = assignment attempt as an error uvolt =3D 3300000; break; default: + if (sc->aw_reg_vqmmc =3D=3D NULL) + return EOPNOTSUPP; return EINVAL; } =20 The above is sufficient for the Pine64+ 2GB to boot and operate from the e.MMC on a microsd card adapter, using DDR52, without the prior hack being present. I can not claim to know enough to make sure the changes are fully general. MMC_CAP_SIGNALING_180 is/was used in the following places: # grep -r MMC_CAP_SIGNALING_180 /usr/src/sys/ /usr/src/sys/arm/allwinner/aw_mmc.c: sc->aw_host.caps |=3D = MMC_CAP_SIGNALING_330; // | MMC_CAP_SIGNALING_180; not used on Pine64+ = 2GB /usr/src/sys/dev/sdhci/sdhci.c: host_caps |=3D = MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180; /usr/src/sys/dev/sdhci/sdhci.c: host_caps &=3D = ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180); /usr/src/sys/dev/sdhci/sdhci.c: (host_caps & = MMC_CAP_SIGNALING_180) ? " 1.8V" : "", /usr/src/sys/dev/sdhci/sdhci.c: if (!(slot->host.caps & = MMC_CAP_SIGNALING_180)) { /usr/src/sys/dev/mmc/mmc.c: if ((host_caps & = MMC_CAP_SIGNALING_180) !=3D 0) /usr/src/sys/dev/mmc/mmc.c: (host_caps & = MMC_CAP_SIGNALING_180) !=3D 0) { /usr/src/sys/dev/mmc/mmc.c: (host_caps & = MMC_CAP_SIGNALING_180) !=3D 0 && /usr/src/sys/dev/mmc/mmc.c: (host_caps & = MMC_CAP_SIGNALING_180) !=3D 0 && /usr/src/sys/dev/mmc/bridge.h:#define MMC_CAP_SIGNALING_180 (1 << = 19) /* Can do signaling at 1.8 V */ I've not done anything relative to the following, as in my limited test context I've not found a operational difference and I do not have the general background to work without such as a cross check. It seem that sdhci_init_slot is another area of source code that forces MMC_CAP_SIGNALING_180, this time for MMC_CAP_MMC_DDR52 use (and MMC_CAP_MMC_DDR52_180 use): /* Determine supported VCCQ signaling levels. */ host_caps |=3D MMC_CAP_SIGNALING_330; if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | MMC_CAP_MMC_HS400_180)) host_caps |=3D MMC_CAP_SIGNALING_120 | = MMC_CAP_SIGNALING_180; where MMC_CAP_MMC_DDR52 and MMC_CAP_MMC_DDR52 _180 are based on: /usr/src/sys/dev/mmc/bridge.h:#define MMC_CAP_MMC_DDR52_120 (1 << = 11) /* Can do eMMC DDR52 at 1.2 V */ /usr/src/sys/dev/mmc/bridge.h:#define MMC_CAP_MMC_DDR52_180 (1 << = 12) /* Can do eMMC DDR52 at 1.8 V */ /usr/src/sys/dev/mmc/bridge.h:#define MMC_CAP_MMC_DDR52 = (MMC_CAP_MMC_DDR52_120 | MMC_CAP_MMC_DDR52_180) (so MMC_CAP_MMC_DDR52 includes MMC_CAP_MMC_DDR52_180). Having e.MMC DDR52 only using the range around 3V does not seem to be = covered in sdhci_init_slot . =3D=3D=3D Mark Millard marklmi at yahoo.com ( dsl-only.net went away in early 2018-Mar)