Date: Wed, 21 May 1997 22:36:31 +1000 From: Bruce Evans <bde@zeta.org.au> To: bde@zeta.org.au, se@FreeBSD.ORG Cc: garycorc@idt.net, HARDWARE@FreeBSD.ORG Subject: Re: isa bus and boca multiport boards Message-ID: <199705211236.WAA23416@godzilla.zeta.org.au>
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>> Times in usec for inb() from selected ports on an ASUS P55TP4XE with >> a P5/133: >> >> min av max speed important for FreeBSD? >> ----- ----- ----- ---------------------------- >> 0x3d4 (crtc data) 0.393 0.393 0.395 no >> 0x3d5 (crtc data) 0.393 0.393 0.395 no >> 0xe428 (de0 status) 0.332 0.333 0.334 yes (if = data access speed) >> addr+0x14 (ncr0 status) 0.363 0.363 0.394 yes (if = data access speed) I tried using 1 ins[bwl](port, dummyaddr, 1000) instead of 1000 inb's. The results were (perhaps not surprisingly) similar. They were within 1 nsec for de0, varied a lot with the access size for the crtc, and were within 1 nsec for ins[bw] from wdc0 and twice as large for insl from wdc0 (1510 nsec instead of 755 nsec). The latter is a bit surprising - my wdc0 is configured for and uses 32-bit accesses and has a 16MB/s transfer speed, yet 4 bytes per 1510 nsec is only 2.65 MB/s. I guess the wdc data register is only valid when there is real data available :-). >> I think the minimum access time is 30 nsec for PCI. There are no signs >> of that here. Accesses can be wider than for ISA, but cheap serial >> boards based on 8-bit UARTs are unlikely to implement anything other >> than 8-bit accesses. > >No, PCI uses a bus cycle time of 30ns (33MHz) maximum, >but the shortest access latency to a single data item >is 4 bus clocks (120ns). Your fastest register accesses >seem to require 11 and 13 PCI bus cycles, though. >The NCR chip uses a 12 cycle micro-program that controls >all its operations, which explains the delay you found. > >1) The CPU has to apply all the signals for the port > access, and the host to PCI bridge has to decode > them before it can start a PCI cycle. > >2) The PCI bus may have been "parked" at some other > bus master. In order to give the output drivers > of the current master time to go into a high > impedance state, one cycle of delay is added. Clearly some magic (like data available :-) is required to get burst mode. Do you thing 300+ nsec is typical for non-data registers? Bruce
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