Date: 19 Jun 1999 15:55:36 -0400 From: Shaun Rowland <rowland@cis.ohio-state.edu> To: Warner Losh <imp@harmony.village.org> Cc: Marc Nicholas <marc@netstor.com>, Pat Lynch <lynch@bsdunix.net>, hackers@FreeBSD.ORG Subject: Re: SMP and Celerons... Message-ID: <87hfo4c6dj.fsf@dhcp9545042.columbus.rr.com> In-Reply-To: Warner Losh's message of "Sat, 19 Jun 1999 11:07:36 -0600" References: <Pine.BSF.4.05.9906191302400.16699-100000@medulla.hippocampus.net> <199906191707.LAA86070@harmony.village.org>
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Warner Losh <imp@harmony.village.org> writes: > In message <Pine.BSF.4.05.9906191302400.16699-100000@medulla.hippocampus.net> Marc Nicholas writes: > : Hmmm...I always thought there was something "broke" inside Celerons to > : prevent SMP...maybe I'm wrong? Sure would be neat if you could run them > : SMP... > > What is "broke" about the Celerons is their cache. Without a good > cache sharing, you can't get good SMP performance. While you can run > a SMP Celeron machine, it won't scale as well as the PII version of > the chip. > > Warner Do you mean the ones that don't have cache or the ones that have 128Kb cache on the chip? Is there that big of a hit of the cache is on the chip? I have seen some benchmarks and the system I have seemed to keep up well with a dual PII 400. I don't know how well it would scale though. -- Shaun Rowland rowland@cis.ohio-state.edu http://www.cis.ohio-state.edu/~rowland/ To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message
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