From owner-freebsd-smp Mon Jul 8 13:42:58 1996 Return-Path: owner-smp Received: (from root@localhost) by freefall.freebsd.org (8.7.5/8.7.3) id NAA07160 for smp-outgoing; Mon, 8 Jul 1996 13:42:58 -0700 (PDT) Received: from uruk.org (uruk.org [198.145.95.253]) by freefall.freebsd.org (8.7.5/8.7.3) with ESMTP id NAA07146 for ; Mon, 8 Jul 1996 13:42:48 -0700 (PDT) From: erich@uruk.org Received: from loopback (loopback [127.0.0.1]) by uruk.org (8.7.4/8.7.3) with SMTP id NAA20837; Mon, 8 Jul 1996 13:42:23 -0700 (PDT) Message-Id: <199607082042.NAA20837@uruk.org> X-Authentication-Warning: uruk.org: Host loopback [127.0.0.1] didn't use HELO protocol To: Terry Lambert cc: peter@spinner.dialix.com, freebsd-smp@freebsd.org Subject: Re: Running SMP In-reply-to: Your message of "Fri, 05 Jul 1996 12:02:49 PDT." <199607051902.MAA15216@phaeton.artisoft.com> Date: Mon, 08 Jul 1996 13:42:12 -0700 Sender: owner-smp@freebsd.org X-Loop: FreeBSD.org Precedence: bulk Terry Lambert writes: > > Does anybody have documentation on the IO apic? I've got enough detail on > > the local apic, but the IO apic is a real problem. We're stuck in the > > painful "dumb" mode where all cpus get all interrupts in parallel with > > each other until we can get some details on the IO apic. (somebody > > pointed me to something from intel, but I can't find the reference anymore) In the default modes ("PIC" or "virtual wire" for different architectures, with the latter being more common as time goes on... i.e. pretty much all new designs use "virtual wire" mode), external interrupts (those normally routed via the 8259 PIC) are routed to the boot CPU only. Internal interrupts (exceptions, etc) occur on the CPU causing the event. > I thought I had pointed you to the www.intel.com page for the IO > chip, and there's now a 1.2 MP document on their site, which goes into > more detail on virtual wire (the mode I think we want to use to > anonymize which procesor has to take which interrupt). Maybe I'm confused, but the documents I'm aware of are somewhat different: -- Intel MPS 1.4 document pointer, which should point to updates as well: "http://www.intel.com/IAL/processr/mpovr.htm" -- 82489DX User's Manual AP-388, order number 292116-002, now part of the "Pentium (tm) Processors and Related Products" boot, order number 241732-002 The first document above has diagrams describing both PIC and virtual wire modes, and how they would be set up using the BIOS. The second document contains both a description of how to program the local unit and the I/O unit. For local unit programming, the list of changes in the Pentium and Pentium Pro programmer's guides are necessary for correct operation. -- Erich Stefan Boleyn \_ E-mail (preferred): Mad Genius wanna-be, CyberMuffin \__ (finger me for other stats) Web: http://www.uruk.org/~erich/ Motto: "I'll live forever or die trying" This is my home system, so I'm speaking only for myself, not for Intel.