From owner-freebsd-mips@FreeBSD.ORG Fri May 23 19:53:45 2003 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 931) id 162B937B401; Fri, 23 May 2003 19:53:45 -0700 (PDT) Date: Fri, 23 May 2003 21:53:45 -0500 From: Juli Mallett To: freebsd-mips@FreeBSD.org Message-ID: <20030523215344.A77797@FreeBSD.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i X-Title: Code Maven X-Towel: Yes X-Negacore: Yes X-Authentication-Warning: localhost: juli pwned teh intarweb Subject: Current status of FreeBSD/MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 24 May 2003 02:53:45 -0000 After many hours sitting and looking blankly at heisenbugs, printfs that would make data accesses work, etc., I finally sat down the other day and started looking for CPU errata. I found some mention of LL/SC errata that might affect my processor, and decided to replace atomic.h with a C version, and suddenly I'm getting to cpu0: messages, and beyond by some ways. I've got about two large pages of SI_SUB listing to make things go through, which at this point means fixing up NetBSD's exception, etc., code to work, and getting stuff like interrupts working, and doing a RealPmap(tm) instead of just doing everything lazily out of KSEG0. Here's what goes on, modulo debugging printfs and the like: %%% Copyright (c) 1992-2003 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights reserved. FreeBSD 5.0-CURRENT #376: Fri May 23 00:17:16 CDT 2003 jmallett@dalek:/usr/people/jmallett/mips.build/sgimips/usr/people/jmallett/p4/mips/sys/INDY MIPS R4400 CPU (0x460) Rev. 6.0 with MIPS R4010 FPC Rev. 0.0 cpu0: 16KB/16B direct-mapped L1 Instruction cache, 48 TLB entries cpu0: 16KB/16B direct-mapped write-back L1 Data cache cpu0: 0KB/128B direct-mapped write-back L2 Unified cache machine: SGI-IP22 ARCS memory = 786432 (768 KB) Loaded program memory = 1449984 (1416 KB) avail memory = 131964928 (125 MB) real memory = 134201344 (127 MB) %%% I'd like a bit of help with one thing, if anyone could help... MIPS redid their website, and in the process seems to have lost all their R4K docs. This includes all the CPU errata from that era, and I've looked at some Google-Cached HTML of these things, but that's very hard to read, and I've had mixed results with doing that. If someone has the errata PDFs and could send them to me, that would be really great. And also, if someone knows much about the LL/SC errata, I can send off a copy of the atomic.h that I'd *like* to be doing, and you can maybe tell me what changes need made :) Thanx much, juli. -- juli mallett. email: jmallett@freebsd.org; efnet: juli;