From owner-freebsd-smp  Sun Mar  9  2:51:15 2003
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From: "Vincent Bruijnes" <bruijnes@xs4all.nl>
To: freebsd-smp@freebsd.org
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Subject: supermicro+4.7-RELEASE-p7
Date: Sun, 9 Mar 2003 11:51:00 +0100
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Dear readers,

I don't see my second cpu in 'top' so I was looking in dmesg and I saw the
following :

----------------------------------------------------------------------------
---------------

Rebooting...
Copyright (c) 1992-2002 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
        The Regents of the University of California. All rights reserved.
FreeBSD 4.7-RELEASE-p7 #0: Sat Mar  8 17:14:15 CET 2003
    root@ams-ix.nlisp.nl:/usr/src/sys/compile/AMSIX
Timecounter "i8254"  frequency 1193182 Hz
CPU: Pentium III/Pentium III Xeon/Celeron (999.52-MHz 686-class CPU)
  Origin = "GenuineIntel"  Id = 0x68a  Stepping = 10

Features=0x383fbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,
CMOV,PAT,PSE36,MMX,FXSR,SSE>
real memory  = 536870912 (524288K bytes)
avail memory = 519065600 (506900K bytes)
Programming 16 pins in IOAPIC #0
IOAPIC #0 intpin 2 -> irq 0
Programming 16 pins in IOAPIC #1
FreeBSD/SMP: Multiprocessor motherboard
 cpu0 (BSP): apic id:  0, version: 0x00040011, at 0xfee00000
 io0 (APIC): apic id:  4, version: 0x000f0011, at 0xfec00000
 io1 (APIC): apic id:  5, version: 0x000f0011, at 0xfec01000
Preloaded elf kernel "kernel" at 0xc0341000.
Pentium Pro MTRR support enabled
md0: Malloc disk
Using $PIR table, 9 entries at 0xc00f5280
npx0: <math processor> on motherboard
npx0: INT 16 interface
pcib0: <ServerWorks NB6635 3.0LE host to PCI bridge> on motherboard
IOAPIC #1 intpin 15 -> irq 2
pci0: <PCI bus> on pcib0
fxp0: <Intel Pro 10/100B/100+ Ethernet> port 0xd800-0xd83f mem
0xfe900000-0xfe9fffff,0xfeade000-0xfeadefff irq 2 at device 6.0 on pci0
fxp0: Ethernet address 00:30:48:21:50:55
inphy0: <i82555 10/100 media interface> on miibus0
inphy0:  10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
isab0: <ServerWorks IB6566 PCI to ISA bridge> at device 15.0 on pci0
isa0: <ISA bus> on isab0
atapci0: <ServerWorks ROSB4 ATA33 controller> port 0xffa0-0xffaf at device
15.1 on pci0
ata0: at 0x1f0 irq 14 on atapci0
ata1: at 0x170 irq 15 on atapci0
pci0: <OHCI USB controller> at 15.2 irq 0
pcib1: <ServerWorks NB6635 3.0LE host to PCI bridge> on motherboard
pci1: <PCI bus> on pcib1
orm0: <Option ROMs> at iomem 0xc0000-0xc7fff,0xc8000-0xc8fff on isa0
fdc0: <NEC 72065B or clone> at port 0x3f0-0x3f5,0x3f7 irq 6 drq 2 on isa0
fdc0: FIFO enabled, 8 bytes threshold
fd0: <1440-KB 3.5" drive> on fdc0 drive 0
atkbdc0: <Keyboard controller (i8042)> at port 0x60,0x64 on isa0
vga0: <Generic ISA VGA> at port 0x3c0-0x3df iomem 0xa0000-0xbffff on isa0
sc0: <System console> at flags 0x100 on isa0
sc0: VGA <16 virtual consoles, flags=0x300>
APIC_IO: Testing 8254 interrupt delivery
APIC_IO: Broken MP table detected: 8254 is not connected to IOAPIC #0 intpin
2
APIC_IO: routing 8254 via 8259 and IOAPIC #0 intpin 0
ad0: 39205MB <Maxtor 6E040L0> [79656/16/63] at ata0-master UDMA33
Mounting root from ufs:/dev/ad0s1a
IP packet filtering initialized, divert disabled, rule-based forwarding
enabled, default to deny, logging disabled

----------------------------------------------------------------------------
---------------------
At this time I have 2 intel pentium 3 1 ghz , 370pin at 133 mhz fsb.
As I was trying to figure out what it could be I also ran mptable to check
something there
if there's something wong.

----------------------------------------------------------------------------
------------------------
============================================================================
===

MPTable, version 2.0.15

----------------------------------------------------------------------------
---

MP Floating Pointer Structure:

  location:                     BIOS
  physical address:             0x000ff780
  signature:                    '_MP_'
  length:                       16 bytes
  version:                      1.4
  checksum:                     0xb5
  mode:                         Virtual Wire

----------------------------------------------------------------------------
---

MP Config Table Header:

  physical address:             0x000f0cd0
  signature:                    'PCMP'
  base table length:            248
  version:                      1.4
  checksum:                     0xa3
  OEM ID:                       'AMI     '
  Product ID:                   'CNB30LE     '
  OEM table pointer:            0x00000000
  OEM table size:               0
  entry count:                  24
  local APIC address:           0xfee00000
  extended table length:        180
  extended table checksum:      7

----------------------------------------------------------------------------
---
MP Config Base Table Entries:

--
Processors:     APIC ID Version State           Family  Model   Step
Flags
                 0       0x11    BSP, usable     6       8       10
0x387fbff
--
Bus:            Bus ID  Type
                 0       PCI
                 1       PCI
                 2       ISA
--
I/O APICs:      APIC ID Version State           Address
                 4       0x11    usable          0xfec00000
                 5       0x11    usable          0xfec01000
--
I/O Ints:       Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#
                INT     active-lo       level        0   6:A          5   15
                ExtINT  active-hi        edge        2     0          4    0
                INT     active-hi        edge        2     1          4    1
                INT     active-hi        edge        2     0          4    2
                INT     active-hi        edge        2     3          4    3
                INT     active-hi        edge        2     4          4    4
                INT     active-hi        edge        2     5          4    5
                INT     active-hi        edge        2     6          4    6
                INT     active-hi        edge        2     7          4    7
                INT     active-hi        edge        2     8          4    8
                INT     active-hi        edge        2     9          4    9
                INT     active-hi        edge        2    10          4   10
                INT     active-hi        edge        2    12          4   12
                INT     active-hi        edge        2    13          4   13
                INT     active-hi        edge        2    14          4   14
                INT     active-hi        edge        2    15          4   15
--
Local Ints:     Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#
                ExtINT  active-hi        edge        2     0        255    0
                NMI     active-hi        edge        0   0:A        255    1

----------------------------------------------------------------------------
---

MP Config Extended Table Entries:

--
System Address Space
 bus ID: 0 address type: I/O address
 address base: 0xd000
 address range: 0x1000
--
System Address Space
 bus ID: 0 address type: I/O address
 address base: 0x0
 address range: 0x100
--
System Address Space
 bus ID: 0 address type: memory address
 address base: 0xfe800000
 address range: 0x300000
--
System Address Space
 bus ID: 0 address type: prefetch address
 address base: 0xfe600000
 address range: 0x100000
--
System Address Space
 bus ID: 1 address type: I/O address
 address base: 0xe000
 address range: 0x1000
--
System Address Space
 bus ID: 1 address type: memory address
 address base: 0xfeb00000
 address range: 0x100000
--
System Address Space
 bus ID: 1 address type: prefetch address
 address base: 0xfe700000
 address range: 0x100000
--
Bus Heirarchy
 bus ID: 2 bus info: 0x01 parent bus ID: 0
--
Compatibility Bus Address
 bus ID: 0 address modifier: add
 predefined range: 0x00000000
--
Compatibility Bus Address
 bus ID: 1 address modifier: subtract
 predefined range: 0x00000000
--
Compatibility Bus Address
 bus ID: 0 address modifier: subtract
 predefined range: 0x00000001
--
Compatibility Bus Address
 bus ID: 1 address modifier: subtract
 predefined range: 0x00000001

============================================================================
===

What can I try to do to this problem.. I think the problem came when I
loaded the fail-safe defaults from
the motherboard but I am not completely sure about it.. Anyone got a
suggestion for me?

Thank you very much

Vincent Bruijnes
bruijnes@xs4all.nl





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From owner-freebsd-smp  Sun Mar  9  8:19:42 2003
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Date: Sun, 9 Mar 2003 17:19:37 +0100
From: Richard Nyberg <rnyberg@it.su.se>
To: Vincent Bruijnes <bruijnes@xs4all.nl>
Cc: freebsd-smp@freebsd.org
Subject: Re: supermicro+4.7-RELEASE-p7
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On Sun, Mar 09, 2003 at 11:51:00AM +0100, Vincent Bruijnes wrote:
> Dear readers,
> 
> I don't see my second cpu in 'top' so I was looking in dmesg and I saw the
> following :

	[snip]

> What can I try to do to this problem.. I think the problem came when I
> loaded the fail-safe defaults from
> the motherboard but I am not completely sure about it.. Anyone got a
> suggestion for me?
> 

See if there is a bios option to enable the second CPU. It was probably
disabled when you chose fail safe.

	-Richard

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From owner-freebsd-smp  Mon Mar 10 10: 0: 0 2003
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From: John Baldwin <jhb@FreeBSD.org>
To: Richard Nyberg <rnyberg@it.su.se>
Subject: RE: hyperthreading randomness
Cc: freebsd-smp@freebsd.org
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On 08-Mar-2003 Richard Nyberg wrote:
> I have a Dell Precision 450 with 2 xeon CPU:s.
> The weird thing is that it randomly boots up
> with either 2 or 4 CPUs on the same 4-STABLE kernel.
> 2 more often than 4. It seems a bit unpredictable :(

Hmm, I have no idea about that one.  Hmm, it seems to be a
"feature" of the BIOS perhaps.  It seems that it may be listing
the second CPU with an APIC ID of 3 (it's second core) instead
of 2 (it's first core) in which case the HTT code sees that
something is not right and doesn't start up any extra processors.

> CPU: Intel(R) Xeon(TM) CPU 2.66GHz (2657.82-MHz 686-class CPU)
>   Origin = "GenuineIntel"  Id = 0xf27  Stepping = 7
>  
> Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUS
> H,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE>
>   Hyperthreading: 2 logical CPUs
> 
> Diff of dmesg with 2 and 4 CPUs.
> 
> --- /tmp/dmesg.old    Sat Mar  8 12:10:33 2003
> +++ /var/run/dmesg.boot       Sat Mar  8 11:57:38 2003
> @@ -19,7 +19,9 @@
>  Programming 24 pins in IOAPIC #2
>  FreeBSD/SMP: Multiprocessor motherboard
>   cpu0 (BSP): apic id:  0, version: 0x00050014, at 0xfee00000
> - cpu1 (AP):  apic id:  3, version: 0x00050014, at 0xfee00000
> + cpu1 (AP):  apic id:  1, version: 0x00050014, at 0xfee00000
> + cpu2 (AP):  apic id:  2, version: 0x00050014, at 0xfee00000
> + cpu3 (AP):  apic id:  3, version: 0x00050014, at 0xfee00000
>   io0 (APIC): apic id:  4, version: 0x00178020, at 0xfec00000
>   io1 (APIC): apic id:  5, version: 0x00178020, at 0xfec80000
>   io2 (APIC): apic id:  6, version: 0x00178020, at 0xfec80800
> @@ -103,6 +105,8 @@
>  APIC_IO: Testing 8254 interrupt delivery
>  APIC_IO: routing 8254 via IOAPIC #0 intpin 2
>  SMP: AP CPU #1 Launched!
> +SMP: AP CPU #3 Launched!
> +SMP: AP CPU #2 Launched!
>  ad0: 38146MB <WDC WD400BB-75DEA0> [77504/16/63] at ata0-master UDMA100
>  acd0: DVD-ROM <LITEON DVD-ROM LTD163> at ata1-master UDMA33
>  acd1: CD-RW <HL-DT-ST GCE-8481B> at ata1-slave UDMA33
> 
>       -Richard
> 
> To Unsubscribe: send mail to majordomo@FreeBSD.org
> with "unsubscribe freebsd-smp" in the body of the message

-- 

John Baldwin <jhb@FreeBSD.org>  <><  http://www.FreeBSD.org/~jhb/
"Power Users Use the Power to Serve!"  -  http://www.FreeBSD.org/

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From owner-freebsd-smp  Mon Mar 10 10:29:23 2003
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Date: Mon, 10 Mar 2003 19:29:18 +0100
From: Richard Nyberg <rnyberg@it.su.se>
To: John Baldwin <jhb@FreeBSD.org>
Cc: freebsd-smp@FreeBSD.org
Subject: Re: hyperthreading randomness
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On Mon, Mar 10, 2003 at 01:00:13PM -0500, John Baldwin wrote:
> 
> On 08-Mar-2003 Richard Nyberg wrote:
> > I have a Dell Precision 450 with 2 xeon CPU:s.
> > The weird thing is that it randomly boots up
> > with either 2 or 4 CPUs on the same 4-STABLE kernel.
> > 2 more often than 4. It seems a bit unpredictable :(
> 
> Hmm, I have no idea about that one.  Hmm, it seems to be a
> "feature" of the BIOS perhaps.  It seems that it may be listing
> the second CPU with an APIC ID of 3 (it's second core) instead
> of 2 (it's first core) in which case the HTT code sees that
> something is not right and doesn't start up any extra processors.
> 

I see.

Do you think this quirk will cause trouble when FreeBSD gets its
CPU info from ACPI?

Happy hacking ;)
	-Richard

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On 10-Mar-2003 Richard Nyberg wrote:
> On Mon, Mar 10, 2003 at 01:00:13PM -0500, John Baldwin wrote:
>> 
>> On 08-Mar-2003 Richard Nyberg wrote:
>> > I have a Dell Precision 450 with 2 xeon CPU:s.
>> > The weird thing is that it randomly boots up
>> > with either 2 or 4 CPUs on the same 4-STABLE kernel.
>> > 2 more often than 4. It seems a bit unpredictable :(
>> 
>> Hmm, I have no idea about that one.  Hmm, it seems to be a
>> "feature" of the BIOS perhaps.  It seems that it may be listing
>> the second CPU with an APIC ID of 3 (it's second core) instead
>> of 2 (it's first core) in which case the HTT code sees that
>> something is not right and doesn't start up any extra processors.
>> 
> 
> I see.
> 
> Do you think this quirk will cause trouble when FreeBSD gets its
> CPU info from ACPI?

No.  With ACPI the BIOS tells us all the CPUs and we don't have to
guess at the existence of any CPUs.

-- 

John Baldwin <jhb@FreeBSD.org>  <><  http://www.FreeBSD.org/~jhb/
"Power Users Use the Power to Serve!"  -  http://www.FreeBSD.org/

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From owner-freebsd-smp  Tue Mar 11  4: 0:43 2003
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To: freebsd-smp@freebsd.org
Subject: Asus PR-DLS/1030 Support (was: Supermicro P4DME-M Support?)
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> After being burned on SMP support for the Intel SE7500CW2 the boss wants to
> make sure the next board we buy doesn't have any issues. We're now looking
> at the Supermicro P4DME-M board.

Same troubles here...due to nonavailability of Supermicro boards here in Czech 
republic we are looking at Asus PR-DLS/1030 
(http://www.asus.com/products/server/srv-mb/pr-dls/overview.htm)

Does anyone use this board with two xeons?

-- 
Robert Kania   
kania@gdi.cz   ICQ:   148585231
gdi, s. r. o.  Anenska 10  Brno
www.gdi.cz     www.jazykovky.cz


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Date: Tue, 11 Mar 2003 21:30:03 +0100
From: Richard Nyberg <rnyberg@it.su.se>
To: John Baldwin <jhb@FreeBSD.org>
Cc: freebsd-smp@FreeBSD.org
Subject: Re: hyperthreading randomness
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--yrj/dFKFPuw6o+aM
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On Mon, Mar 10, 2003 at 01:00:13PM -0500, John Baldwin wrote:
> 
> On 08-Mar-2003 Richard Nyberg wrote:
> > I have a Dell Precision 450 with 2 xeon CPU:s.
> > The weird thing is that it randomly boots up
> > with either 2 or 4 CPUs on the same 4-STABLE kernel.
> > 2 more often than 4. It seems a bit unpredictable :(
> 
> Hmm, I have no idea about that one.  Hmm, it seems to be a
> "feature" of the BIOS perhaps.  It seems that it may be listing
> the second CPU with an APIC ID of 3 (it's second core) instead
> of 2 (it's first core) in which case the HTT code sees that
> something is not right and doesn't start up any extra processors.
> 
This patch works for me ;) It allows the physical CPUs APIC ID to
be either the lowest (as is currently assumed) or the highest
number in the range of APIC IDs for the logical cores.

Happy hacking!
	-Richard

--yrj/dFKFPuw6o+aM
Content-Type: text/plain; charset=us-ascii
Content-Disposition: attachment; filename="hyperquirk.diff"

--- sys/i386/i386/orig-mp_machdep.c	Tue Mar 11 20:46:06 2003
+++ sys/i386/i386/mp_machdep.c	Tue Mar 11 21:12:02 2003
@@ -973,10 +973,18 @@
 				 * enumerate the logical CPUs.
 				 */
 				proc.apic_id = ((proc_entry_ptr)position)->apic_id;
-				for (i = 1; i < logical_cpus; i++) {
-					proc.apic_id++;
-					(void)processor_entry(&proc, cpu);
-					cpu++;
+				if (proc.apic_id % logical_cpus == 0) {
+					for (i = 1; i < logical_cpus; i++) {
+						proc.apic_id++;
+						(void)processor_entry(&proc, cpu);
+						cpu++;
+					}
+				} else {
+					for (i = 1; i < logical_cpus; i++) {
+						proc.apic_id--;
+						(void)processor_entry(&proc, cpu);
+						cpu++;
+					}
 				}
 			}
 			break;
@@ -1020,8 +1028,9 @@
  * system have the same number of logical CPUs.
  *
  * XXX: We assume that APIC ID's are allocated such that
- * the APIC ID's for a physical processor are aligned
- * with the number of logical CPU's in the processor.
+ * the APIC ID's for a physical processor are either
+ * the lowest or the highest number in the group of
+ * logical cores.
  */
 static void
 mptable_hyperthread_fixup(u_int id_mask)
@@ -1044,12 +1053,17 @@
 	for (id = 0; id <= MAXCPU; id++) {
 		if ((id_mask & 1 << id) == 0)
 			continue;
-		/* First, make sure we are on a logical_cpus boundary. */
-		if (id % logical_cpus != 0)
-			return;
-		for (i = id + 1; i < id + logical_cpus; i++)
-			if ((id_mask & 1 << i) != 0)
-				return;
+		/* If we are on a logical_cpus boundary look upwards,
+		 * otherwise look downwards. */
+		if (id % logical_cpus == 0) {
+			for (i = id + 1; i < id + logical_cpus; i++)
+				if ((id_mask & 1 << i) != 0)
+					return;
+		} else {
+			for (i = id - 1; i < id - logical_cpus; i--)
+				if ((id_mask & 1 << i) != 0)
+					return;
+		}
 	}
 
 	/*

--yrj/dFKFPuw6o+aM--

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From owner-freebsd-smp  Tue Mar 11 12:36:44 2003
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From: John Baldwin <jhb@FreeBSD.org>
To: Richard Nyberg <rnyberg@it.su.se>
Subject: Re: hyperthreading randomness
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On 11-Mar-2003 Richard Nyberg wrote:
> On Mon, Mar 10, 2003 at 01:00:13PM -0500, John Baldwin wrote:
>> 
>> On 08-Mar-2003 Richard Nyberg wrote:
>> > I have a Dell Precision 450 with 2 xeon CPU:s.
>> > The weird thing is that it randomly boots up
>> > with either 2 or 4 CPUs on the same 4-STABLE kernel.
>> > 2 more often than 4. It seems a bit unpredictable :(
>> 
>> Hmm, I have no idea about that one.  Hmm, it seems to be a
>> "feature" of the BIOS perhaps.  It seems that it may be listing
>> the second CPU with an APIC ID of 3 (it's second core) instead
>> of 2 (it's first core) in which case the HTT code sees that
>> something is not right and doesn't start up any extra processors.
>> 
> This patch works for me ;) It allows the physical CPUs APIC ID to
> be either the lowest (as is currently assumed) or the highest
> number in the range of APIC IDs for the logical cores.

I'm not sure it's entirely safe since it doesn't verify that you
are at the top of a boundary when it looks downwards.  Really
though, the current stuff is more of a quick hack to get it mostly
working for now.  When the ACPI stuff gets done it won't really
matter anymore.  I'd like to keep the current hack very conservative
since I'm making assumptions that I am not completely sure I am
allowed to make and I'd like to keep the number and scope of such
assumptions as small as possible.

-- 

John Baldwin <jhb@FreeBSD.org>  <><  http://www.FreeBSD.org/~jhb/
"Power Users Use the Power to Serve!"  -  http://www.FreeBSD.org/

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From owner-freebsd-smp  Tue Mar 11 23:51:55 2003
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Date: Wed, 12 Mar 2003 08:51:51 +0100
From: Richard Nyberg <rnyberg@it.su.se>
To: John Baldwin <jhb@FreeBSD.org>
Cc: freebsd-smp@FreeBSD.org
Subject: Re: hyperthreading randomness
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On Tue, Mar 11, 2003 at 03:36:57PM -0500, John Baldwin wrote:
> I'm not sure it's entirely safe since it doesn't verify that you
> are at the top of a boundary when it looks downwards.

Yes I know. Sorry about that :(
Of course, I had to realize this just before going to bed ;)

> Really
> though, the current stuff is more of a quick hack to get it mostly
> working for now.  When the ACPI stuff gets done it won't really
> matter anymore.  I'd like to keep the current hack very conservative
> since I'm making assumptions that I am not completely sure I am
> allowed to make and I'd like to keep the number and scope of such
> assumptions as small as possible.

The patch was intented as a quick hack for people with
the same "feature" as me ;) Anyway, if there really are
anyone who needs it, you can get a revised patch at
http://people.su.se/~rnyberg/bsd_patches/hyperquirk.diff.

	-Richard

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From owner-freebsd-smp  Wed Mar 12  3:19:32 2003
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X-Mailer: exmh version 2.2 06/23/2000 with version: MH 6.8.4 #1[UCI]
To: freebsd-smp@freebsd.org
Subject: Re: SMP hang on boot in RELENG_4_7 on Iwill DP533 board
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	I'm running dual Xeon processors on an Iwill DP533 board.
This board has an E7505 MCH chipset from Intel, using the ICH4 I/O hub
and an 82870P2 PCI-X controller.  This is the only motherboard on
the market of which I'm aware which both supports dual Xeon
processors, and also has an AGP slot.

	Earlier, I reported what is by now a well-known problem with
4.7, namely, SMP doesn't work with this board, apparently because it
has a relative of the 7500 chipset.  I understand there's a whole long
history about Clearwater vs. Stillwater boards, about which I don't
know very much, except that one works, the other doesn't.  Apparently
the 7505 chipset belongs to the "doesn't work" category.

	I'm here to report success.  Thanks to changes recently checked
in to the RELENG_4 branch, which I cvsuped tonight, the APIC_IO problem
that caused a boot hang is now resolved.  The second CPU is started.

	There was a problem remaining, however: disk drive write timeouts,
and watchdog timeouts on the em0 ethernet adapter.  Apparently there is
remaining badness in the interrupt configuration. 

	However, thanks to a message from Nicolas Kowalski which I found
in the archives (THANK YOU NICOLAS!), this problem has also been resolved.
In -STABLE (== RELENG_4), it is necessary to undefine the symbol
GRAB_LOPRIO in the file "smptests.h" and rebuild an SMP kernel.  This
kernel appears to work correctly with the Iwill DP533 motherboard and
its 7505 chipset, allowing both processors to run without generating
I/O errors.

	Hallelujah.  Thanks, guys.

Mike O'Brien
P.S. I used to push FreeBSD regularly back when I had a column in
_Server/Workstation Expert_ (nee _Sun Expert_).  I'd do it again, if
the magazine hadn't folded.  :-P


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From owner-freebsd-smp  Wed Mar 12  3:56:26 2003
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Date: Wed, 12 Mar 2003 12:56:21 +0100
From: Robert Barten <robert@barok.de>
To: freebsd-smp@freebsd.org
Subject: K7D Master L mit Adaptec RAID 2100S
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Hello readers,

it's not a FreeBSD question but I hope to get
help/suggestions to solve this problem because you are
working everyday with SMP. This email was sent to MSI after
talking at lot of times with Adaptec and MSI. They sent me a
new BIOS, v1.8b1, no improvement. It seems to me that there
is a big DMA conflict which doesn't allow the RAID BIOS to
boot. I consider to buy ASUS A7M 266D ... what to to with
"the old one"? Does anyone uses the K7D Master?

----- Forwarded message from Robert Barten <robert@barok.de> -----

Dear Sirs,

our problem:
System hangs when trying to start RAID BIOS.

our configuration:
K7D Master L (everything onboard is deactivated!)
AMD-760 MPX Chipset
MB BIOS v1.8b1 (also tested v1.3, v1.5 and v1.6)
2 GB reg. DDR RAM (works)
2 AMD Athlon MP 2200+ (work)
AGP ATI XpertWork 8MB (works)
RAID Controller Adaptec 2100S with up-to-date firmware and BIOS
(Controller works fine on ASUS Boards)
4 SCSI HDD (work)
No OS yet, will be FreeBSD when the system boots finally.
recommended EnerMax Power Supply 3,3V/32A and 5V/32A

I can't even boot a floppy disk without deactivating the RAID Controller.

----- End forwarded message -----

Thanks for your efforts in advance,
Robert
-- 
CONCORDIA DOMI FORIS PAX

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From owner-freebsd-smp  Wed Mar 12  4:28:57 2003
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Subject: Question about number of CPUs
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	I read over the recent thread about the number of CPUs
detected and reported at boot time.  If I followed this correctly,
dual Xeon processors should be detected as four CPUs due to
hyperthreading, but one person reported that only two were being
detected because the APIC IDs of the two CPUs were expected to be 0
and 2, but were coming back as 0 and 3 instead.  (Presumably the
other pair of CPUs would report ids of 1 and 3.)

	I have the opposite problem.  My dual Xeons are reporting
APIC IDs of 0 and 1.  Yes, hyperthreading is turned on in the BIOS;
I checked.  'dmesg' output follows.

	Any ideas or suggestions?

Copyright (c) 1992-2003 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
	The Regents of the University of California. All rights reserved.
FreeBSD 4.8-RC #5: Wed Mar 12 02:47:28 PST 2003
    root@.we1.client2.attbi.com:/usr/obj/usr/src/sys/GENERIC
Timecounter "i8254"  frequency 1193182 Hz
CPU: Intel(R) Xeon(TM) CPU 2.40GHz (2399.33-MHz 686-class CPU)
  Origin = "GenuineIntel"  Id = 0xf27  Stepping = 7
  Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE>
  Hyperthreading: 2 logical CPUs
real memory  = 1073676288 (1048512K bytes)
config> di bt0
config> di adv0
config> q
avail memory = 1039396864 (1015036K bytes)
Changing APIC ID for IO APIC #0 from 0 to 4 on chip
Programming 24 pins in IOAPIC #0
IOAPIC #0 intpin 2 -> irq 0
Programming 24 pins in IOAPIC #1
Programming 24 pins in IOAPIC #2
FreeBSD/SMP: Multiprocessor motherboard
 cpu0 (BSP): apic id:  0, version: 0x00050014, at 0xfee00000
 cpu1 (AP):  apic id:  1, version: 0x00050014, at 0xfee00000
 io0 (APIC): apic id:  4, version: 0x00178020, at 0xfec00000
 io1 (APIC): apic id:  5, version: 0x00178020, at 0xfec80000
 io2 (APIC): apic id:  6, version: 0x00178020, at 0xfec80400
Preloaded elf kernel "kernel" at 0xc0583000.
Preloaded userconfig_script "/boot/kernel.conf" at 0xc058309c.
Pentium Pro MTRR support enabled
md0: Malloc disk
Using $PIR table, 13 entries at 0xc00fde90
npx0: <math processor> on motherboard
npx0: INT 16 interface
pcib0: <Host to PCI bridge> on motherboard
IOAPIC #0 intpin 16 -> irq 2
IOAPIC #0 intpin 19 -> irq 5
IOAPIC #0 intpin 18 -> irq 9
IOAPIC #0 intpin 23 -> irq 10
IOAPIC #0 intpin 17 -> irq 11
pci0: <PCI bus> on pcib0
agp0: <Intel Generic host to PCI bridge> mem 0xd8000000-0xdfffffff at device 0.0 on pci0
pci0: <unknown card> (vendor=0x8086, dev=0x2551) at 0.1
pcib1: <PCI to PCI bridge (vendor=8086 device=2552)> mem 0xe0000000-0xe7ffffff at device 1.0 on pci0
pci1: <PCI bus> on pcib1
pci1: <ATI model 4e44 graphics accelerator> at 0.0 irq 2
pci1: <ATI model 4e64 graphics accelerator> at 0.1
pcib2: <PCI to PCI bridge (vendor=8086 device=2553)> at device 2.0 on pci0
pci2: <PCI bus> on pcib2
pci2: <unknown card> (vendor=0x8086, dev=0x1461) at 28.0
pcib3: <PCI to PCI bridge (vendor=8086 device=1460)> at device 29.0 on pci2
pci3: <PCI bus> on pcib3
pci2: <unknown card> (vendor=0x8086, dev=0x1461) at 30.0
pcib4: <PCI to PCI bridge (vendor=8086 device=1460)> at device 31.0 on pci2
pci4: <PCI bus> on pcib4
uhci0: <Intel 82801DB (ICH4) USB controller USB-A> port 0xb800-0xb81f irq 2 at device 29.0 on pci0
usb0: <Intel 82801DB (ICH4) USB controller USB-A> on uhci0
usb0: USB revision 1.0
uhub0: Intel UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub0: 2 ports with 2 removable, self powered
uhci1: <Intel 82801DB (ICH4) USB controller USB-B> port 0xb000-0xb01f irq 5 at device 29.1 on pci0
usb1: <Intel 82801DB (ICH4) USB controller USB-B> on uhci1
usb1: USB revision 1.0
uhub1: Intel UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub1: 2 ports with 2 removable, self powered
uhci2: <Intel 82801DB (ICH4) USB controller USB-C> port 0xb400-0xb41f irq 9 at device 29.2 on pci0
usb2: <Intel 82801DB (ICH4) USB controller USB-C> on uhci2
usb2: USB revision 1.0
uhub2: Intel UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub2: 2 ports with 2 removable, self powered
pci0: <USB controller> at 29.7 irq 10
pcib5: <Intel 82801BA/BAM (ICH2) Hub to PCI bridge> at device 30.0 on pci0
IOAPIC #0 intpin 20 -> irq 16
IOAPIC #0 intpin 21 -> irq 17
pci5: <PCI bus> on pcib5
pci5: <unknown card> (vendor=0x104c, dev=0x8023) at 3.0 irq 16
em0: <Intel(R) PRO/1000 Network Connection, Version - 1.4.10> port 0xa000-0xa03f mem 0xf8200000-0xf821ffff irq 5 at device 4.0 on pci5
em0:  Speed:100 Mbps  Duplex:Full
pcm0: <Creative EMU10K1> port 0xa400-0xa41f irq 17 at device 5.0 on pci5
pcm0: <unknown ac97 codec> (id=0x454d4328)
isab0: <PCI to ISA bridge (vendor=8086 device=24c0)> at device 31.0 on pci0
isa0: <ISA bus> on isab0
atapci0: <Intel ICH4 ATA100 controller> port 0xf000-0xf00f,0-0x3,0-0x7,0-0x3,0-0x7 irq 2 at device 31.1 on pci0
ata0: at 0x1f0 irq 14 on atapci0
ata1: at 0x170 irq 15 on atapci0
pci0: <unknown card> (vendor=0x8086, dev=0x24c3) at 31.3 irq 11
orm0: <Option ROMs> at iomem 0xc0000-0xccfff,0xd0000-0xd7fff on isa0
fdc0: <NEC 72065B or clone> at port 0x3f0-0x3f5,0x3f7 irq 6 drq 2 on isa0
fdc0: FIFO enabled, 8 bytes threshold
fd0: <1440-KB 3.5" drive> on fdc0 drive 0
atkbdc0: <Keyboard controller (i8042)> at port 0x60,0x64 on isa0
atkbd0: <AT Keyboard> flags 0x1 irq 1 on atkbdc0
kbd0 at atkbd0
psm0: <PS/2 Mouse> irq 12 on atkbdc0
psm0: model MouseMan+, device ID 0
vga0: <Generic ISA VGA> at port 0x3c0-0x3df iomem 0xa0000-0xbffff on isa0
sc0: <System console> at flags 0x100 on isa0
sc0: VGA <16 virtual consoles, flags=0x300>
sio0 at port 0x3f8-0x3ff irq 4 flags 0x10 on isa0
sio0: type 16550A
sio1 at port 0x2f8-0x2ff irq 3 on isa0
sio1: type 16550A
ppc0: <Parallel port> at port 0x378-0x37f irq 7 on isa0
ppc0: SMC-like chipset (ECP/EPP/PS2/NIBBLE) in COMPATIBLE mode
ppc0: FIFO with 16/16/9 bytes threshold
plip0: <PLIP network interface> on ppbus0
lpt0: <Printer> on ppbus0
lpt0: Interrupt-driven port
ppi0: <Parallel I/O> on ppbus0
APIC_IO: Testing 8254 interrupt delivery
APIC_IO: routing 8254 via IOAPIC #0 intpin 2
SMP: AP CPU #1 Launched!
ad0: 76319MB <WDC WD800JB-00CRA1> [155061/16/63] at ata0-master UDMA100
ad1: 76319MB <WDC WD800JB-00CRA1> [155061/16/63] at ata0-slave UDMA100
acd0: DVD-R <SONY DVD RW DRU-500A> at ata1-master PIO4
Mounting root from ufs:/dev/ad1s1a



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From owner-freebsd-smp  Wed Mar 12  5: 3:11 2003
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To: freebsd-smp@freebsd.org
Subject: Re: Question about number of CPUs 
In-reply-to: Your message of "Wed, 12 Mar 2003 04:28:14 PST."
             <200303121228.h2CCSEK01127@c-24-130-253-104.we.client2.attbi.com> 
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From: "Mike O'Brien" <obrien@leonardo.net>
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	Ok, I've spotted what other people probably spotted immediately:
the most likely explanation is that only one of the two Xeons on the
motherboard is firing, and both its cores are being detected.  I'll go
troubleshoot.

Mike O'Brien


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From owner-freebsd-smp  Wed Mar 12  7:48:53 2003
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From: John Baldwin <jhb@FreeBSD.org>
To: "Mike O'Brien" <obrien@leonardo.net>
Subject: Re: Question about number of CPUs
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On 12-Mar-2003 Mike O'Brien wrote:
>       Ok, I've spotted what other people probably spotted immediately:
> the most likely explanation is that only one of the two Xeons on the
> motherboard is firing, and both its cores are being detected.  I'll go
> troubleshoot.

Not necessarily.  Does mptable list both CPU's?  In that case, you are
just going to have to wait for ACPI SMP support for hyperthreading to
work.

-- 

John Baldwin <jhb@FreeBSD.org>  <><  http://www.FreeBSD.org/~jhb/
"Power Users Use the Power to Serve!"  -  http://www.FreeBSD.org/

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From owner-freebsd-smp  Wed Mar 12 12:13:20 2003
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> Not necessarily.  Does mptable list both CPU's?

Here is the output of 'mptable -verbose'.  As you can see, it lists
two CPUs, but I don't know if those are separate physical processors,
or twin cores on just one of them.


===============================================================================

MPTable, version 2.0.15

 looking for EBDA pointer @ 0x040e, found, searching EBDA @ 0x0009fc00
 searching CMOS 'top of mem' @ 0x0009f800 (638K)
 searching default 'top of mem' @ 0x0009fc00 (639K)
 searching BIOS @ 0x000f0000

 MP FPS found in BIOS @ physical addr: 0x000f56d0

-------------------------------------------------------------------------------

MP Floating Pointer Structure:

  location:			BIOS
  physical address:		0x000f56d0
  signature:			'_MP_'
  length:			16 bytes
  version:			1.4
  checksum:			0x7d
  mode:				Virtual Wire

-------------------------------------------------------------------------------

MP Config Table Header:

  physical address:		0x000f1400
  signature:			'PCMP'
  base table length:		356
  version:			1.4
  checksum:			0x03
  OEM ID:			'OEM00000'
  Product ID:			'PROD00000000'
  OEM table pointer:		0x00000000
  OEM table size:		0
  entry count:			36
  local APIC address:		0xfee00000
  extended table length:	0
  extended table checksum:	0

-------------------------------------------------------------------------------

MP Config Base Table Entries:

--
Processors:	APIC ID	Version	State		Family	Model	Step	Flags
		 0	 0x11	 BSP, usable	 15	 2	 7	 0xfbff
		 1	 0x11	 AP, usable	 15	 2	 7	 0xfbff
--
Bus:		Bus ID	Type
		 0	 PCI   
		 1	 PCI   
		 2	 PCI   
		 3	 PCI   
		 4	 PCI   
		 5	 PCI   
		 6	 ISA   
--
I/O APICs:	APIC ID	Version	State		Address
		 4	 0x11	 usable		 0xfec00000
		 5	 0x11	 usable		 0xfec80000
		 6	 0x11	 usable		 0xfec80400
--
I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
		INT	active-lo       level	     0	31:B	      4	  17
		INT	active-lo       level	     0	29:B	      4	  19
		INT	active-lo       level	     0	29:C	      4	  18
		INT	active-lo       level	     0	29:D	      4	  23
		INT	active-lo       level	     0	29:A	      4	  16
		INT	active-lo       level	     5	 3:A	      4	  20
		INT	active-lo       level	     5	 5:A	      4	  21
		INT	active-lo       level	     1	 0:A	      4	  16
		INT	active-lo       level	     5	 4:A	      4	  19
		INT	active-lo       level	     0	31:A	      4	  16
		ExtINT	 conforms    conforms	     6	   0	      4	   0
		INT	 conforms    conforms	     6	   1	      4	   1
		INT	 conforms    conforms	     6	   0	      4	   2
		INT	 conforms    conforms	     6	   3	      4	   3
		INT	 conforms    conforms	     6	   4	      4	   4
		INT	 conforms    conforms	     6	   6	      4	   6
		INT	 conforms    conforms	     6	   7	      4	   7
		INT	active-hi        edge	     6	   8	      4	   8
		INT	 conforms    conforms	     6	  12	      4	  12
		INT	 conforms    conforms	     6	  13	      4	  13
		INT	 conforms    conforms	     6	  14	      4	  14
		INT	 conforms    conforms	     6	  15	      4	  15
--
Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
		ExtINT	 conforms    conforms	     0	 0:A	    255	   0
		NMI	 conforms    conforms	     0	 0:A	    255	   1

===============================================================================




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From owner-freebsd-smp  Wed Mar 12 12:41:57 2003
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From: John Baldwin <jhb@FreeBSD.org>
To: "Mike O'Brien" <obrien@leonardo.net>
Subject: Re: Question about number of CPUs
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On 12-Mar-2003 Mike O'Brien wrote:
>> Not necessarily.  Does mptable list both CPU's?
> 
> Here is the output of 'mptable -verbose'.  As you can see, it lists
> two CPUs, but I don't know if those are separate physical processors,
> or twin cores on just one of them.

Probably it is the separate CPU's.  If you want, you can try checking out
the sources to acpidump, compiling it and running it.  acpidump can list
the output of the MADT table which will list all CPUs and their APIC IDs.

-- 

John Baldwin <jhb@FreeBSD.org>  <><  http://www.FreeBSD.org/~jhb/
"Power Users Use the Power to Serve!"  -  http://www.FreeBSD.org/

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From owner-freebsd-smp  Wed Mar 12 14:45: 9 2003
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From: Gregor Bittel <Gregor.Bittel@GMX.de>
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To: freebsd-smp@FreeBSD.ORG, freebsd-questions@freebsd.org
Subject: SMP-Mainboards-Listing.
Date: Wed, 12 Mar 2003 23:41:25 +0100
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Hi,
two years are gone, since I decided to make a list
of running SMP-Mainboards with FreeBSD.
At this time (2 years ago) I wanted to buy a new SMP-Board,
but I haven't done this - I'm quite happy now with my
good old Pentium and FreeBSD-4.7R.

But - I need much more informations, which boards are
running, a dmesg-output and mptable-output.
(Currently are 96 boards of 377 known boards listed...)

This site/listing is still under development, and is at
http://www.bnv-bamberg.de/home/ba3294/smp/index.htm
available.

And not to forget, I wish to say thank you to all people, which
helped me with this site and their support.

-Gregor.

-- 
Gregor.Bittel@GMX.de
This is the first time posted to questions (I'm not subscribed there)
and the 2nd posting to the smp-mailinglist (subscribed there).

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From owner-freebsd-smp  Thu Mar 13  8:17:38 2003
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From: John Baldwin <jhb@FreeBSD.org>
To: "Mike O'Brien" <obrien@leonardo.net>
Subject: Re: Question about number of CPUs
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On 13-Mar-2003 Mike O'Brien wrote:
>       Here is the output of acpidump on that machine.  It does list four
> CPUs, but I can't tell from this table which APIC IDs are associated with
> which physical processors.  The two processors that are detected have
> APIC IDs of 0 and 1.  If these are separate processors, I figure I should
> just wait for the correct APIC code to appear, since hyperthreading will
> only improve performance by about 30%, if I remember correctly.  But if
> these are two cores on the same physical processor then I'm planning to
> crash around in mp_machdep.c and do whatever I have to do to get the
> second physical processor on this particular machine to show up.

Humm, it does seem that your BIOS is broken and is reporting the two cores
on CPU 0 in the mptable. :-/  The part at the end here lists the 4 cpus
and their APIC IDs as 0, 1, 2, and 3.  According to the IA-32 docs I've
read, when HTT is used, the APIC ID's of logical cores within a physical
CPU are consecutive, i.e. x then x+1.

> /*
> APIC: Length=156, Revision=1, Checksum=90,
>       OEMID=IntelR, OEM Table ID=AWRDACPI, OEM Revision=0x42302e31,
>       Creator ID=AWRD, Creator Revision=0x0
>  */
> /*
>       Local APIC ADDR=0xfee00000
>       Flags={PC-AT}

This tells us the physical address that the local APIC resides at.  Well
the address that it decodes and that this system has a PC-AT compat mode
meaning it has 8259A's that can do interrupts.

>       Type=Local APIC
>       ACPI CPU=0
>       Flags={ENABLED}
>       APIC ID=0
> 
>       Type=Local APIC
>       ACPI CPU=1
>       Flags={ENABLED}
>       APIC ID=1
> 
>       Type=Local APIC
>       ACPI CPU=2
>       Flags={ENABLED}
>       APIC ID=2
> 
>       Type=Local APIC
>       ACPI CPU=3
>       Flags={ENABLED}
>       APIC ID=3

These are your four CPU's with APIC IDs 0, 1, 2, and 3.  BTW, if you
disable HTT in your BIOS, then APIC IDs 1 and 3 should become
DISABLED instead of ENABLED.  Or rather, they may have a flags of
{}.  (Lack of ENABLED)

>       Type=IO APIC
>       APIC ID=4
>       INT BASE=0
>       ADDR=0xfec00000
> 
>       Type=IO APIC
>       APIC ID=5
>       INT BASE=24
>       ADDR=0xfec80000
> 
>       Type=IO APIC
>       APIC ID=6
>       INT BASE=48
>       ADDR=0xfec80400

These are your IO APICs along with the addresses they decode for
access to their registers and the base global interrupt number for
their interrupt pins.  I.e., pin 2 on IO APIC 1 (ID 5) would have
a global interrupt number of 2 + 24 = 26.  Part of my ACPI work is
to rework our current APIC code to use a similar global interrupt
number scheme with the mptable and IO APICs and to then fix our
PCI interrupt routing code for mptable SMP.

>       Type=INT Override
>       BUS=0
>       IRQ=0
>       INTR=2
>       Flags={Polarity=conforming, Trigger=conforming}
> 
>       Type=INT Override
>       BUS=0
>       IRQ=9
>       INTR=9
>       Flags={Polarity=active-hi, Trigger=level}

These are the normal pin overrides on IO APIC 0 (IRQ 0 is
mapped to pin 2 because pin 0 is used for the mixed mode
pass through and the 8259's don't have a real IRQ 2).  IRQ
9 mapping to pin 9 seems rather normal except that it is
level triggered instead of edge triggered.
 
>       Type=Local NMI
>       ACPI CPU=0
>       LINT Pin=1
>       Flags={Polarity=active-hi, Trigger=edge}
> 
>       Type=Local NMI
>       ACPI CPU=0
>       LINT Pin=1
>       Flags={Polarity=active-hi, Trigger=edge}
> 
>       Type=Local NMI
>       ACPI CPU=0
>       LINT Pin=1
>       Flags={Polarity=active-hi, Trigger=edge}
> 
>       Type=Local NMI
>       ACPI CPU=0
>       LINT Pin=1
>       Flags={Polarity=active-hi, Trigger=edge}

This says that the local interrupt pin 1 on each CPU
is wired up to an NMI.

>  */

-- 

John Baldwin <jhb@FreeBSD.org>  <><  http://www.FreeBSD.org/~jhb/
"Power Users Use the Power to Serve!"  -  http://www.FreeBSD.org/

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From owner-freebsd-smp  Thu Mar 13 10:10:12 2003
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Date: Thu, 13 Mar 2003 15:12:47 -0300
From: Ali Faiez Taha <aftaha@cirp.usp.br>
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Dear Sir. 

I'm  trying to use one Intel Motherboard, MODEL: SE7500CW2, with SMP on
the kernel.
The FreeBSD version is 4.8 RC 
The processors are 2 Xeon 2.4 GHz

BIOS version : 1.17

When I compile the Kernel with the options:

options         SMP                     # Symmetric MultiProcessor
Kernel
options         APIC_IO                 # Symmetric (APIC) I/O

and reboot, the CPU crash.

The partial boot messages is :
--------------------------------------------------------------
Hyperthreading: 2 logical CPUs
Programming 24 pins in IOAPIC#0
IOAPIC #0 intpin2 -> irq 0

Programming 24 pins in IOAPIC # 1
Programming 24 pins in IOAPIC # 2

AP # 1 (PHY#1) failed !

panic (y/n) [y]  

If I press y the answer is :

bye-bye
mp_lock=00000001, cpuid=0,lapic.id=00000000

Uptime:0s

Here, the CPU is locked.
-----------------------------------------------------------

What I need to do to this CPU run with SMP ?
There are more options to put on the kernel ?

Thanks.

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From owner-freebsd-smp  Thu Mar 13 10:20:57 2003
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From: John Baldwin <jhb@FreeBSD.org>
To: Ali Faiez Taha <aftaha@cirp.usp.br>
Subject: RE: SMP on the Kernel
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On 13-Mar-2003 Ali Faiez Taha wrote:
> Dear Sir. 
> 
> I'm  trying to use one Intel Motherboard, MODEL: SE7500CW2, with SMP on
> the kernel.
> The FreeBSD version is 4.8 RC 
> The processors are 2 Xeon 2.4 GHz

Unfortunately FreeBSD does not currently work with SMP on this motherboard.

> BIOS version : 1.17
> 
> When I compile the Kernel with the options:
> 
> options         SMP                     # Symmetric MultiProcessor
> Kernel
> options         APIC_IO                 # Symmetric (APIC) I/O
> 
> and reboot, the CPU crash.
> 
> The partial boot messages is :
> --------------------------------------------------------------
> Hyperthreading: 2 logical CPUs
> Programming 24 pins in IOAPIC#0
> IOAPIC #0 intpin2 -> irq 0
> 
> Programming 24 pins in IOAPIC # 1
> Programming 24 pins in IOAPIC # 2
> 
> AP # 1 (PHY#1) failed !
> 
> panic (y/n) [y]  
> 
> If I press y the answer is :
> 
> bye-bye
> mp_lock=00000001, cpuid=0,lapic.id=00000000
> 
> Uptime:0s
> 
> Here, the CPU is locked.
> -----------------------------------------------------------
> 
> What I need to do to this CPU run with SMP ?
> There are more options to put on the kernel ?
> 
> Thanks.
> 
> To Unsubscribe: send mail to majordomo@FreeBSD.org
> with "unsubscribe freebsd-smp" in the body of the message

-- 

John Baldwin <jhb@FreeBSD.org>  <><  http://www.FreeBSD.org/~jhb/
"Power Users Use the Power to Serve!"  -  http://www.FreeBSD.org/

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From owner-freebsd-smp  Thu Mar 13 13:38:56 2003
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From owner-freebsd-smp  Thu Mar 13 13:52:34 2003
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Date: Thu, 13 Mar 2003 13:52:32 -0800 (PST)
From: Jorge Aldana <jorge@salk.edu>
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To: freebsd-smp@freebsd.org
Subject: SMP and Hyperthreading Info
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Hello SMP Group,

I'd like to get the low down on how FreeBSD is dealing with hyperthreading, as
in docs or specs? Or do I need to dig into the code?

Thanks,

Jorge


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From owner-freebsd-smp  Thu Mar 13 14:55:22 2003
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From: John Baldwin <jhb@FreeBSD.org>
To: Jorge Aldana <jorge@salk.edu>
Subject: RE: SMP and Hyperthreading Info
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On 13-Mar-2003 Jorge Aldana wrote:
> Hello SMP Group,
> 
> I'd like to get the low down on how FreeBSD is dealing with hyperthreading, as
> in docs or specs? Or do I need to dig into the code?

Right now we just spin up the logical CPU's as if they were extra CPUs.
There isn't any special treatment in the schedule for logical CPUs.

-- 

John Baldwin <jhb@FreeBSD.org>  <><  http://www.FreeBSD.org/~jhb/
"Power Users Use the Power to Serve!"  -  http://www.FreeBSD.org/

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From owner-freebsd-smp  Fri Mar 14  2: 3: 2 2003
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Date: Fri, 14 Mar 2003 11:02:57 +0100 (CET)
From: Harti Brandt <brandt@fokus.fraunhofer.de>
To: smp@freebsd.org
Subject: information about locking requirements
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Hi,

having red through the smp pages and papers and the smp mailing list
archive and seeing the current SMP state of the network interface drivers
does it make sense to do the following:

1. Gradually append to (some of) the section 9 man pages a new section
"locking requirements" (or something like this) that decribes, what
requirements with regard to locks a given interface has. In the recent
discussion about the M_ flags the was some arguing about "we need to teach
the programmer" and I think it would really help. For example, neither the
malloc(9) not the mbuf(9) page tells me anything about whether I'm allowed
or not to hold any locks while calling the interface and whether it uses
Giant or not. The only information if have found so far is at the end of
mutex(9) that lists copyout() and Co. Do you think this makes sense?
If yes, I would try to craft a couple of initial sentences for some of the
man pages.

2. I would like to gradually collect some of the assumptions that an
interface driver may make (with regard to locking) and some requirements
and put them somewhere (after getting comments on the net and smp lists).
This will probably help people later on so they don't have to read through
zillions of old mails. What is the best place to put such information to?
A man page? The SMP project page?

harti
-- 
harti brandt,
http://www.fokus.fraunhofer.de/research/cc/cats/employees/hartmut.brandt/private
brandt@fokus.fraunhofer.de, harti@freebsd.org

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From owner-freebsd-smp  Fri Mar 14  2:11:32 2003
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Subject: Re: SMP and Hyperthreading Info
From: Nicolas Kowalski <Nicolas.Kowalski@imag.fr>
Date: Fri, 14 Mar 2003 11:11:26 +0100
In-Reply-To: <XFMail.20030313175533.jhb@FreeBSD.org> (John Baldwin's message
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John Baldwin <jhb@FreeBSD.ORG> writes:

> Right now we just spin up the logical CPU's as if they were extra CPUs.
> There isn't any special treatment in the schedule for logical CPUs.

Just a question : is there a way (kernel option ?) to disable
Hyperthreading, so that FreeBSD only uses two physical CPUs ?  

I am running FreeBSD 4.8-RC on a Compaq ML370 dual-Xeon, and disabling
HT in the BIOS has no effect.

Thanks in advance.

-- 
Nicolas


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From owner-freebsd-smp  Fri Mar 14  2:46:19 2003
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Subject: Re: SMP and Hyperthreading Info
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> Just a question : is there a way (kernel option ?) to disable
> Hyperthreading, so that FreeBSD only uses two physical CPUs ?
>
> I am running FreeBSD 4.8-RC on a Compaq ML370 dual-Xeon, and disabling
> HT in the BIOS has no effect.
>
Not yet, but there´s supposed to be one soon.

Meanwhile, source is your friend.

Pete


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From: John Baldwin <jhb@FreeBSD.org>
To: Nicolas Kowalski <Nicolas.Kowalski@imag.fr>
Subject: Re: SMP and Hyperthreading Info
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On 14-Mar-2003 Nicolas Kowalski wrote:
> John Baldwin <jhb@FreeBSD.ORG> writes:
> 
>> Right now we just spin up the logical CPU's as if they were extra CPUs.
>> There isn't any special treatment in the schedule for logical CPUs.
> 
> Just a question : is there a way (kernel option ?) to disable
> Hyperthreading, so that FreeBSD only uses two physical CPUs ?

It is an option on current.  I need to backport it so that it will
be a kernel option on 4.8 as well.  

> I am running FreeBSD 4.8-RC on a Compaq ML370 dual-Xeon, and disabling
> HT in the BIOS has no effect.
> 
> Thanks in advance.
> 
> -- 
> Nicolas
> 
> 
> To Unsubscribe: send mail to majordomo@FreeBSD.org
> with "unsubscribe freebsd-smp" in the body of the message

-- 

John Baldwin <jhb@FreeBSD.org>  <><  http://www.FreeBSD.org/~jhb/
"Power Users Use the Power to Serve!"  -  http://www.FreeBSD.org/

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From owner-freebsd-smp  Fri Mar 14 17:41:18 2003
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Date: Fri, 14 Mar 2003 17:41:13 -0800
From: Brooks Davis <brooks@one-eyed-alien.net>
To: smp@freebsd.org
Subject: weird power usage on dual Xeon
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I recently got a dual Xeon from work that I'm using for testing and
since I'm paying for the power I hooked up my power meter up to it to
see how much power it consumed when.  The results were somewhat
suprising.  Is it expected that the Idle loop would consume more power
then a FPU intensive application like SETI@Home?  The only thing I can
think of is that the Idle loop stays in the cache and doesn't have the
kinds of stalls an appliction with 15MB of data to process does.

		no HTT	HTT
idle+hlt	94W	94W
idle		170W	183W
seti		160W	172W
seti+hlt	159W	171W

idle:	idle
htl:	sysctl machdep.cpu_idle_hlt=3D1
seti:	all CPUs (real or logical) running linux-setiathome-i686

-- Brooks

--=20
Any statement of the form "X is the one, true Y" is FALSE.
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From: Andy Isaacson <adi@hexapodia.org>
To: Brooks Davis <brooks@one-eyed-alien.net>
Cc: smp@freebsd.org
Subject: Re: weird power usage on dual Xeon
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On Fri, Mar 14, 2003 at 05:41:13PM -0800, Brooks Davis wrote:
>             Is it expected that the Idle loop would consume more power
> then a FPU intensive application like SETI@Home?  The only thing I can
> think of is that the Idle loop stays in the cache and doesn't have the
> kinds of stalls an appliction with 15MB of data to process does.
> 
> 		no HTT	HTT
> idle+hlt	94W	94W
> idle		170W	183W
> seti		160W	172W
> seti+hlt	159W	171W
> 
> idle:	idle
> htl:	sysctl machdep.cpu_idle_hlt=1
> seti:	all CPUs (real or logical) running linux-setiathome-i686

FWIW, I've measured about 45 W per processor (2.4 GHz Xeon 512k).

Do you get a different answer if you run only two copies of SETI?  I
can't imagine that their FFT routine takes kindly to having to share L1
cache, perhaps it's spending all its time waiting for the L2... and do
you actually process more work units per hour with 4 SETI processes
running on HT as opposed to 2 SETIs without HT?  I kinda doubt it, but
would welcome real information.

-andy

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From owner-freebsd-smp  Fri Mar 14 23: 7:21 2003
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From: "John Stockdale" <jstockdale@stanford.edu>
To: <freebsd-smp@FreeBSD.ORG>
Subject: SMP Enabled Make?
Date: Fri, 14 Mar 2003 23:07:17 -0800
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I am curious as to whether or not there is a SMP enabled version of make
for FreeBSD. I was recompiling my kernel yesterday and the fact that it
only spooled onto one processor annoyed me. Now although optimizing an
actual compiling operation for SMP is very difficult, is there (or why
isn't there) a make that will spool as many gcc operations at once as
you specify, or just as many as cpu's exist?

Seems that this combined with a ramdisk containing kernel source would
take make times from 8 mins down to about 3 (with HyperThreading).

Thanks

-John


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From owner-freebsd-smp  Fri Mar 14 23:12:10 2003
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On Fri, 14 Mar 2003, John Stockdale wrote:

> I am curious as to whether or not there is a SMP enabled version of make
> for FreeBSD.

Have you actually read the man page for make? Especially the -j option?

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From owner-freebsd-smp  Fri Mar 14 23:14:49 2003
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From: "John Stockdale" <jstockdale@stanford.edu>
To: "'Doug Barton'" <DougB@FreeBSD.ORG>
Cc: <freebsd-smp@FreeBSD.ORG>
Subject: RE: SMP Enabled Make?
Date: Fri, 14 Mar 2003 23:14:46 -0800
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No, but I'm just about to :)

Apolgies all around for spamming the list.

Thanks for the heads up Doug.

Sincerely,

-John

-----Original Message-----
From: owner-freebsd-smp@FreeBSD.ORG
[mailto:owner-freebsd-smp@FreeBSD.ORG] On Behalf Of Doug Barton
Sent: Friday, March 14, 2003 11:12 PM
To: John Stockdale
Cc: freebsd-smp@FreeBSD.ORG
Subject: Re: SMP Enabled Make?


On Fri, 14 Mar 2003, John Stockdale wrote:

> I am curious as to whether or not there is a SMP enabled version of 
> make for FreeBSD.

Have you actually read the man page for make? Especially the -j option?

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From owner-freebsd-smp  Sat Mar 15  3:41:10 2003
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From: Harti Brandt <brandt@fokus.fraunhofer.de>
To: smp@freebsd.org
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Subject: malloc.9 locking section
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Hi,

attached is a diff to malloc.9 that adds a section 'locking
considerations' to the man page. I would like to receive comments about

- whether this is altogether useful information to have in the man page
- about the section name (Solaris calls this section 'CONTEXT')
- about the section contents itself. I'm quite sure, that I got this
partly wrong.
- about the formatting (not beeing a mandoc expert)

harti

Index: malloc.9
===================================================================
RCS file: /home/ncvs/src/share/man/man9/malloc.9,v
retrieving revision 1.29
diff -u -r1.29 malloc.9
--- malloc.9	5 Feb 2003 14:00:46 -0000	1.29
+++ malloc.9	15 Mar 2003 11:34:03 -0000
@@ -230,6 +230,35 @@
 be used with
 .Xr mbuf 9
 routines as it will cause undesired results.
+.Sh LOCKING CONSIDERATIONS
+.Fn malloc ,
+.Fn realloc
+and
+.Fn reallocf
+may be called from threaded and fast interrupts handlers.
+When called from fast interrupts
+.Ar flag
+must contain
+.Dv M_NOWAIT .
+When called from threaded interrupts
+.Ar flag
+should contain
+.Dv M_NOWAIT .
+.Pp
+.Fn malloc ,
+.Fn realloc
+and
+.Fn reallocf
+must not be called with
+.Dv M_WAIT
+while a mutex other than Giant is held.
+Giant may or may not be held when
+.Fn malloc ,
+.Fn realloc ,
+.Fn reallocf
+or
+.Fn free
+are called.
 .Pp
 Any calls to
 .Fn malloc

-- 
harti brandt,
http://www.fokus.fraunhofer.de/research/cc/cats/employees/hartmut.brandt/private
brandt@fokus.fraunhofer.de, harti@freebsd.org

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From owner-freebsd-smp  Sat Mar 15  4:58:33 2003
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On Sat, 15 Mar 2003, Harti Brandt wrote:

> attached is a diff to malloc.9 that adds a section 'locking
> considerations' to the man page. I would like to receive comments about
>
> - whether this is altogether useful information to have in the man page
> - about the section name (Solaris calls this section 'CONTEXT')
> - about the section contents itself. I'm quite sure, that I got this
> partly wrong.
> - about the formatting (not beeing a mandoc expert)

> Index: malloc.9
> ===================================================================
> RCS file: /home/ncvs/src/share/man/man9/malloc.9,v
> retrieving revision 1.29
> diff -u -r1.29 malloc.9
> --- malloc.9	5 Feb 2003 14:00:46 -0000	1.29
> +++ malloc.9	15 Mar 2003 11:34:03 -0000
> @@ -230,6 +230,35 @@
>  be used with
>  .Xr mbuf 9
>  routines as it will cause undesired results.
> +.Sh LOCKING CONSIDERATIONS
> +.Fn malloc ,
> +.Fn realloc
> +and
> +.Fn reallocf
> +may be called from threaded and fast interrupts handlers.
> +When called from fast interrupts
> +.Ar flag
> +must contain
> +.Dv M_NOWAIT .

These functions (like most (should be all) functions that aren't in
<machine/atomic.h> or <machine/cpufunc.h>) may NOT be called from fast
interrupt handlers.  You may be confused by the bogus and broken check
of td_intr_nesting_level in malloc().  This is supposed to check that
normal interrupt handlers don't call malloc() with M_WAITOK, but has
rotted to only checking that fast interrupt handlers don't do this.
But fast interrupt handlers shouldn't even think of calling malloc().

> +When called from threaded interrupts
> +.Ar flag
> +should contain

s/should/must/

> +.Dv M_NOWAIT .

and not M_WAITOK (*).

> +.Pp
> +.Fn malloc ,
> +.Fn realloc
> +and
> +.Fn reallocf
> +must not be called with
> +.Dv M_WAIT
> +while a mutex other than Giant is held.

I think you mean M_WAITOK (M_WAIT is only for mbufs).  It's confusing to
say "flag must contain M_NOWAIT" for ithreads and "must not be called
with M_WAITOK" while a mutex other than Giant is held.  The requirements
are the same, and the conditions are almost the same too -- ithreads
might even be implemented using a mutex other than Giant to prevent
them being reentred, though in practice they use a different type of
locking.

> +Giant may or may not be held when
> +.Fn malloc ,
> +.Fn realloc ,
> +.Fn reallocf
> +or
> +.Fn free
> +are called.

This is redundant.

(*)  The man page doesn't seem to say that exactly one of {M_NOWAIT,
M_WAITOK}, must be set, perhaps because it has rotted and still
essentially says that M_WAITOK is 0.  Changes like the above should
be merged into the rotted bits to fix them and avoid redundancy.  Here
are some of the rotted bits:

% Note that
% .Dv M_NOWAIT
% is defined to be 0, meaning that blocking operation is the default.

Nope.  Clearly no one reads man section 9 manpages.

% Also note that
% .Dv M_NOWAIT
% is required when running in an interrupt context.

Still correct.

% .Pp
% Programmers should be careful not to confuse
% .Dv M_NOWAIT ,
% the
% .Fn malloc
% flag, with
% .Dv M_DONTWAIT ,
% an
% .Xr mbuf 9
% allocation flag, which is not a valid argument to
% .Fn malloc .
% .It Dv M_WAITOK
% Indicates that it is Ok to wait for resources.  It is unconveniently
% defined as 0 so care should be taken never to compare against this value
% directly or try to AND it as a flag.  The default operation is to block
% until the memory allocation succeeds.

Mostly rotted.

Bruce

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From owner-freebsd-smp  Sat Mar 15 22:21:27 2003
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I hate to beat a dead horse concerning this issue, but was anything ever
resolved with SMP problems with FreeBSD and the Intel SE7500CW2 running
Dual P4-Xeons ?  I don't have the time to read every message I get from
the FreeBSD related mail lists but a cursory search for related topics
showed up nothing.  Many thanks in advance.

Regards,
James Schmidt



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