Date: Sun, 31 Aug 2003 15:47:41 -0700 (PDT) From: Marcel Moolenaar <marcel@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 37284 for review Message-ID: <200308312247.h7VMlfUp086856@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=37284 Change 37284 by marcel@marcel_nfs on 2003/08/31 15:47:21 Properly deal with the fact that the registers on the ultra2 are not consecutive. This is considered a bug. The address lines are probably not wired correctly. We deal with this by adding a register shift variable to the puc(4) device information. It is exposed to subordinate devices as an IVAR. Since we already had support for shifting register numbers in uart(4), we only have to make sure we use it. Of course we also need to set the regshft for the low-level console. This too is trivial enough. Redefine the z8530 register offsets to be 0 for the control register and 1 for the data register as intended. Administrative note: There's a change in uart_dev_z8530.h that belongs to the next commit. Affected files ... .. //depot/projects/uart/dev/puc/puc.c#8 edit .. //depot/projects/uart/dev/puc/puc_sbus.c#3 edit .. //depot/projects/uart/dev/puc/pucvar.h#6 edit .. //depot/projects/uart/dev/uart/uart_bus_puc.c#5 edit .. //depot/projects/uart/dev/uart/uart_cpu_sparc64.c#8 edit .. //depot/projects/uart/dev/uart/uart_dev_z8530.h#5 edit Differences ... ==== //depot/projects/uart/dev/puc/puc.c#8 (text+ko) ==== @@ -105,8 +105,9 @@ struct puc_device { struct resource_list resources; - u_int serialfreq; - u_int subtype; + u_int serialfreq; + u_int subtype; + int regshft; }; static void puc_intr(void *arg); @@ -333,6 +334,7 @@ pdev->serialfreq = sc->sc_desc.ports[i].serialfreq; pdev->subtype = sc->sc_desc.ports[i].type & PUC_PORT_SUBTYPE_MASK; + pdev->regshft = sc->sc_desc.ports[i].regshft; childunit = puc_find_free_unit(typestr); if (childunit < 0 && strcmp(typestr, "uart") != 0) { @@ -599,6 +601,9 @@ case PUC_IVAR_SUBTYPE: *result = pdev->subtype; break; + case PUC_IVAR_REGSHFT: + *result = pdev->regshft; + break; default: return (ENOENT); } ==== //depot/projects/uart/dev/puc/puc_sbus.c#3 (text+ko) ==== @@ -71,6 +71,7 @@ dd.ports[i].offset = 4 * i; dd.ports[i].serialfreq = 0; dd.ports[i].flags = PUC_FLAGS_MEMORY; + dd.ports[i].regshft = 1; } return (puc_attach(dev, &dd)); } ==== //depot/projects/uart/dev/puc/pucvar.h#6 (text+ko) ==== @@ -79,6 +79,7 @@ int offset; u_int serialfreq; u_int flags; + int regshft; } ports[PUC_MAX_PORTS]; uint32_t ilr_type; uint32_t ilr_offset[2]; @@ -114,7 +115,8 @@ enum puc_device_ivars { PUC_IVAR_FREQ, - PUC_IVAR_SUBTYPE + PUC_IVAR_SUBTYPE, + PUC_IVAR_REGSHFT }; #ifdef PUC_ENTRAILS ==== //depot/projects/uart/dev/uart/uart_bus_puc.c#5 (text+ko) ==== @@ -63,7 +63,7 @@ { device_t parent; struct uart_softc *sc; - uintptr_t rclk, type; + uintptr_t rclk, regshft, type; parent = device_get_parent(dev); sc = device_get_softc(dev); @@ -86,7 +86,9 @@ if (BUS_READ_IVAR(parent, dev, PUC_IVAR_FREQ, &rclk)) rclk = 0; - return (uart_bus_probe(dev, 0, rclk, 0)); + if (BUS_READ_IVAR(parent, dev, PUC_IVAR_REGSHFT, ®shft)) + regshft = 0; + return (uart_bus_probe(dev, regshft, rclk, 0)); } DRIVER_MODULE(uart, puc, uart_puc_driver, uart_devclass, 0, 0); ==== //depot/projects/uart/dev/uart/uart_cpu_sparc64.c#8 (text+ko) ==== @@ -100,6 +100,7 @@ di->ops = uart_ns8250_ops; else if (!strcmp(buffer, "zs")) { di->ops = uart_z8530_ops; + di->bas.regshft = 1; di->bas.bsh += 4; } else return (ENXIO); ==== //depot/projects/uart/dev/uart/uart_dev_z8530.h#5 (text+ko) ==== @@ -31,12 +31,14 @@ /* * Channel B control: 0 - * Channel B data: 2 - * Channel A control: 4 - * Channel A data: 6 + * Channel B data: 1 + * Channel A control: 2 + * Channel A data: 3 + * + * We expect a seperate subregion for each channel. */ #define REG_CTRL 0 -#define REG_DATA 2 +#define REG_DATA 1 /* Write registers. */ #define WR_CR 0 /* Command Register. */ @@ -241,7 +243,7 @@ #define TPC_TB6 0x40 /* 6 databits. */ #define TPC_TB7 0x20 /* 7 databits. */ #define TPC_TB5 0x00 /* 5 or fewer databits. */ -#define TPC_SB 0x10 /* Send break. */ +#define TPC_BRK 0x10 /* Send break. */ #define TPC_TXE 0x08 /* Transmitter Enable. */ #define TPC_CRC16 0x04 /* CRC16. */ #define TPC_RTS 0x02 /* RTS. */
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