From owner-freebsd-hackers@FreeBSD.ORG Sun Jun 5 02:53:58 2005 Return-Path: X-Original-To: freebsd-hackers@freebsd.org Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id C232316A41C for ; Sun, 5 Jun 2005 02:53:58 +0000 (GMT) (envelope-from imp@bsdimp.com) Received: from harmony.village.org (berlin-qwest.village.org [168.103.84.175]) by mx1.FreeBSD.org (Postfix) with ESMTP id 70B6043D55 for ; Sun, 5 Jun 2005 02:53:56 +0000 (GMT) (envelope-from imp@bsdimp.com) Received: from localhost (warner@rover2.village.org [10.0.0.1]) by harmony.village.org (8.13.3/8.13.1) with ESMTP id j552opx6057155; Sat, 4 Jun 2005 20:50:52 -0600 (MDT) (envelope-from imp@bsdimp.com) Date: Sat, 04 Jun 2005 20:51:38 -0600 (MDT) Message-Id: <20050604.205138.89664988.imp@bsdimp.com> To: dipjyoti.saikia@gmail.com From: "M. Warner Losh" In-Reply-To: References: X-Mailer: Mew version 3.3 on Emacs 21.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cc: freebsd-hackers@freebsd.org Subject: Re: NMI handlers ?? X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 05 Jun 2005 02:53:58 -0000 In message: Dipjyoti Saikia writes: : I am working on IPMI watchdog implementation . The problem that I am : facing is that in case of improper system shutdown or powerfail the : watchdog keeps running and the next time system boots up , BIOS : complains of FRB2 timeout and fails one of the CPU's ( Working on SMP : system ) . : : My idea is to handle NMI generated by abruptly pushing power button : and disabling the timer in the routine. : : Can we have a handlers for NMI ?? I am not very sure what is happening : inside the kernel when NMI is delivered . : : Please provide me some inputs. We did this at timing solutions. Here are a few notes: (1) You must disable the F00F_HACK with the kernel config file. (2) We had to hack the nmi code to allow multiple refiring of the nmi routine in the chipset. These hacks are evidentially fairly chipset specific. We were using the #IOCHK line on the ISA bus to accomplish this. I don't think that you'll need to worry about this. (3) You need some kind of NMI handler. You can do almost nothing in this handler. The following code is from 4.x. nmiReset is set elsewhere. #include /* miscellaneous macros */ #include /* CPP macros */ /* XXX: not very portable! */ #define KDSEL 0x10 /* kernel data selector */ .text ALIGN_TEXT .globl Xtscnmidrv Xtscnmidrv: pushl %eax pushl %ecx pushl %edx pushl %ds movl $KDSEL, %eax movl %eax, %ds /* read the timestamp counter */ .byte 0x0f, 0x31 /* RDTSC */ movl %edx, tsHi movl %eax, tsLo /* update the counter */ incl nmiCounter /* * XXX: It is necessary to drop the NMI level on the driving * card at this point IF we wish to use 'NMI_CREATE_EDGE' */ .globl nmiReset movl nmiReset, %eax testl %eax, %eax /* XXX: we should really just permanently disable NMIs in this case */ je skip call *%eax skip: /* diddle the IOCHK# NMI registers */ inb $0x61, %al /* current PORT-B contents */ /* XXX: need to test source bits, assume IOCHK# for now... */ andb $0x0f, %al /* PIIX wants upper bits 0 on write */ orb $0x08, %al /* IOCHK# high to clear */ outb %al, $0x61 andb $0x07, %al /* IOCHK# low to enable */ outb %al, $0x61 /* restore registers */ popl %ds popl %edx popl %ecx popl %eax iret .data ALIGN_DATA .globl nmiCounter nmiCounter: .long 0 .globl timeStamp timeStamp: tsLo: .long 0 tsHi: .long 0 4) We have to establish the handler: /* Install the custom TSC NMI handler. */ setidt( 2, &IDTVEC(tscnmidrv), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL) ); and set nmiReset when you arm the nmi source and clear it if you ever disarm it. nmiReset should be set to the function you want to call. I'm not sure what the right sequence of inb/outb is for your chipset... Warner