From owner-freebsd-smp@FreeBSD.ORG Tue Oct 3 15:12:29 2006 Return-Path: X-Original-To: freebsd-smp@freebsd.org Delivered-To: freebsd-smp@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 51A4E16A51B for ; Tue, 3 Oct 2006 15:12:29 +0000 (UTC) (envelope-from girish.motwani@gmail.com) Received: from ug-out-1314.google.com (ug-out-1314.google.com [66.249.92.174]) by mx1.FreeBSD.org (Postfix) with ESMTP id AD05A43D46 for ; Tue, 3 Oct 2006 15:12:28 +0000 (GMT) (envelope-from girish.motwani@gmail.com) Received: by ug-out-1314.google.com with SMTP id m2so592721uge for ; Tue, 03 Oct 2006 08:12:27 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:to:subject:mime-version:content-type; b=J08OSoeei/lliHcizkV2PYjC9+NqGlBOSoXe38igKuXXhd8l0hzVJVnteUW3IB9k7uraxjHa6g5ARlpW271Gn3HUtOwB6nFiM/H14qleUJ2TSoIQAiLOATfqFqUuts0DYLJti+IiymcOjZAiiURDnuSpA21t7GL4gPJLREtLAL0= Received: by 10.67.117.2 with SMTP id u2mr3872813ugm; Tue, 03 Oct 2006 08:12:27 -0700 (PDT) Received: by 10.66.232.1 with HTTP; Tue, 3 Oct 2006 08:12:26 -0700 (PDT) Message-ID: <2779e6080610030812t7aed1eedua3e89d81baedafa5@mail.gmail.com> Date: Tue, 3 Oct 2006 20:42:26 +0530 From: "Girish Motwani" To: freebsd-smp@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline X-Content-Filtered-By: Mailman/MimeDel 2.1.5 Subject: Interrupt Handling with Multiple CPUs X-BeenThere: freebsd-smp@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: FreeBSD SMP implementation group List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Oct 2006 15:12:29 -0000 Hi, I was looking through the FreeBSD 6.1 release code and had the following questions related to interrupt handling: 1. How are the interrupts distributed to multiple CPUs in an SMP system ? On i386, from the code it appears that that IRQs are tied to CPUs using a round robin mechanism whereby a particular interrupt (for eg UART) would always be serviced on a particular CPU. Is the same model followed on other architectures ? 2. Is there support for directing the interrupt to any CPU based on the current load on each CPU ? or round robin the interrupts across CPUs ? If yes, then what happens in the following scenario: A interrupt arrives and the handler needs to sleep since it needs a sleep mutex which is owned by some other thread. So it uses the ithread for that interrupt source to provide the context for sleeping. At this time, another interrupt of the same type arrives. Thanks in advance, girish