From owner-freebsd-ppc@FreeBSD.ORG Sun Sep 28 06:40:55 2008 Return-Path: Delivered-To: freebsd-ppc@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id AEE6D106568B for ; Sun, 28 Sep 2008 06:40:55 +0000 (UTC) (envelope-from grehan@freebsd.org) Received: from alto.onthenet.com.au (alto.OntheNet.com.au [203.13.68.12]) by mx1.freebsd.org (Postfix) with ESMTP id 3553B8FC15 for ; Sun, 28 Sep 2008 06:40:55 +0000 (UTC) (envelope-from grehan@freebsd.org) Received: from dommail.onthenet.com.au (dommail.OntheNet.com.au [203.13.70.57]) by alto.onthenet.com.au (Postfix) with ESMTP id B259B11991; Sun, 28 Sep 2008 16:40:52 +1000 (EST) Received: from peter-grehans-power-mac-g5.local (dsl-63-249-90-35.cruzio.com [63.249.90.35]) by dommail.onthenet.com.au (MOS 3.8.6-GA) with ESMTP id EJF89406 (AUTH peterg@ptree32.com.au); Sun, 28 Sep 2008 16:40:11 +1000 (EST) Message-ID: <48DF26F2.1000209@freebsd.org> Date: Sat, 27 Sep 2008 23:40:50 -0700 From: Peter Grehan User-Agent: Thunderbird 2.0.0.17 (Macintosh/20080914) MIME-Version: 1.0 To: Marcel Moolenaar References: <48DD91A4.2060306@freebsd.org> <263AF44F-FC15-4700-B93B-B0DE07A17B40@mac.com> <11FEA924-DB76-46E1-BF79-A26206F796C0@mac.com> In-Reply-To: <11FEA924-DB76-46E1-BF79-A26206F796C0@mac.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: freebsd-ppc@freebsd.org Subject: Re: 8.0-current 200809 snapshot CD boot problem X-BeenThere: freebsd-ppc@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list Reply-To: grehan@freebsd.org List-Id: Porting FreeBSD to the PowerPC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 28 Sep 2008 06:40:55 -0000 Hi Marcel, > o I-cache coherency The culprit could be the code fragment in sys/boot/ofw/libofw/elf_freebsd.c:__elfN(ofw_loadfile), if (!strcmp((*result)->f_type, "elf kernel")) __syncicache((void *) (*result)->f_addr, (*result)->f_size); If f_addr isn't the start of the text segment i.e. if the initial page wasn't included, then that is what is blowing up. > Quick question: On ARM and ia64 you need to sync the > D-cache before you can make the I-cache coherent. That's > because the I-cache is made coherent with memory and > not with the D-cache. How's that on PowerPC? Same - see powerpc/syncicache.c where the d-cache is flushed before the invalidating the i-cache. later, Peter.