From owner-svn-src-projects@FreeBSD.ORG Sun Nov 8 07:26:02 2009 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id CA5B9106566C; Sun, 8 Nov 2009 07:26:02 +0000 (UTC) (envelope-from gonzo@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id B97758FC08; Sun, 8 Nov 2009 07:26:02 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id nA87Q2HD077341; Sun, 8 Nov 2009 07:26:02 GMT (envelope-from gonzo@svn.freebsd.org) Received: (from gonzo@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id nA87Q2LJ077337; Sun, 8 Nov 2009 07:26:02 GMT (envelope-from gonzo@svn.freebsd.org) Message-Id: <200911080726.nA87Q2LJ077337@svn.freebsd.org> From: Oleksandr Tymoshenko Date: Sun, 8 Nov 2009 07:26:02 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r199038 - projects/mips/sys/mips/atheros X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Nov 2009 07:26:03 -0000 Author: gonzo Date: Sun Nov 8 07:26:02 2009 New Revision: 199038 URL: http://svn.freebsd.org/changeset/base/199038 Log: - Access to all 5 PHYs goes through registers in MAC0 memory space, rewrite miibus accessors respectively Modified: projects/mips/sys/mips/atheros/ar71xxreg.h projects/mips/sys/mips/atheros/if_arge.c projects/mips/sys/mips/atheros/if_argevar.h Modified: projects/mips/sys/mips/atheros/ar71xxreg.h ============================================================================== --- projects/mips/sys/mips/atheros/ar71xxreg.h Sun Nov 8 02:33:33 2009 (r199037) +++ projects/mips/sys/mips/atheros/ar71xxreg.h Sun Nov 8 07:26:02 2009 (r199038) @@ -214,6 +214,10 @@ */ #define AR71XX_MAC0_BASE 0x19000000 #define AR71XX_MAC1_BASE 0x1A000000 +/* + * All 5 PHYs accessible only through MAC0 register space + */ +#define AR71XX_MII_BASE 0x19000000 #define AR71XX_MAC_CFG1 0x00 #define MAC_CFG1_SOFT_RESET (1 << 31) Modified: projects/mips/sys/mips/atheros/if_arge.c ============================================================================== --- projects/mips/sys/mips/atheros/if_arge.c Sun Nov 8 02:33:33 2009 (r199037) +++ projects/mips/sys/mips/atheros/if_arge.c Sun Nov 8 07:26:02 2009 (r199038) @@ -162,6 +162,11 @@ DRIVER_MODULE(miibus, arge, miibus_drive */ extern uint32_t ar711_base_mac[ETHER_ADDR_LEN]; +static struct mtx miibus_mtx; + +MTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_SPIN); + + /* * Flushes all */ @@ -488,23 +493,27 @@ arge_miibus_readreg(device_t dev, int ph if (phy != sc->arge_phy_num) return (0); - ARGE_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); - ARGE_WRITE(sc, AR71XX_MAC_MII_ADDR, addr); - ARGE_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ); + mtx_lock(&miibus_mtx); + ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); + ARGE_MII_WRITE(AR71XX_MAC_MII_ADDR, addr); + ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ); i = ARGE_MII_TIMEOUT; - while ((ARGE_READ(sc, AR71XX_MAC_MII_INDICATOR) & + while ((ARGE_MII_READ(AR71XX_MAC_MII_INDICATOR) & MAC_MII_INDICATOR_BUSY) && (i--)) DELAY(5); if (i < 0) { + mtx_unlock(&miibus_mtx); dprintf("%s timedout\n", __func__); /* XXX: return ERRNO istead? */ return (-1); } - result = ARGE_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK; - ARGE_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); + result = ARGE_MII_READ(AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK; + ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); + mtx_unlock(&miibus_mtx); + dprintf("%s: phy=%d, reg=%02x, value[%08x]=%04x\n", __func__, phy, reg, addr, result); @@ -519,17 +528,24 @@ arge_miibus_writereg(device_t dev, int p uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK); + + if (phy != sc->arge_phy_num) + return (-1); + dprintf("%s: phy=%d, reg=%02x, value=%04x\n", __func__, phy, reg, data); - ARGE_WRITE(sc, AR71XX_MAC_MII_ADDR, addr); - ARGE_WRITE(sc, AR71XX_MAC_MII_CONTROL, data); + mtx_lock(&miibus_mtx); + ARGE_MII_WRITE(AR71XX_MAC_MII_ADDR, addr); + ARGE_MII_WRITE(AR71XX_MAC_MII_CONTROL, data); i = ARGE_MII_TIMEOUT; - while ((ARGE_READ(sc, AR71XX_MAC_MII_INDICATOR) & + while ((ARGE_MII_READ(AR71XX_MAC_MII_INDICATOR) & MAC_MII_INDICATOR_BUSY) && (i--)) DELAY(5); + mtx_unlock(&miibus_mtx); + if (i < 0) { dprintf("%s timedout\n", __func__); /* XXX: return ERRNO istead? */ Modified: projects/mips/sys/mips/atheros/if_argevar.h ============================================================================== --- projects/mips/sys/mips/atheros/if_argevar.h Sun Nov 8 02:33:33 2009 (r199037) +++ projects/mips/sys/mips/atheros/if_argevar.h Sun Nov 8 07:26:02 2009 (r199038) @@ -64,6 +64,16 @@ #define ARGE_CLEAR_BITS(sc, reg, bits) \ ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) & ~(bits)) +/* + * MII registers access macros + */ +#define ARGE_MII_READ(reg) \ + *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((AR71XX_MII_BASE + reg))) + +#define ARGE_MII_WRITE(reg, val) \ + *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((AR71XX_MII_BASE + reg))) = (val) + + #define ARGE_DESC_EMPTY (1 << 31) #define ARGE_DESC_MORE (1 << 24) #define ARGE_DESC_SIZE_MASK ((1 << 12) - 1)