From owner-freebsd-arch@FreeBSD.ORG Sun Oct 3 23:21:51 2010 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 175C51065673 for ; Sun, 3 Oct 2010 23:21:51 +0000 (UTC) (envelope-from freebsd-arch@m.gmane.org) Received: from lo.gmane.org (lo.gmane.org [80.91.229.12]) by mx1.freebsd.org (Postfix) with ESMTP id C01998FC15 for ; Sun, 3 Oct 2010 23:21:50 +0000 (UTC) Received: from list by lo.gmane.org with local (Exim 4.69) (envelope-from ) id 1P2Xdo-0006uk-3Z for freebsd-arch@freebsd.org; Mon, 04 Oct 2010 01:06:48 +0200 Received: from 93-141-115-47.adsl.net.t-com.hr ([93.141.115.47]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Mon, 04 Oct 2010 01:06:48 +0200 Received: from ivoras by 93-141-115-47.adsl.net.t-com.hr with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Mon, 04 Oct 2010 01:06:48 +0200 X-Injected-Via-Gmane: http://gmane.org/ To: freebsd-arch@freebsd.org From: Ivan Voras Date: Mon, 04 Oct 2010 01:06:39 +0200 Lines: 17 Message-ID: References: Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Complaints-To: usenet@dough.gmane.org X-Gmane-NNTP-Posting-Host: 93-141-115-47.adsl.net.t-com.hr User-Agent: Mozilla/5.0 (X11; U; FreeBSD amd64; en-US; rv:1.9.1.9) Gecko/20100620 Thunderbird/3.0.4 In-Reply-To: Subject: Re: Porting effort towards TILERA massive multicore CPUs...? X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 03 Oct 2010 23:21:51 -0000 On 09/30/10 12:05, Robert Watson wrote: > > On Sun, 26 Sep 2010, Paketix wrote: > >> there is a rather new processor from TILERA (100 core chip) which is >> most certainly already known here at FreeBSD mailing list. > > Theory has it I'll be getting access to Intel SCC 48/96-core hardware > here at Cambridge in the moderately near future, and I've been pondering > what would be involved. Their model involves 48+ x86 cores without > cache coherency, so you need separate OS instances for each. However, > the cores are linked by fifo-like memory that we'll need to figure out > what to do with. Sounds pretty much made for a variation on the microkernel design, or virtualization.