From owner-freebsd-arm@FreeBSD.ORG Sun Mar 7 01:40:01 2010 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id BF479106564A for ; Sun, 7 Mar 2010 01:40:01 +0000 (UTC) (envelope-from maksverver@geocities.com) Received: from mx.utwente.nl (mx2.utsp.utwente.nl [130.89.2.13]) by mx1.freebsd.org (Postfix) with ESMTP id 3C5078FC17 for ; Sun, 7 Mar 2010 01:40:00 +0000 (UTC) Received: from heaven.student.utwente.nl (heaven.student.utwente.nl [130.89.167.52]) by mx.utwente.nl (8.12.10/SuSE Linux 0.7) with ESMTP id o271dro2020425 for ; Sun, 7 Mar 2010 02:39:53 +0100 Message-ID: <4B9303E4.3090500@geocities.com> Date: Sun, 07 Mar 2010 02:39:48 +0100 From: Maks Verver User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100209 Thunderbird/3.0.1 MIME-Version: 1.0 To: freebsd-arm@freebsd.org References: <4B92BD9D.6030709@geocities.com> <20100306211715.GK58319@cicely7.cicely.de> <20100306215153.GL58319@cicely7.cicely.de> <20100306.152603.716362616846278503.imp@bsdimp.com> In-Reply-To: <20100306.152603.716362616846278503.imp@bsdimp.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-UTwente-MailScanner-Information: Scanned by MailScanner. Contact icts.servicedesk@utwente.nl for more information. X-UTwente-MailScanner: Found to be clean X-UTwente-MailScanner-From: maksverver@geocities.com X-Spam-Status: No Subject: Re: Performance of SheevaPlug on 8-stable X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 07 Mar 2010 01:40:01 -0000 On 03/06/2010 10:17 PM, Bernd Walter wrote: > Such massive speed difference sounds a bit like cache problems. On 03/06/2010 11:26 PM, M. Warner Losh wrote: > Sounds a lot like ICACHE isn't being enabled, since a 3-liner like > this should be executing entirely out of cache after the first > instruction in main prefetches the cache line. Thanks for the quick responses! I think the both of you are right. I didn't realize the cache could be turned off at all, but the boot output shows: CPU: Feroceon 88FR131 rev 1 (write-through core) WB enabled EABT branch prediction enabled 16KB/32B 4-way Instruction cache 16KB/32B 4-way write-back-locking-C Data cache This is different from the output on the wiki (which instructions I followed, to some extent) at http://wiki.freebsd.org/FreeBSDMarvell: CPU: ARM926EJ-S rev 0 (ARM9EJ-S core) DC enabled IC enabled WB enabled EABT branch prediction enabled 32KB/32B 1-way Instruction cache 32KB/32B 4-way write-back-locking-C Data cache Note that this guy is not running a SheevaPlug; the CPU is different. But it's clear enough that on my system both processor caches are disabled (even though they are correctly identified) and this is understandably catastrophic for performance. It's good to have that figured out at least. :-) The logical next question is: why aren't these caches enabled? How is this supposed to work? Is the bootloader supposed to enable the cache, or the kernel? If the kernel, why isn't it doing this? (If it's the bootloader's task, then it's strange that the Linux kernel has no trouble enabling the cache with the same bootloader). Kind regards, Maks Verver.