From owner-svn-src-head@FreeBSD.ORG Sun Mar 21 00:13:11 2010 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id DEC6A106566B; Sun, 21 Mar 2010 00:13:11 +0000 (UTC) (envelope-from alc@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id B38A38FC0C; Sun, 21 Mar 2010 00:13:11 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o2L0DBsd029606; Sun, 21 Mar 2010 00:13:11 GMT (envelope-from alc@svn.freebsd.org) Received: (from alc@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o2L0DBbi029603; Sun, 21 Mar 2010 00:13:11 GMT (envelope-from alc@svn.freebsd.org) Message-Id: <201003210013.o2L0DBbi029603@svn.freebsd.org> From: Alan Cox Date: Sun, 21 Mar 2010 00:13:11 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r205402 - in head/sys/amd64: amd64 include X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 21 Mar 2010 00:13:12 -0000 Author: alc Date: Sun Mar 21 00:13:11 2010 New Revision: 205402 URL: http://svn.freebsd.org/changeset/base/205402 Log: I am told by AMD that the machine check hardware on the instruction TLB won't generate bogus exceptions. Therefore, the implementation of the "unofficial" workaround needn't mask L1TP errors by the instruction cache unit. Modified: head/sys/amd64/amd64/mca.c head/sys/amd64/include/specialreg.h Modified: head/sys/amd64/amd64/mca.c ============================================================================== --- head/sys/amd64/amd64/mca.c Sun Mar 21 00:05:29 2010 (r205401) +++ head/sys/amd64/amd64/mca.c Sun Mar 21 00:13:11 2010 (r205402) @@ -565,19 +565,16 @@ mca_init(void) /* * Disable logging of level one TLB parity (L1TP) errors by - * the data and instruction caches as an alternative - * workaround for AMD Family 10h Erratum 383. Unlike the - * recommended workaround, there is no performance penalty to - * this workaround. However, L1TP errors will go unreported. + * the data cache as an alternative workaround for AMD Family + * 10h Erratum 383. Unlike the recommended workaround, there + * is no performance penalty to this workaround. However, + * L1TP errors will go unreported. */ if (cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY(cpu_id) == 0x10 && !amd10h_L1TP) { mask = rdmsr(MSR_MC0_CTL_MASK); if ((mask & (1UL << 5)) == 0) wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5)); - mask = rdmsr(MSR_MC1_CTL_MASK); - if ((mask & (1UL << 5)) == 0) - wrmsr(MSR_MC1_CTL_MASK, mask | (1UL << 5)); } for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) { /* By default enable logging of all errors. */ Modified: head/sys/amd64/include/specialreg.h ============================================================================== --- head/sys/amd64/include/specialreg.h Sun Mar 21 00:05:29 2010 (r205401) +++ head/sys/amd64/include/specialreg.h Sun Mar 21 00:13:11 2010 (r205402) @@ -507,7 +507,6 @@ #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ #define MSR_MC0_CTL_MASK 0xc0010044 -#define MSR_MC1_CTL_MASK 0xc0010045 /* VIA ACE crypto featureset: for via_feature_rng */ #define VIA_HAS_RNG 1 /* cpu has RNG */