From owner-freebsd-mips@FreeBSD.ORG Tue Jul 19 01:07:37 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 59890106566C; Tue, 19 Jul 2011 01:07:37 +0000 (UTC) (envelope-from asmrookie@gmail.com) Received: from mail-yx0-f182.google.com (mail-yx0-f182.google.com [209.85.213.182]) by mx1.freebsd.org (Postfix) with ESMTP id E203D8FC17; Tue, 19 Jul 2011 01:07:36 +0000 (UTC) Received: by yxl31 with SMTP id 31so1924805yxl.13 for ; Mon, 18 Jul 2011 18:07:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=Tz0xS4cN7aKMOqYjI5Ngjo7+mf1kZ2le6KsrQR9qIxY=; b=EC1rDeYxAwiLALs3252rFJHlnMUPjwkih6sL77Ey7L0wIYwHtnDCz1aN1WW6+T3pH2 tFH1vBx1CLEOr7b/RB5Tbx8596NOwHGAFAPHsyqUpSdQtov8SxsWSt9Ncd5RzaAtSevA HDi7HHl8HcdDn2mL+AkPuuKOaJ054Tcx3Yrs4= MIME-Version: 1.0 Received: by 10.236.136.106 with SMTP id v70mr7730042yhi.406.1311037656132; Mon, 18 Jul 2011 18:07:36 -0700 (PDT) Sender: asmrookie@gmail.com Received: by 10.236.105.169 with HTTP; Mon, 18 Jul 2011 18:07:36 -0700 (PDT) In-Reply-To: References: Date: Tue, 19 Jul 2011 03:07:36 +0200 X-Google-Sender-Auth: C5-T0BIrrNcwJ-Xnu73b6EOKRTE Message-ID: From: Attilio Rao To: "Jayachandran C." Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Cc: Warner Losh , freebsd-mips@freebsd.org Subject: Re: Bumping MAXCPU for MIPS configurations X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jul 2011 01:07:37 -0000 2011/7/3 Jayachandran C. : > On Wed, Jun 29, 2011 at 4:48 PM, Attilio Rao wrote: >> 2011/6/29 Jayachandran C. : >>> On Wed, Jun 29, 2011 at 3:10 PM, Attilio Rao wrot= e: >>>> [ Please CC me in replies as I'm not subscribed to this mailing list ] >>>> >>>> I'm planning to bump MAXCPU for all the kernel configurations >>>> requiring it, as long as the latest cut of largeSMP changes is >>>> completed. >>>> >>>> Anyway, I'm not really sure what MIPS configurations may benefit from >>>> a larger number of MAXCPU. Probabilly XLP should, for what I've heard, >>>> but I'd like to get a precise mapping between configurations that want >>>> to bump the number and the actual maximum number of CPUs to be >>>> supported. >>> >>> An XLP SoC has 32 cpus (8cores x 4 hw threads per core), and 4 of >>> these can be interconnected to have upto 128 cpus. =C2=A0We have an XLP >>> port running on one chip with 32cpus, but there is interest in trying >>> out 2 chip (64cpus) and 4 chip(128 cpus) configurations, so this is >>> something I want to do when I get access to multi-chip boards for >>> FreeBSD development. >> >> I'll bump MAXCPU to 128 for XLP then, thanks. >> Do you have informations about XLR? > > For XLR the the MAXCPU should be 32 (8 cores x 4 threads per core on > the SoC). We cannot connect multiple chips together like the XLP. So what do you think about this patch?: http://www.freebsd.org/~attilio/maxcpu_bump.diff I already got Marcel's approval on ia64 part, but I need you review the mips bits. Thanks, Attilio --=20 Peace can only be achieved by understanding - A. Einstein From owner-freebsd-mips@FreeBSD.ORG Tue Jul 19 03:46:14 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 96425106568F; Tue, 19 Jul 2011 03:46:14 +0000 (UTC) (envelope-from c.jayachandran@gmail.com) Received: from mail-ww0-f42.google.com (mail-ww0-f42.google.com [74.125.82.42]) by mx1.freebsd.org (Postfix) with ESMTP id AAB858FC14; Tue, 19 Jul 2011 03:46:13 +0000 (UTC) Received: by wwg11 with SMTP id 11so3499750wwg.1 for ; Mon, 18 Jul 2011 20:46:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=/EE1y2a0Q7E8Bq844l8qMR68OujN5DxHMtPhxRXdpKg=; b=hRyGyGCH5WUKRdw1cs5yOf7RVOMHY/3BQqwy+L9q2fdqeDEQrHFDYqdbaZNtajeO+p BtJTb7cHxJbZpJMtJYlattthPAD2ph+6g9CI/nszsg1gmRRlAvdk+xs+N2h6csp+LQGA McrUaozQI1T/T6H6DFmxoqMxUgeYq5tz5tWfI= MIME-Version: 1.0 Received: by 10.216.155.134 with SMTP id j6mr6385775wek.81.1311047172328; Mon, 18 Jul 2011 20:46:12 -0700 (PDT) Received: by 10.216.173.211 with HTTP; Mon, 18 Jul 2011 20:46:12 -0700 (PDT) In-Reply-To: References: Date: Tue, 19 Jul 2011 09:16:12 +0530 Message-ID: From: "Jayachandran C." To: Attilio Rao Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: Warner Losh , freebsd-mips@freebsd.org Subject: Re: Bumping MAXCPU for MIPS configurations X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jul 2011 03:46:14 -0000 On Tue, Jul 19, 2011 at 6:37 AM, Attilio Rao wrote: > 2011/7/3 Jayachandran C. : >> On Wed, Jun 29, 2011 at 4:48 PM, Attilio Rao wrote= : >>> 2011/6/29 Jayachandran C. : >>>> On Wed, Jun 29, 2011 at 3:10 PM, Attilio Rao wro= te: >>>>> [ Please CC me in replies as I'm not subscribed to this mailing list = ] >>>>> >>>>> I'm planning to bump MAXCPU for all the kernel configurations >>>>> requiring it, as long as the latest cut of largeSMP changes is >>>>> completed. >>>>> >>>>> Anyway, I'm not really sure what MIPS configurations may benefit from >>>>> a larger number of MAXCPU. Probabilly XLP should, for what I've heard= , >>>>> but I'd like to get a precise mapping between configurations that wan= t >>>>> to bump the number and the actual maximum number of CPUs to be >>>>> supported. >>>> >>>> An XLP SoC has 32 cpus (8cores x 4 hw threads per core), and 4 of >>>> these can be interconnected to have upto 128 cpus. =A0We have an XLP >>>> port running on one chip with 32cpus, but there is interest in trying >>>> out 2 chip (64cpus) and 4 chip(128 cpus) configurations, so this is >>>> something I want to do when I get access to multi-chip boards for >>>> FreeBSD development. >>> >>> I'll bump MAXCPU to 128 for XLP then, thanks. >>> Do you have informations about XLR? >> >> For XLR the the MAXCPU should be 32 (8 cores x 4 threads per core on >> the SoC). We cannot connect multiple chips together like the XLP. > > So what do you think about this patch?: > http://www.freebsd.org/~attilio/maxcpu_bump.diff > > I already got Marcel's approval on ia64 part, but I need you review > the mips bits. For the XLP changes, we don't really need 128 for MAXCPU now. The ICI interface driver which is needed to connect multiple XLPs together to get 64/128 cpus have not been checked in yet. I plan to do this a few months down the line. Regards, JC. From owner-freebsd-mips@FreeBSD.ORG Tue Jul 19 11:48:05 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id EF6CB1065674; Tue, 19 Jul 2011 11:48:04 +0000 (UTC) (envelope-from asmrookie@gmail.com) Received: from mail-yx0-f182.google.com (mail-yx0-f182.google.com [209.85.213.182]) by mx1.freebsd.org (Postfix) with ESMTP id 879108FC0A; Tue, 19 Jul 2011 11:48:04 +0000 (UTC) Received: by yxl31 with SMTP id 31so2105837yxl.13 for ; Tue, 19 Jul 2011 04:48:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=naAdwigXJBXXiDe4KQimnXsp4i37uAg899GQy+JSAnw=; b=vPvVSedh0gsA6ZOw76w9PVpq+GZ3pyBLgBchGj+oqTaawNs7vaDMdosrRIt+HKO7bY gYLwOoMmn/iLxE7mzMDmW+iOdtdijhPtlzWOj98HUPugqbCRhom4qUIDV97RwAIs7URu TjMxfT+/SwVkhCSSVpS/oQJl2UXWjHWqviL48= MIME-Version: 1.0 Received: by 10.236.9.100 with SMTP id 64mr5614677yhs.339.1311076083804; Tue, 19 Jul 2011 04:48:03 -0700 (PDT) Sender: asmrookie@gmail.com Received: by 10.236.105.169 with HTTP; Tue, 19 Jul 2011 04:48:03 -0700 (PDT) In-Reply-To: References: Date: Tue, 19 Jul 2011 13:48:03 +0200 X-Google-Sender-Auth: v5Ag74XCXakmKNJz_AoC_0c8Ai0 Message-ID: From: Attilio Rao To: "Jayachandran C." Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Cc: Warner Losh , freebsd-mips@freebsd.org Subject: Re: Bumping MAXCPU for MIPS configurations X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jul 2011 11:48:05 -0000 2011/7/19 Jayachandran C. : > On Tue, Jul 19, 2011 at 6:37 AM, Attilio Rao wrote: >> 2011/7/3 Jayachandran C. : >>> On Wed, Jun 29, 2011 at 4:48 PM, Attilio Rao wrot= e: >>>> 2011/6/29 Jayachandran C. : >>>>> On Wed, Jun 29, 2011 at 3:10 PM, Attilio Rao wr= ote: >>>>>> [ Please CC me in replies as I'm not subscribed to this mailing list= ] >>>>>> >>>>>> I'm planning to bump MAXCPU for all the kernel configurations >>>>>> requiring it, as long as the latest cut of largeSMP changes is >>>>>> completed. >>>>>> >>>>>> Anyway, I'm not really sure what MIPS configurations may benefit fro= m >>>>>> a larger number of MAXCPU. Probabilly XLP should, for what I've hear= d, >>>>>> but I'd like to get a precise mapping between configurations that wa= nt >>>>>> to bump the number and the actual maximum number of CPUs to be >>>>>> supported. >>>>> >>>>> An XLP SoC has 32 cpus (8cores x 4 hw threads per core), and 4 of >>>>> these can be interconnected to have upto 128 cpus. =C2=A0We have an X= LP >>>>> port running on one chip with 32cpus, but there is interest in trying >>>>> out 2 chip (64cpus) and 4 chip(128 cpus) configurations, so this is >>>>> something I want to do when I get access to multi-chip boards for >>>>> FreeBSD development. >>>> >>>> I'll bump MAXCPU to 128 for XLP then, thanks. >>>> Do you have informations about XLR? >>> >>> For XLR the the MAXCPU should be 32 (8 cores x 4 threads per core on >>> the SoC). We cannot connect multiple chips together like the XLP. >> >> So what do you think about this patch?: >> http://www.freebsd.org/~attilio/maxcpu_bump.diff >> >> I already got Marcel's approval on ia64 part, but I need you review >> the mips bits. > > For the XLP changes, we don't really need 128 for MAXCPU now. =C2=A0The I= CI > interface driver which is needed to connect multiple XLPs together to > get 64/128 cpus have not been checked in yet. =C2=A0I plan to do this a f= ew > months down the line. As I'm going to bump the MAXCPUs for all the architectures now, where needed, I'm not sure why we should not do that now, even if the full support is not ready yet. If you are strongly against the change I won't commit it, otherwise it would be good to bump now, along with amd64 and ia64. Attilio --=20 Peace can only be achieved by understanding - A. Einstein From owner-freebsd-mips@FreeBSD.ORG Tue Jul 19 12:33:39 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id ADDB8106566B; Tue, 19 Jul 2011 12:33:39 +0000 (UTC) (envelope-from c.jayachandran@gmail.com) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx1.freebsd.org (Postfix) with ESMTP id C203A8FC16; Tue, 19 Jul 2011 12:33:38 +0000 (UTC) Received: by wwe6 with SMTP id 6so3909913wwe.31 for ; Tue, 19 Jul 2011 05:33:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=Qadfl2novgUNfUWuSaYl/jGPk83ee6JWpI5OSKlKH2c=; b=YPStDLmt2jGF+7vvfP0PoT68hmUjGR+gzHJAHwaaJdxdJy/PnYZyidH8gvn2sNMQIu P4d4jnX6SXHzCF4W/2B05hnGpe35mYO67Lc1v9DrS7OLARzQs+84bC0AmVdOWJLy+aaV MOnTVID3lsI0AuDdVFhch7OKCIzY4/01qn1SM= MIME-Version: 1.0 Received: by 10.216.234.143 with SMTP id s15mr681348weq.66.1311078817588; Tue, 19 Jul 2011 05:33:37 -0700 (PDT) Received: by 10.216.173.211 with HTTP; Tue, 19 Jul 2011 05:33:37 -0700 (PDT) In-Reply-To: References: Date: Tue, 19 Jul 2011 18:03:37 +0530 Message-ID: From: "Jayachandran C." To: Attilio Rao Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: Warner Losh , freebsd-mips@freebsd.org Subject: Re: Bumping MAXCPU for MIPS configurations X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jul 2011 12:33:39 -0000 On Tue, Jul 19, 2011 at 5:18 PM, Attilio Rao wrote: > 2011/7/19 Jayachandran C. : >> On Tue, Jul 19, 2011 at 6:37 AM, Attilio Rao wrote= : >>> 2011/7/3 Jayachandran C. : >>>> On Wed, Jun 29, 2011 at 4:48 PM, Attilio Rao wro= te: >>>>> 2011/6/29 Jayachandran C. : >>>>>> On Wed, Jun 29, 2011 at 3:10 PM, Attilio Rao w= rote: >>>>>>> [ Please CC me in replies as I'm not subscribed to this mailing lis= t ] >>>>>>> >>>>>>> I'm planning to bump MAXCPU for all the kernel configurations >>>>>>> requiring it, as long as the latest cut of largeSMP changes is >>>>>>> completed. >>>>>>> >>>>>>> Anyway, I'm not really sure what MIPS configurations may benefit fr= om >>>>>>> a larger number of MAXCPU. Probabilly XLP should, for what I've hea= rd, >>>>>>> but I'd like to get a precise mapping between configurations that w= ant >>>>>>> to bump the number and the actual maximum number of CPUs to be >>>>>>> supported. >>>>>> >>>>>> An XLP SoC has 32 cpus (8cores x 4 hw threads per core), and 4 of >>>>>> these can be interconnected to have upto 128 cpus. =A0We have an XLP >>>>>> port running on one chip with 32cpus, but there is interest in tryin= g >>>>>> out 2 chip (64cpus) and 4 chip(128 cpus) configurations, so this is >>>>>> something I want to do when I get access to multi-chip boards for >>>>>> FreeBSD development. >>>>> >>>>> I'll bump MAXCPU to 128 for XLP then, thanks. >>>>> Do you have informations about XLR? >>>> >>>> For XLR the the MAXCPU should be 32 (8 cores x 4 threads per core on >>>> the SoC). We cannot connect multiple chips together like the XLP. >>> >>> So what do you think about this patch?: >>> http://www.freebsd.org/~attilio/maxcpu_bump.diff >>> >>> I already got Marcel's approval on ia64 part, but I need you review >>> the mips bits. >> >> For the XLP changes, we don't really need 128 for MAXCPU now. =A0The ICI >> interface driver which is needed to connect multiple XLPs together to >> get 64/128 cpus have not been checked in yet. =A0I plan to do this a few >> months down the line. > > As I'm going to bump the MAXCPUs for all the architectures now, where > needed, I'm not sure why we should not do that now, even if the full > support is not ready yet. > > If you are strongly against the change I won't commit it, otherwise it > would be good to bump now, along with amd64 and ia64. I have no issues with bumping it up to 128. Thought I would just note that we don't support it yet, and hopefully we can remedy that soon :) JC. From owner-freebsd-mips@FreeBSD.ORG Tue Jul 19 13:05:26 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 3F6F81065673 for ; Tue, 19 Jul 2011 13:05:26 +0000 (UTC) (envelope-from rmh.aybabtu@gmail.com) Received: from mail-iw0-f182.google.com (mail-iw0-f182.google.com [209.85.214.182]) by mx1.freebsd.org (Postfix) with ESMTP id 0C0C38FC12 for ; Tue, 19 Jul 2011 13:05:25 +0000 (UTC) Received: by iwr19 with SMTP id 19so4930714iwr.13 for ; Tue, 19 Jul 2011 06:05:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:date:x-google-sender-auth:message-id:subject :from:to:content-type; bh=sa8JiliKYz67JA1VmKrZOJIlRML+f5B+oKNx2Kx3+hE=; b=sgMTKoC37htZTnzeBViOLIndRp2GaWf7H1Ek9yl5l6eZAdkwLFOJTV7LlhMZjR5zaV mG1t6WQgnG83x1Az5vVUToyjSmteMhXOoLXyyEJlEVmaS18nQeQNDa5+z3C2lqb0QUcb x3zyU7kll2ecoVP/3D1imvK+NQwsBP9k2Uans= MIME-Version: 1.0 Received: by 10.43.134.8 with SMTP id ia8mr834177icc.113.1311080725175; Tue, 19 Jul 2011 06:05:25 -0700 (PDT) Sender: rmh.aybabtu@gmail.com Received: by 10.42.224.70 with HTTP; Tue, 19 Jul 2011 06:05:25 -0700 (PDT) Date: Tue, 19 Jul 2011 15:05:25 +0200 X-Google-Sender-Auth: K_6vHdfDyQ_YXUAzmwLXsaQT190 Message-ID: From: Robert Millan To: freebsd-mips@freebsd.org Content-Type: multipart/mixed; boundary=20cf307cfecce55e2d04a86bc436 Subject: [PATCH] _MIPS_SIM builtin macro X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jul 2011 13:05:26 -0000 --20cf307cfecce55e2d04a86bc436 Content-Type: text/plain; charset=UTF-8 Hi, Please could you define the _MIPS_SIM builtin macro on MIPS platforms? It is defined in recent versions of GCC. -- Robert Millan --20cf307cfecce55e2d04a86bc436 Content-Type: text/x-patch; charset=US-ASCII; name="mips_abi.diff" Content-Disposition: attachment; filename="mips_abi.diff" Content-Transfer-Encoding: base64 X-Attachment-Id: f_gqavkz210 SW5kZXg6IGNvbnRyaWIvZ2NjL2NvbmZpZy9taXBzL21pcHMuaAo9PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09Ci0tLSBjb250 cmliL2djYy9jb25maWcvbWlwcy9taXBzLmgJKHJldmlzaW9uIDIyNDAyNSkKKysrIGNvbnRyaWIv Z2NjL2NvbmZpZy9taXBzL21pcHMuaAkod29ya2luZyBjb3B5KQpAQCAtMzkwLDcgKzM5MCwzMCBA QAogCSAgYnVpbHRpbl9kZWZpbmUgKCJfX21pcHNfaXNhX3Jldj0yIik7CQkJXAogCSAgYnVpbHRp bl9kZWZpbmUgKCJfTUlQU19JU0E9X01JUFNfSVNBX01JUFM2NCIpOwlcCiAJfQkJCQkJCQlcCisg ICAgICAJCQkJCQkJCVwKKyAgICAgIHN3aXRjaCAobWlwc19hYmkpCQkJCQkJXAorCXsJCQkJCQkJ XAorCWNhc2UgQUJJXzMyOgkJCQkJCVwKKwkgIGJ1aWx0aW5fZGVmaW5lICgiX0FCSU8zMj0xIik7 CQkJCVwKKwkgIGJ1aWx0aW5fZGVmaW5lICgiX01JUFNfU0lNPV9BQklPMzIiKTsJCQlcCisJICBi cmVhazsJCQkJCQlcCiAJCQkJCQkJCVwKKwljYXNlIEFCSV9OMzI6CQkJCQkJXAorCSAgYnVpbHRp bl9kZWZpbmUgKCJfQUJJTjMyPTIiKTsJCQkJXAorCSAgYnVpbHRpbl9kZWZpbmUgKCJfTUlQU19T SU09X0FCSU4zMiIpOwkJCVwKKwkgIGJyZWFrOwkJCQkJCVwKKwkJCQkJCQkJXAorCWNhc2UgQUJJ XzY0OgkJCQkJCVwKKwkgIGJ1aWx0aW5fZGVmaW5lICgiX0FCSTY0PTMiKTsJCQkJXAorCSAgYnVp bHRpbl9kZWZpbmUgKCJfTUlQU19TSU09X0FCSTY0Iik7CQkJXAorCSAgYnJlYWs7CQkJCQkJXAor CQkJCQkJCQlcCisJY2FzZSBBQklfTzY0OgkJCQkJCVwKKwkgIGJ1aWx0aW5fZGVmaW5lICgiX0FC SU82ND00Iik7CQkJCVwKKwkgIGJ1aWx0aW5fZGVmaW5lICgiX01JUFNfU0lNPV9BQklPNjQiKTsJ CQlcCisJICBicmVhazsJCQkJCQlcCisJfQkJCQkJCQlcCisJCQkJCQkJCVwKICAgICAgIGlmIChU QVJHRVRfSEFSRF9GTE9BVCkJCQkJCVwKIAlidWlsdGluX2RlZmluZSAoIl9fbWlwc19oYXJkX2Zs b2F0Iik7CQkJXAogICAgICAgZWxzZSBpZiAoVEFSR0VUX1NPRlRfRkxPQVQpCQkJCVwK --20cf307cfecce55e2d04a86bc436-- From owner-freebsd-mips@FreeBSD.ORG Tue Jul 19 13:56:48 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id AEA11106564A for ; Tue, 19 Jul 2011 13:56:48 +0000 (UTC) (envelope-from c.jayachandran@gmail.com) Received: from mail-ww0-f50.google.com (mail-ww0-f50.google.com [74.125.82.50]) by mx1.freebsd.org (Postfix) with ESMTP id 424798FC0A for ; Tue, 19 Jul 2011 13:56:48 +0000 (UTC) Received: by wwe6 with SMTP id 6so3988606wwe.31 for ; Tue, 19 Jul 2011 06:56:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; bh=GskLb7BXkq3pE7NjiluiLcAckc2QdBesf/3Ay6g82OE=; b=E1P5c3n6lvjGIN9hb5RF2oCJP1V0ookGg9UqMSF41UUTEEZvtAguk3R9Y0bcTBKi6F gyxLhVR80PDg7+U89VWIieGyasHxUAKoHoHxCsX5qbkW7ua5qntGHit7GDCkWpgDe+EB /NEmwC5ClQ5DWF0LvF6uIr6b1fbweEcOReS/g= MIME-Version: 1.0 Received: by 10.216.155.134 with SMTP id j6mr6896663wek.81.1311083807175; Tue, 19 Jul 2011 06:56:47 -0700 (PDT) Received: by 10.216.173.211 with HTTP; Tue, 19 Jul 2011 06:56:47 -0700 (PDT) In-Reply-To: References: Date: Tue, 19 Jul 2011 19:26:47 +0530 Message-ID: From: "Jayachandran C." To: Robert Millan Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: freebsd-mips@freebsd.org Subject: Re: [PATCH] _MIPS_SIM builtin macro X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jul 2011 13:56:48 -0000 On Tue, Jul 19, 2011 at 6:35 PM, Robert Millan wrote: > Hi, > > Please could you define the _MIPS_SIM builtin macro on MIPS platforms? = =A0It is > defined in recent versions of GCC. The macros seems to be already there, or am I missing something here? [jc@daemon]$ make buildenv Entering world for mips64eb:mips $ touch /tmp/x.c $ gcc -dM -E /tmp/x.c | grep SIM #define _MIPS_SIM _ABI64 JC. From owner-freebsd-mips@FreeBSD.ORG Tue Jul 19 14:03:08 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 5EA4C1065670 for ; Tue, 19 Jul 2011 14:03:08 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id 1EF348FC19 for ; Tue, 19 Jul 2011 14:03:08 +0000 (UTC) Received: from 63.imp.bsdimp.com (63.imp.bsdimp.com [10.0.0.63]) (authenticated bits=0) by harmony.bsdimp.com (8.14.4/8.14.3) with ESMTP id p6JDvl6g092234 (version=TLSv1/SSLv3 cipher=DHE-DSS-AES128-SHA bits=128 verify=NO); Tue, 19 Jul 2011 07:57:47 -0600 (MDT) (envelope-from imp@bsdimp.com) Mime-Version: 1.0 (Apple Message framework v1084) Content-Type: text/plain; charset=us-ascii From: Warner Losh In-Reply-To: Date: Tue, 19 Jul 2011 07:57:43 -0600 Content-Transfer-Encoding: quoted-printable Message-Id: <7F95A706-5FC7-4172-8330-1A3D45C84D22@bsdimp.com> References: To: Robert Millan X-Mailer: Apple Mail (2.1084) X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.0.1 (harmony.bsdimp.com [10.0.0.6]); Tue, 19 Jul 2011 07:57:47 -0600 (MDT) Cc: freebsd-mips@freebsd.org Subject: Re: [PATCH] _MIPS_SIM builtin macro X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jul 2011 14:03:08 -0000 I like it. Thanks! Warner On Jul 19, 2011, at 7:05 AM, Robert Millan wrote: > Hi, >=20 > Please could you define the _MIPS_SIM builtin macro on MIPS platforms? = It is > defined in recent versions of GCC. >=20 > --=20 > Robert Millan > _______________________________________________ > freebsd-mips@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-mips > To unsubscribe, send any mail to = "freebsd-mips-unsubscribe@freebsd.org" From owner-freebsd-mips@FreeBSD.ORG Tue Jul 19 14:06:30 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id CD4C51065679 for ; Tue, 19 Jul 2011 14:06:30 +0000 (UTC) (envelope-from rmh.aybabtu@gmail.com) Received: from mail-iy0-f182.google.com (mail-iy0-f182.google.com [209.85.210.182]) by mx1.freebsd.org (Postfix) with ESMTP id 986FC8FC0A for ; Tue, 19 Jul 2011 14:06:30 +0000 (UTC) Received: by iyb11 with SMTP id 11so5007929iyb.13 for ; Tue, 19 Jul 2011 07:06:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=ueCrPlYoqi+j81ME8rutH00bHynrgdWaxkHjpuUtgrQ=; b=hCaqGy3dt2HzqFF+COmT0GovSg8W7I3zoWUKr0pwSit6A3WUG9hqEwh7ei1Dt656e/ MluWqQOGgMH+5yWM+Zp9qNJADAYklNGS454DxWiOMwdxyFR2kB5Txecfq72ckR74XuxJ xKe5VAyTBpr+T0Xq49mugWBN9S9PElhR4C2D4= MIME-Version: 1.0 Received: by 10.42.73.9 with SMTP id q9mr9146161icj.314.1311084389905; Tue, 19 Jul 2011 07:06:29 -0700 (PDT) Sender: rmh.aybabtu@gmail.com Received: by 10.42.224.70 with HTTP; Tue, 19 Jul 2011 07:06:29 -0700 (PDT) In-Reply-To: References: Date: Tue, 19 Jul 2011 16:06:29 +0200 X-Google-Sender-Auth: DUfVSuv2lfXdnPoo6p56_UKHFwI Message-ID: From: Robert Millan To: "Jayachandran C." Content-Type: text/plain; charset=UTF-8 Cc: freebsd-mips@freebsd.org Subject: Re: [PATCH] _MIPS_SIM builtin macro X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jul 2011 14:06:30 -0000 2011/7/19 Jayachandran C. : > The macros seems to be already there, or am I missing something here? > > [jc@daemon]$ make buildenv > Entering world for mips64eb:mips > $ touch /tmp/x.c > $ gcc -dM -E /tmp/x.c | grep SIM > #define _MIPS_SIM _ABI64 My bad. I checked gcc/config/mips/mips.h, but in FreeBSD tree they're implemented as OS-specific macros. I should have grepped in the whole tree. Sorry. -- Robert Millan From owner-freebsd-mips@FreeBSD.ORG Tue Jul 19 14:27:31 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 962301065675 for ; Tue, 19 Jul 2011 14:27:31 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id 524948FC0A for ; Tue, 19 Jul 2011 14:27:31 +0000 (UTC) Received: from 63.imp.bsdimp.com (63.imp.bsdimp.com [10.0.0.63]) (authenticated bits=0) by harmony.bsdimp.com (8.14.4/8.14.3) with ESMTP id p6JENr7R092474 (version=TLSv1/SSLv3 cipher=DHE-DSS-AES128-SHA bits=128 verify=NO); Tue, 19 Jul 2011 08:23:54 -0600 (MDT) (envelope-from imp@bsdimp.com) Mime-Version: 1.0 (Apple Message framework v1084) Content-Type: text/plain; charset=us-ascii From: Warner Losh In-Reply-To: Date: Tue, 19 Jul 2011 08:23:49 -0600 Content-Transfer-Encoding: 7bit Message-Id: References: To: Robert Millan X-Mailer: Apple Mail (2.1084) X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.0.1 (harmony.bsdimp.com [10.0.0.6]); Tue, 19 Jul 2011 08:23:54 -0600 (MDT) Cc: freebsd-mips@freebsd.org Subject: Re: [PATCH] _MIPS_SIM builtin macro X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jul 2011 14:27:31 -0000 On Jul 19, 2011, at 8:06 AM, Robert Millan wrote: > 2011/7/19 Jayachandran C. : >> The macros seems to be already there, or am I missing something here? >> >> [jc@daemon]$ make buildenv >> Entering world for mips64eb:mips >> $ touch /tmp/x.c >> $ gcc -dM -E /tmp/x.c | grep SIM >> #define _MIPS_SIM _ABI64 > > My bad. I checked gcc/config/mips/mips.h, but in FreeBSD tree they're > implemented as OS-specific macros. I should have grepped in the whole > tree. That likely is a bug, but maybe not one worth fixing :) Warner From owner-freebsd-mips@FreeBSD.ORG Tue Jul 19 15:50:37 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 3A3E4106564A for ; Tue, 19 Jul 2011 15:50:37 +0000 (UTC) (envelope-from rmh.aybabtu@gmail.com) Received: from mail-iy0-f182.google.com (mail-iy0-f182.google.com [209.85.210.182]) by mx1.freebsd.org (Postfix) with ESMTP id 0B3CE8FC1B for ; Tue, 19 Jul 2011 15:50:35 +0000 (UTC) Received: by iyb11 with SMTP id 11so5126715iyb.13 for ; Tue, 19 Jul 2011 08:50:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:date:x-google-sender-auth:message-id:subject :from:to:content-type; bh=l7baGOMVRqfbaEZPpMMgn3EpuwFtGnR62Fl9bMUwdb0=; b=ZwbWkwsei7h5Dz+7Xh+hbelnHhqhZ2HB+buM+Ytqms0kG+R8dFHk+hAQsdfK9DMAn4 thfV7W7n43VSYv5mCg6k+00Qz4jMMhLqj12yhTEK+eQvXc6fRpz02Zy0Z0iC5QKSvWoM Nsl2EtcwlsGCRBPxPqYiJc0NU/GUpJXAXKeRA= MIME-Version: 1.0 Received: by 10.42.147.65 with SMTP id m1mr7222149icv.46.1311090634745; Tue, 19 Jul 2011 08:50:34 -0700 (PDT) Sender: rmh.aybabtu@gmail.com Received: by 10.42.224.70 with HTTP; Tue, 19 Jul 2011 08:50:34 -0700 (PDT) Date: Tue, 19 Jul 2011 17:50:34 +0200 X-Google-Sender-Auth: cj1d0626eentH5SMDummGtKoTHk Message-ID: From: Robert Millan To: freebsd-mips@freebsd.org Content-Type: text/plain; charset=UTF-8 Subject: hang on QEMU after ATA probe X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jul 2011 15:50:37 -0000 After the ATA probe phase, build from 9-CURRENT (MALTA flavour) gets stuck in QEMU but not in GXEMUL. On GXEMUL it proceeds to "Trying to mount root" message while on QEMU it doesn't. Debug messages from ATA probe are a bit different: --- GXEMUL 2011-07-19 17:46:18.548381982 +0200 +++ QEMU 2011-07-19 17:45:26.248582706 +0200 @@ -2,8 +2,8 @@ ata0: stat0=0x00 err=0x00 lsb=0x00 msb=0x00 ata0: stat1=0x00 err=0x00 lsb=0x00 msb=0x00 ata0: reset tp2 stat0=00 stat1=00 devices=0x0 -ata1: reset tp1 mask=03 ostat0=00 ostat1=00 -ata1: stat0=0x00 err=0x00 lsb=0x00 msb=0x00 -ata1: stat1=0x00 err=0x00 lsb=0x00 msb=0x00 -ata1: reset tp2 stat0=00 stat1=00 devices=0x0 -Trying to mount root from ufs:ada0s1a []... +ata1: reset tp1 mask=03 ostat0=50 ostat1=00 +ata1: stat0=0x00 err=0x01 lsb=0x14 msb=0xeb +ata1: stat1=0x00 err=0x00 lsb=0xff msb=0xff +ata1: reset tp2 stat0=00 stat1=00 devices=0x10000 +(aprobe1:ata1:0:0:0): SIGNATURE: eb14 Any idea what's going on? -- Robert Millan From owner-freebsd-mips@FreeBSD.ORG Wed Jul 20 07:39:20 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id ABDD61065673 for ; Wed, 20 Jul 2011 07:39:20 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-yw0-f54.google.com (mail-yw0-f54.google.com [209.85.213.54]) by mx1.freebsd.org (Postfix) with ESMTP id 6CEEE8FC0A for ; Wed, 20 Jul 2011 07:39:20 +0000 (UTC) Received: by ywf7 with SMTP id 7so2604443ywf.13 for ; Wed, 20 Jul 2011 00:39:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=2DrTX+T16uUE4MfpXKj9HvZTUa4SNfJsnRfCOHxYiyk=; b=mqO/TEEAmOilWmeYLseqkgPcGEyktJPKVstE+tfmpR/NOuhwHGdA7TOJL8dA7/MIn2 t5R0xrt7PK+yxtGGJ3A8KenQ9kPeEz7Oi4wRd1nMMQJ5rerVSylE1DPhoRrFwnaAeHGG ZOaHQ/Nl7ptjZ4fpcPbFBlmyS8xN2VBYdKGq8= MIME-Version: 1.0 Received: by 10.150.74.3 with SMTP id w3mr7676794yba.329.1311147559584; Wed, 20 Jul 2011 00:39:19 -0700 (PDT) Sender: adrian.chadd@gmail.com Received: by 10.150.197.5 with HTTP; Wed, 20 Jul 2011 00:39:19 -0700 (PDT) In-Reply-To: <20110715152210.88db1c98.ray@dlink.ua> References: <20110715152210.88db1c98.ray@dlink.ua> Date: Wed, 20 Jul 2011 15:39:19 +0800 X-Google-Sender-Auth: 4dgGjCCwQ_4dncyGi1NVgqvN6gg Message-ID: From: Adrian Chadd To: Aleksandr Rybalko Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: freebsd-mips@freebsd.org Subject: Re: dev/flash patch X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jul 2011 07:39:20 -0000 That's fine to me. Just read this: http://wiki.freebsd.org/Releng/ChangeRequestGuidelines Then write up what is required, email re@ to get approval. Thanks, Adrian On 15 July 2011 20:22, Aleksandr Rybalko wrote: > Hi all, > > I have proposal to tidy mx25l driver, since he have macro's that called > M25PXX_*. That name match a real(world known) name, but seems renaming > whole driver is bigger pain than use well known for our users. > > Please let me know, if someone have objections or opinion differ from > my. > > Patch: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> > Index: sys/dev/flash/mx25l.c > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- sys/dev/flash/mx25l.c =A0 =A0 =A0 (revision 223926) > +++ sys/dev/flash/mx25l.c =A0 =A0 =A0 (working copy) > @@ -79,14 +79,14 @@ > =A0 =A0 =A0 =A0unsigned int =A0 =A0sc_flags; > =A0}; > > -#define M25PXX_LOCK(_sc) =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtx_lock(&(_sc)->sc= _mtx) > -#define =A0 =A0 =A0 =A0M25PXX_UNLOCK(_sc) =A0 =A0 =A0 =A0 =A0 =A0 =A0mtx= _unlock(& > (_sc)->sc_mtx) -#define M25PXX_LOCK_INIT(_sc) \ > +#define MX25L_LOCK(_sc) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0mtx_lock(&(_sc)->= sc_mtx) > +#define =A0 =A0 =A0 =A0MX25L_UNLOCK(_sc) =A0 =A0 =A0 =A0 =A0 =A0 =A0 mtx= _unlock(& > (_sc)->sc_mtx) +#define MX25L_LOCK_INIT(_sc) \ > =A0 =A0 =A0 =A0mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ > =A0 =A0 =A0 =A0 =A0 =A0"mx25l", MTX_DEF) > -#define M25PXX_LOCK_DESTROY(_sc) =A0 =A0 =A0 mtx_destroy(&_sc->sc_mtx); > -#define M25PXX_ASSERT_LOCKED(_sc) =A0 =A0 =A0mtx_assert(&_sc->sc_mtx, > MA_OWNED); -#define M25PXX_ASSERT_UNLOCKED(_sc) mtx_assert > (&_sc->sc_mtx, MA_NOTOWNED); +#define MX25L_LOCK_DESTROY(_sc) > mtx_destroy(&_sc->sc_mtx); +#define MX25L_ASSERT_LOCKED(_sc) > mtx_assert(&_sc->sc_mtx, MA_OWNED); +#define MX25L_ASSERT_UNLOCKED(_sc) > mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); > =A0/* disk routines */ > =A0static int mx25l_open(struct disk *dp); > @@ -356,7 +356,7 @@ > > =A0 =A0 =A0 =A0sc =3D device_get_softc(dev); > =A0 =A0 =A0 =A0sc->sc_dev =3D dev; > - =A0 =A0 =A0 M25PXX_LOCK_INIT(sc); > + =A0 =A0 =A0 MX25L_LOCK_INIT(sc); > > =A0 =A0 =A0 =A0ident =3D mx25l_get_device_ident(sc); > =A0 =A0 =A0 =A0if (ident =3D=3D NULL) > @@ -427,10 +427,10 @@ > =A0 =A0 =A0 =A0struct mx25l_softc *sc; > > =A0 =A0 =A0 =A0sc =3D (struct mx25l_softc *)bp->bio_disk->d_drv1; > - =A0 =A0 =A0 M25PXX_LOCK(sc); > + =A0 =A0 =A0 MX25L_LOCK(sc); > =A0 =A0 =A0 =A0bioq_disksort(&sc->sc_bio_queue, bp); > =A0 =A0 =A0 =A0wakeup(sc); > - =A0 =A0 =A0 M25PXX_UNLOCK(sc); > + =A0 =A0 =A0 MX25L_UNLOCK(sc); > =A0} > > =A0static void > @@ -442,14 +442,14 @@ > > =A0 =A0 =A0 =A0for (;;) { > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0dev =3D sc->sc_dev; > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 M25PXX_LOCK(sc); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 MX25L_LOCK(sc); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0do { > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bp =3D bioq_first(&sc->sc_= bio_queue); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (bp =3D=3D NULL) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0msleep(sc,= &sc->sc_mtx, PRIBIO, > "jobqueue", 0); } while (bp =3D=3D NULL); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bioq_remove(&sc->sc_bio_queue, bp); > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 M25PXX_UNLOCK(sc); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 MX25L_UNLOCK(sc); > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0switch (bp->bio_cmd) { > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0case BIO_READ: >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> > > -- > Alexandr Rybalko > aka Alex RAY > _______________________________________________ > freebsd-mips@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-mips > To unsubscribe, send any mail to "freebsd-mips-unsubscribe@freebsd.org" >