From owner-svn-src-stable-7@FreeBSD.ORG Mon May 2 08:31:53 2011 Return-Path: Delivered-To: svn-src-stable-7@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id D718D106566C; Mon, 2 May 2011 08:31:53 +0000 (UTC) (envelope-from mm@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id C31E58FC0C; Mon, 2 May 2011 08:31:53 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id p428VrFZ028846; Mon, 2 May 2011 08:31:53 GMT (envelope-from mm@svn.freebsd.org) Received: (from mm@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id p428VroZ028836; Mon, 2 May 2011 08:31:53 GMT (envelope-from mm@svn.freebsd.org) Message-Id: <201105020831.p428VroZ028836@svn.freebsd.org> From: Martin Matuska Date: Mon, 2 May 2011 08:31:53 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-7@freebsd.org X-SVN-Group: stable-7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r221317 - in stable/7: contrib/gcc contrib/gcc/config/i386 contrib/gcc/config/mips contrib/gcc/config/rs6000 contrib/gcc/config/s390 contrib/gcc/cp contrib/gcc/doc contrib/libstdc++ con... X-BeenThere: svn-src-stable-7@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for only the 7-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 May 2011 08:31:54 -0000 Author: mm Date: Mon May 2 08:31:53 2011 New Revision: 221317 URL: http://svn.freebsd.org/changeset/base/221317 Log: MFC 218895, 218896, 219374, 219376, 219639, 219640, 219697, 219711, 220150: MFC r218895: Backport svn r124339 from gcc 4.3 and add opteron-sse3, athlon64-sse3 and k8-sse3 cpu-types for -march=/-mtune= gcc options. These new cpu-types include the SSE3 instruction set that is supported by all newer AMD Athlon 64 and Opteron processors. All three cpu-types are supported by clang and all gcc versions starting with 4.3 SVN rev 124339 (at that time GPLv2 licensed). Source: gcc-4_3-branch (rev. 124339; GPLv2) MFC r218896: Add opteron-sse3, athlon64-sse3 and k8-sse3 cpu types to bsd.cpu.mk. - add "sse3" to MACHINE_CPU for the new cpu types - for i386, default to CPUTYPE=prescott for the new cpu types MFC r219374: Backport Intel Core 2 and AMD Geode CPU types from gcc-4.3 (GPLv2) These options are supported in this shape in all newer GCC versions. Source: gcc-4_3-branch (rev. 118090, 118973, 120846; GPLv2) MFC r219376: Add AMD Geode CPU type to bsd.cpu.mk and examples/etc/make.conf For CPUTYPE=core2 use -march=core2 MFC r219639: Backport SSSE3 instruction set support to base gcc. Enabled by default for -march=core2 Source: gcc-4_3-branch (rev. 117958, 121687, 121726, 123639; GPLv2) MFC r219640: Add ssse3 capability for CPUTYPE=core2 to MACHINE_CPU in bsd.cpu.mk MFC r219697: Fix -march/-mtune=native autodetection for Intel Core 2 CPUs Source: gcc-4_3-branch (partial rev. 119454; GPLv2) MFC r219711: Backport missing tunings for -march=core2: - enable extra 80387 mathematical constants (ext_80387_constants) - enable compare and exchange 16 bytes (cmpxchg16b) Verified against llvm-gcc (and apple gcc) Source: gcc-4_3-branch (ref. svn revs. 119260, 121140; GPLv2) MFC r220150: Upgrade of base gcc and libstdc++ to the last GPLv2-licensed revision (rev. 127959 of gcc-4_2-branch). Resolved GCC bugs: c++: 17763, 29365, 30535, 30917, 31337, 31941, 32108, 32112, 32346, 32898, 32992 debug: 32610, 32914 libstdc++: 33084, 33128 middle-end: 32563 rtl-optimization: 33148 tree-optimization: 25413, 32723 target: 32218 Source: gcc-4_2-branch (up to rev. 127959) Obtained from: gcc (var. revs of gcc-4_2-branch and gcc-4_3-branch; GPLv2) PR: gnu/153298, gnu/153959, gnu/154385, gnu/155308, gnu/154906 Added: stable/7/contrib/gcc/config/i386/geode.md - copied unchanged from r219374, head/contrib/gcc/config/i386/geode.md stable/7/contrib/gcc/config/i386/tmmintrin.h - copied unchanged from r219639, head/contrib/gcc/config/i386/tmmintrin.h Modified: stable/7/contrib/gcc/BASE-VER stable/7/contrib/gcc/ChangeLog stable/7/contrib/gcc/DATESTAMP stable/7/contrib/gcc/DEV-PHASE stable/7/contrib/gcc/config.gcc stable/7/contrib/gcc/config/i386/driver-i386.c stable/7/contrib/gcc/config/i386/i386.c stable/7/contrib/gcc/config/i386/i386.h stable/7/contrib/gcc/config/i386/i386.md stable/7/contrib/gcc/config/i386/i386.opt stable/7/contrib/gcc/config/i386/sse.md stable/7/contrib/gcc/config/i386/xmmintrin.h stable/7/contrib/gcc/config/mips/predicates.md stable/7/contrib/gcc/config/rs6000/rs6000.c stable/7/contrib/gcc/config/s390/s390.md stable/7/contrib/gcc/cp/ChangeLog stable/7/contrib/gcc/cp/call.c stable/7/contrib/gcc/cp/cp-tree.h stable/7/contrib/gcc/cp/cxx-pretty-print.c stable/7/contrib/gcc/cp/decl.c stable/7/contrib/gcc/cp/decl2.c stable/7/contrib/gcc/cp/error.c stable/7/contrib/gcc/cp/lex.c stable/7/contrib/gcc/cp/name-lookup.c stable/7/contrib/gcc/cp/pt.c stable/7/contrib/gcc/cp/semantics.c stable/7/contrib/gcc/cp/typeck.c stable/7/contrib/gcc/doc/contrib.texi stable/7/contrib/gcc/doc/extend.texi stable/7/contrib/gcc/doc/gcc.1 stable/7/contrib/gcc/doc/invoke.texi stable/7/contrib/gcc/dwarf2out.c stable/7/contrib/gcc/expr.c stable/7/contrib/gcc/fold-const.c stable/7/contrib/gcc/gimplify.c stable/7/contrib/gcc/reload1.c stable/7/contrib/gcc/simplify-rtx.c stable/7/contrib/gcc/target-def.h stable/7/contrib/gcc/target.h stable/7/contrib/gcc/targhooks.c stable/7/contrib/gcc/targhooks.h stable/7/contrib/gcc/tree-if-conv.c stable/7/contrib/gcc/tree-ssa-structalias.c stable/7/contrib/gcc/tree-vect-analyze.c stable/7/contrib/gcc/tree-vect-patterns.c stable/7/contrib/gcc/tree.c stable/7/contrib/gcc/tree.h stable/7/contrib/libstdc++/ChangeLog stable/7/contrib/libstdc++/include/std/std_valarray.h stable/7/contrib/libstdc++/include/tr1/random stable/7/share/examples/etc/make.conf stable/7/share/mk/bsd.cpu.mk Directory Properties: stable/7/contrib/gcc/ (props changed) stable/7/contrib/libstdc++/ (props changed) stable/7/share/examples/ (props changed) stable/7/share/mk/ (props changed) Modified: stable/7/contrib/gcc/BASE-VER ============================================================================== --- stable/7/contrib/gcc/BASE-VER Mon May 2 06:59:09 2011 (r221316) +++ stable/7/contrib/gcc/BASE-VER Mon May 2 08:31:53 2011 (r221317) @@ -1 +1 @@ -4.2.1 +4.2.2 Modified: stable/7/contrib/gcc/ChangeLog ============================================================================== --- stable/7/contrib/gcc/ChangeLog Mon May 2 06:59:09 2011 (r221316) +++ stable/7/contrib/gcc/ChangeLog Mon May 2 08:31:53 2011 (r221317) @@ -1,3 +1,121 @@ +2007-08-31 Jakub Jelinek + + PR rtl-optimization/33148 + * simplify-rtx.c (simplify_unary_operation_1): Only optimize + (neg (lt X 0)) if X has scalar int mode. + + PR debug/32914 + * dwarf2out.c (rtl_for_decl_init): If vector decl has CONSTRUCTOR + initializer, use build_vector_from_ctor if possible to create + VECTOR_CST out of it. If vector initializer is not VECTOR_CST + even after this, return NULL. + +2007-08-27 Jason Merrill + + PR c++/31337 + * gimplify.c (gimplify_modify_expr): Discard the assignment of + zero-sized types after calling gimplify_modify_expr_rhs. + +2007-08-24 Jakub Jelinek + + PR debug/32610 + * dwarf2out.c (gen_decl_die): Don't call + gen_tagged_type_instantiation_die if decl doesn't have tagged type. + +2007-08-24 Richard Guenther + + * expr.c (get_inner_reference): Remove unused variable. + +2007-08-24 Richard Guenther + + * expr.c (get_inner_reference): Do computation of bitoffset + from offset in a way we can detect overflow reliably. + +2007-08-22 Richard Guenther + + PR middle-end/32563 + * tree.c (host_integerp): Treat sizetype as signed as it is + sign-extended. + +2007-08-20 Adam Nemet + + * config/mips/predicates.md (const_call_insn_operand): Invoke + SYMBOL_REF_LONG_CALL_P only on SYMBOL_REFs. + +2007-08-17 Chen liqin + + * config/score/score.md : Update pattern tablejump. + * config/score/score.c : Update score_initialize_trampoline + function. + * config/score/score.h (TRAMPOLINE_TEMPLATE): Added macro. + (TRAMPOLINE_INSNS, TRAMPOLINE_SIZE) Update macro. + * doc/contrib.texi: Add my entry. + +2007-08-02 Andreas Krebbel + + * config/s390/s390.md ("*xordi3_cconly"): Change xr to xg. + +2007-08-01 Andreas Krebbel + + * config/s390/s390.md (TF in GPR splitter): Change operand_subword + parameter to TFmode. + +2007-07-30 Mark Mitchell + + * BASE-VER: Bump. + * DEV-PHASE: Mark as prerelease. + +2007-07-25 Steve Ellcey + + PR target/32218 + * tree-vect-patterns.c (vect_pattern_recog_1): Check for valid type. + +2007-07-25 Dorit Nuzman + Devang Patel + + PR tree-optimization/25413 + * targhooks.c (default_builtin_vector_alignment_reachable): New. + * targhooks.h (default_builtin_vector_alignment_reachable): New. + * tree.h (contains_packed_reference): New. + * expr.c (contains_packed_reference): New. + * tree-vect-analyze.c (vector_alignment_reachable_p): New. + (vect_enhance_data_refs_alignment): Call + vector_alignment_reachable_p. + * target.h (vector_alignment_reachable): New builtin. + * target-def.h (TARGET_VECTOR_ALIGNMENT_REACHABLE): New. + * config/rs6000/rs6000.c (rs6000_vector_alignment_reachable): New. + (TARGET_VECTOR_ALIGNMENT_REACHABLE): Define. + +2007-07-24 Richard Guenther + + Backport from mainline: + 2007-07-16 Richard Guenther + Uros Bizjak + + * tree-if-conv.c (find_phi_replacement_condition): Unshare "*cond" + before forcing it to gimple operand. + +2007-07-24 Richard Guenther + + PR tree-optimization/32723 + Backport from mainline: + 2007-03-09 Daniel Berlin + + * tree-ssa-structalias.c (shared_bitmap_info_t): New structure. + (shared_bitmap_table): New variable. + (shared_bitmap_hash): New function. + (shared_bitmap_eq): Ditto + (shared_bitmap_lookup): Ditto. + (shared_bitmap_add): Ditto. + (find_what_p_points_to): Rewrite to use shared bitmap hashtable. + (init_alias_vars): Init shared bitmap hashtable. + (delete_points_to_sets): Delete shared bitmap hashtable. + +2007-07-23 Bernd Schmidt + + * reload1.c (choose_reload_regs): Set reload_spill_index for regs + chosen during find_reloads. + 2007-07-19 Release Manager * GCC 4.2.1 released. Modified: stable/7/contrib/gcc/DATESTAMP ============================================================================== --- stable/7/contrib/gcc/DATESTAMP Mon May 2 06:59:09 2011 (r221316) +++ stable/7/contrib/gcc/DATESTAMP Mon May 2 08:31:53 2011 (r221317) @@ -1 +1 @@ -20070719 +20070831 Modified: stable/7/contrib/gcc/DEV-PHASE ============================================================================== --- stable/7/contrib/gcc/DEV-PHASE Mon May 2 06:59:09 2011 (r221316) +++ stable/7/contrib/gcc/DEV-PHASE Mon May 2 08:31:53 2011 (r221317) @@ -0,0 +1 @@ +prerelease Modified: stable/7/contrib/gcc/config.gcc ============================================================================== --- stable/7/contrib/gcc/config.gcc Mon May 2 06:59:09 2011 (r221316) +++ stable/7/contrib/gcc/config.gcc Mon May 2 08:31:53 2011 (r221317) @@ -268,11 +268,13 @@ xscale-*-*) ;; i[34567]86-*-*) cpu_type=i386 - extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h pmmintrin.h" + extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h + pmmintrin.h tmmintrin.h" ;; x86_64-*-*) cpu_type=i386 - extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h pmmintrin.h" + extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h + pmmintrin.h tmmintrin.h" need_64bit_hwint=yes ;; ia64-*-*) @@ -1207,14 +1209,14 @@ i[34567]86-*-solaris2*) # FIXME: -m64 for i[34567]86-*-* should be allowed just # like -m32 for x86_64-*-*. case X"${with_cpu}" in - Xgeneric|Xnocona|Xx86-64|Xk8|Xopteron|Xathlon64|Xathlon-fx) + Xgeneric|Xcore2|Xnocona|Xx86-64|Xk8|Xopteron|Xathlon64|Xathlon-fx) ;; X) with_cpu=generic ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic nocona x86-64 k8 opteron athlon64 athlon-fx" 1>&2 + echo "generic core2 nocona x86-64 k8 opteron athlon64 athlon-fx" 1>&2 exit 1 ;; esac @@ -2537,6 +2539,9 @@ if test x$with_cpu = x ; then nocona-*) with_cpu=nocona ;; + core2-*) + with_cpu=core2 + ;; pentium_m-*) with_cpu=pentium-m ;; @@ -2556,6 +2561,9 @@ if test x$with_cpu = x ; then nocona-*) with_cpu=nocona ;; + core2-*) + with_cpu=core2 + ;; *) with_cpu=generic ;; @@ -2787,7 +2795,7 @@ case "${target}" in esac # OK ;; - "" | k8 | opteron | athlon64 | athlon-fx | nocona | generic) + "" | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | generic) # OK ;; *) Modified: stable/7/contrib/gcc/config/i386/driver-i386.c ============================================================================== --- stable/7/contrib/gcc/config/i386/driver-i386.c Mon May 2 06:59:09 2011 (r221316) +++ stable/7/contrib/gcc/config/i386/driver-i386.c Mon May 2 08:31:53 2011 (r221317) @@ -39,6 +39,7 @@ const char *host_detect_local_cpu (int a #define bit_SSE2 (1 << 26) #define bit_SSE3 (1 << 0) +#define bit_SSSE3 (1 << 9) #define bit_CMPXCHG16B (1 << 13) #define bit_3DNOW (1 << 31) @@ -66,7 +67,7 @@ const char *host_detect_local_cpu (int a unsigned int vendor; unsigned int ext_level; unsigned char has_mmx = 0, has_3dnow = 0, has_3dnowp = 0, has_sse = 0; - unsigned char has_sse2 = 0, has_sse3 = 0, has_cmov = 0; + unsigned char has_sse2 = 0, has_sse3 = 0, has_ssse3 = 0, has_cmov = 0; unsigned char has_longmode = 0, has_cmpxchg8b = 0; unsigned char is_amd = 0; unsigned int family = 0; @@ -107,6 +108,7 @@ const char *host_detect_local_cpu (int a has_sse = !!(edx & bit_SSE); has_sse2 = !!(edx & bit_SSE2); has_sse3 = !!(ecx & bit_SSE3); + has_ssse3 = !!(ecx & bit_SSSE3); /* We don't care for extended family. */ family = (eax >> 8) & ~(1 << 4); @@ -148,7 +150,9 @@ const char *host_detect_local_cpu (int a /* We have no idea. Use something reasonable. */ if (arch) { - if (has_sse3) + if (has_ssse3) + cpu = "core2"; + else if (has_sse3) { if (has_longmode) cpu = "nocona"; @@ -230,6 +234,9 @@ const char *host_detect_local_cpu (int a cpu = "generic"; } break; + case PROCESSOR_GEODE: + cpu = "geode"; + break; case PROCESSOR_K6: if (has_3dnow) cpu = "k6-3"; Copied: stable/7/contrib/gcc/config/i386/geode.md (from r219374, head/contrib/gcc/config/i386/geode.md) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ stable/7/contrib/gcc/config/i386/geode.md Mon May 2 08:31:53 2011 (r221317, copy of r219374, head/contrib/gcc/config/i386/geode.md) @@ -0,0 +1,153 @@ +;; Geode Scheduling +;; Copyright (C) 2006 +;; Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING. If not, write to +;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, +;; Boston, MA 02110-1301, USA. +;; +;; The Geode architecture is one insn issue processor. +;; +;; This description is based on data from the following documents: +;; +;; "AMD Geode GX Processor Data Book" +;; Advanced Micro Devices, Inc., Aug 2005. +;; +;; "AMD Geode LX Processor Data Book" +;; Advanced Micro Devices, Inc., Jan 2006. +;; +;; +;; CPU execution units of the Geode: +;; +;; issue describes the issue pipeline. +;; alu describes the Integer unit +;; fpu describes the FP unit +;; +;; The fp unit is out of order execution unit with register renaming. +;; There is also memory management unit and execution pipeline for +;; load/store operations. We ignore it and difference between insns +;; using memory and registers. + +(define_automaton "geode") + +(define_cpu_unit "geode_issue,geode_alu,geode_fpu" "geode") + +(define_insn_reservation "alu" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "alu,alu1,negnot,icmp,lea,test,imov,imovx,icmov,incdec,setcc")) + "geode_issue,geode_alu") + +(define_insn_reservation "shift" 2 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "ishift,ishift1,rotate,rotate1,cld")) + "geode_issue,geode_alu*2") + +(define_insn_reservation "imul" 7 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "imul")) + "geode_issue,geode_alu*7") + +(define_insn_reservation "idiv" 40 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "idiv")) + "geode_issue,geode_alu*40") + +;; The branch unit. +(define_insn_reservation "call" 2 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "call,callv")) + "geode_issue,geode_alu*2") + +(define_insn_reservation "geode_branch" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "ibr")) + "geode_issue,geode_alu") + +(define_insn_reservation "geode_pop_push" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "pop,push")) + "geode_issue,geode_alu") + +(define_insn_reservation "geode_leave" 2 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "leave")) + "geode_issue,geode_alu*2") + +(define_insn_reservation "geode_load_str" 4 + (and (eq_attr "cpu" "geode") + (and (eq_attr "type" "str") + (eq_attr "memory" "load,both"))) + "geode_issue,geode_alu*4") + +(define_insn_reservation "geode_store_str" 2 + (and (eq_attr "cpu" "geode") + (and (eq_attr "type" "str") + (eq_attr "memory" "store"))) + "geode_issue,geode_alu*2") + +;; Be optimistic +(define_insn_reservation "geode_unknown" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "multi,other")) + "geode_issue,geode_alu") + +;; FPU + +(define_insn_reservation "geode_fop" 6 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fop,fcmp")) + "geode_issue,geode_fpu*6") + +(define_insn_reservation "geode_fsimple" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fmov,fcmov,fsgn,fxch")) + "geode_issue,geode_fpu") + +(define_insn_reservation "geode_fist" 4 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fistp,fisttp")) + "geode_issue,geode_fpu*4") + +(define_insn_reservation "geode_fmul" 10 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fmul")) + "geode_issue,geode_fpu*10") + +(define_insn_reservation "geode_fdiv" 47 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fdiv")) + "geode_issue,geode_fpu*47") + +;; We use minimal latency (fsin) here +(define_insn_reservation "geode_fpspc" 54 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "fpspc")) + "geode_issue,geode_fpu*54") + +(define_insn_reservation "geode_frndint" 12 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "frndint")) + "geode_issue,geode_fpu*12") + +(define_insn_reservation "geode_mmxmov" 1 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "mmxmov")) + "geode_issue,geode_fpu") + +(define_insn_reservation "geode_mmx" 2 + (and (eq_attr "cpu" "geode") + (eq_attr "type" "mmx,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")) + "geode_issue,geode_fpu*2") Modified: stable/7/contrib/gcc/config/i386/i386.c ============================================================================== --- stable/7/contrib/gcc/config/i386/i386.c Mon May 2 06:59:09 2011 (r221316) +++ stable/7/contrib/gcc/config/i386/i386.c Mon May 2 08:31:53 2011 (r221317) @@ -336,6 +336,60 @@ struct processor_costs pentiumpro_cost = }; static const +struct processor_costs geode_cost = { + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1), /* cost of a lea instruction */ + COSTS_N_INSNS (2), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (3), /* cost of starting multiply for QI */ + COSTS_N_INSNS (4), /* HI */ + COSTS_N_INSNS (7), /* SI */ + COSTS_N_INSNS (7), /* DI */ + COSTS_N_INSNS (7)}, /* other */ + 0, /* cost of multiply per each bit set */ + {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (23), /* HI */ + COSTS_N_INSNS (39), /* SI */ + COSTS_N_INSNS (39), /* DI */ + COSTS_N_INSNS (39)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ + 8, /* "large" insn */ + 4, /* MOVE_RATIO */ + 1, /* cost for loading QImode using movzbl */ + {1, 1, 1}, /* cost of loading integer registers + in QImode, HImode and SImode. + Relative to reg-reg move (2). */ + {1, 1, 1}, /* cost of storing integer registers */ + 1, /* cost of reg,reg fld/fst */ + {1, 1, 1}, /* cost of loading fp registers + in SFmode, DFmode and XFmode */ + {4, 6, 6}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ + + 1, /* cost of moving MMX register */ + {1, 1}, /* cost of loading MMX registers + in SImode and DImode */ + {1, 1}, /* cost of storing MMX registers + in SImode and DImode */ + 1, /* cost of moving SSE register */ + {1, 1, 1}, /* cost of loading SSE registers + in SImode, DImode and TImode */ + {1, 1, 1}, /* cost of storing SSE registers + in SImode, DImode and TImode */ + 1, /* MMX or SSE register to integer */ + 32, /* size of prefetch block */ + 1, /* number of parallel prefetches */ + 1, /* Branch cost */ + COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (11), /* cost of FMUL instruction. */ + COSTS_N_INSNS (47), /* cost of FDIV instruction. */ + COSTS_N_INSNS (1), /* cost of FABS instruction. */ + COSTS_N_INSNS (1), /* cost of FCHS instruction. */ + COSTS_N_INSNS (54), /* cost of FSQRT instruction. */ +}; + +static const struct processor_costs k6_cost = { COSTS_N_INSNS (1), /* cost of an add instruction */ COSTS_N_INSNS (2), /* cost of a lea instruction */ @@ -600,6 +654,58 @@ struct processor_costs nocona_cost = { COSTS_N_INSNS (44), /* cost of FSQRT instruction. */ }; +static const +struct processor_costs core2_cost = { + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (3), /* cost of starting multiply for QI */ + COSTS_N_INSNS (3), /* HI */ + COSTS_N_INSNS (3), /* SI */ + COSTS_N_INSNS (3), /* DI */ + COSTS_N_INSNS (3)}, /* other */ + 0, /* cost of multiply per each bit set */ + {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (22), /* HI */ + COSTS_N_INSNS (22), /* SI */ + COSTS_N_INSNS (22), /* DI */ + COSTS_N_INSNS (22)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ + 8, /* "large" insn */ + 16, /* MOVE_RATIO */ + 2, /* cost for loading QImode using movzbl */ + {6, 6, 6}, /* cost of loading integer registers + in QImode, HImode and SImode. + Relative to reg-reg move (2). */ + {4, 4, 4}, /* cost of storing integer registers */ + 2, /* cost of reg,reg fld/fst */ + {6, 6, 6}, /* cost of loading fp registers + in SFmode, DFmode and XFmode */ + {4, 4, 4}, /* cost of loading integer registers */ + 2, /* cost of moving MMX register */ + {6, 6}, /* cost of loading MMX registers + in SImode and DImode */ + {4, 4}, /* cost of storing MMX registers + in SImode and DImode */ + 2, /* cost of moving SSE register */ + {6, 6, 6}, /* cost of loading SSE registers + in SImode, DImode and TImode */ + {4, 4, 4}, /* cost of storing SSE registers + in SImode, DImode and TImode */ + 2, /* MMX or SSE register to integer */ + 128, /* size of prefetch block */ + 8, /* number of parallel prefetches */ + 3, /* Branch cost */ + COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (5), /* cost of FMUL instruction. */ + COSTS_N_INSNS (32), /* cost of FDIV instruction. */ + COSTS_N_INSNS (1), /* cost of FABS instruction. */ + COSTS_N_INSNS (1), /* cost of FCHS instruction. */ + COSTS_N_INSNS (58), /* cost of FSQRT instruction. */ +}; + /* Generic64 should produce code tuned for Nocona and K8. */ static const struct processor_costs generic64_cost = { @@ -721,38 +827,41 @@ const struct processor_costs *ix86_cost #define m_486 (1<mask, d->name, type, d->code); } + /* Add all builtins that are more or less simple operations on 1 operand. */ + for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) + { + enum machine_mode mode; + tree type; + + if (d->name == 0) + continue; + mode = insn_data[d->icode].operand[1].mode; + + switch (mode) + { + case V16QImode: + type = v16qi_ftype_v16qi; + break; + case V8HImode: + type = v8hi_ftype_v8hi; + break; + case V4SImode: + type = v4si_ftype_v4si; + break; + case V2DFmode: + type = v2df_ftype_v2df; + break; + case V4SFmode: + type = v4sf_ftype_v4sf; + break; + case V8QImode: + type = v8qi_ftype_v8qi; + break; + case V4HImode: + type = v4hi_ftype_v4hi; + break; + case V2SImode: + type = v2si_ftype_v2si; + break; + + default: + abort (); + } + + def_builtin (d->mask, d->name, type, d->code); + } + /* Add the remaining MMX insns with somewhat more complicated types. */ def_builtin (MASK_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS); def_builtin (MASK_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW); @@ -15522,6 +15798,12 @@ ix86_init_mmx_sse_builtins (void) def_builtin (MASK_SSE3, "__builtin_ia32_lddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU); + /* SSSE3. */ + def_builtin (MASK_SSSE3, "__builtin_ia32_palignr128", + v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PALIGNR128); + def_builtin (MASK_SSSE3, "__builtin_ia32_palignr", di_ftype_di_di_int, + IX86_BUILTIN_PALIGNR); + /* Access to the vec_init patterns. */ ftype = build_function_type_list (V2SI_type_node, integer_type_node, integer_type_node, NULL_TREE); @@ -16020,7 +16302,7 @@ ix86_expand_builtin (tree exp, rtx targe tree arglist = TREE_OPERAND (exp, 1); tree arg0, arg1, arg2; rtx op0, op1, op2, pat; - enum machine_mode tmode, mode0, mode1, mode2; + enum machine_mode tmode, mode0, mode1, mode2, mode3; unsigned int fcode = DECL_FUNCTION_CODE (fndecl); switch (fcode) @@ -16490,6 +16772,52 @@ ix86_expand_builtin (tree exp, rtx targe return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, arglist, target, 1); + case IX86_BUILTIN_PALIGNR: *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***