From owner-freebsd-arm@FreeBSD.ORG Mon Nov 19 11:06:14 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 8477FB3 for ; Mon, 19 Nov 2012 11:06:14 +0000 (UTC) (envelope-from muhammad.ossaama@gmail.com) Received: from mail-da0-f54.google.com (mail-da0-f54.google.com [209.85.210.54]) by mx1.freebsd.org (Postfix) with ESMTP id 578ED8FC1B for ; Mon, 19 Nov 2012 11:06:14 +0000 (UTC) Received: by mail-da0-f54.google.com with SMTP id z9so2249863dad.13 for ; Mon, 19 Nov 2012 03:06:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:date:message-id:subject:from:to:content-type; bh=9bED8F6HWRkbQ+Ssw9+AQTRsQGHk4OqH2qZ3xlEu/28=; b=CYjXvK9rpOUE3CHNyCjhQlLJVr16gQmbcWZYrpTsAcKcLbk+p6+UHONaR/m6yBYFUg in57y+jkOUNjmar1Kzy2woWVzo4A/TKCQ5SS34/XuULDO1e0EYvytZGYmABt6RTIbBZl OTACupcENO2Jb0YvgjxIE2dZMND8Cygr9LTXe0bX6Qs/xQ/O+O1ci8tiwTnwwBGtQrMq eyXIQT386xpfD93+//2SF97sHx5lEbyySMGrDURnG4qsw0m7X/ycV0u4pL4D3hj6dZLW OwSsaVhe3KoRn29nOYA2Xd0u4o7vKpP8VHAkeJefgrhoN9rRbY4kXUu97z0ST4dogBec 6D4Q== MIME-Version: 1.0 Received: by 10.68.238.199 with SMTP id vm7mr37378802pbc.105.1353323173954; Mon, 19 Nov 2012 03:06:13 -0800 (PST) Received: by 10.66.159.197 with HTTP; Mon, 19 Nov 2012 03:06:13 -0800 (PST) Date: Mon, 19 Nov 2012 13:06:13 +0200 Message-ID: Subject: inquiry From: Muhammad Osama To: freebsd-arm@freebsd.org Content-Type: text/plain; charset=ISO-8859-1 X-Content-Filtered-By: Mailman/MimeDel 2.1.14 X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Nov 2012 11:06:14 -0000 hi, I am Muhammad a astudent at last year of electronics and communication department faculty of engineering. i am very interested in Embedded system in general and developing in linux and unix . i want to interact with freebsd ,but i am still a beginner i have to do a graduation project this year so i want some develoment ideas in freebsd projects so i can choose one thanks in advance. From owner-freebsd-arm@FreeBSD.ORG Mon Nov 19 11:06:41 2012 Return-Path: Delivered-To: freebsd-arm@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id A85CA1B8 for ; Mon, 19 Nov 2012 11:06:41 +0000 (UTC) (envelope-from owner-bugmaster@FreeBSD.org) Received: from freefall.freebsd.org (freefall.freebsd.org [IPv6:2001:1900:2254:206c::16:87]) by mx1.freebsd.org (Postfix) with ESMTP id 8CC828FC1A for ; Mon, 19 Nov 2012 11:06:41 +0000 (UTC) Received: from freefall.freebsd.org (localhost [127.0.0.1]) by freefall.freebsd.org (8.14.5/8.14.5) with ESMTP id qAJB6fwp013232 for ; Mon, 19 Nov 2012 11:06:41 GMT (envelope-from owner-bugmaster@FreeBSD.org) Received: (from gnats@localhost) by freefall.freebsd.org (8.14.5/8.14.5/Submit) id qAJB6frb013230 for freebsd-arm@FreeBSD.org; Mon, 19 Nov 2012 11:06:41 GMT (envelope-from owner-bugmaster@FreeBSD.org) Date: Mon, 19 Nov 2012 11:06:41 GMT Message-Id: <201211191106.qAJB6frb013230@freefall.freebsd.org> X-Authentication-Warning: freefall.freebsd.org: gnats set sender to owner-bugmaster@FreeBSD.org using -f From: FreeBSD bugmaster To: freebsd-arm@FreeBSD.org Subject: Current problem reports assigned to freebsd-arm@FreeBSD.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Nov 2012 11:06:41 -0000 Note: to view an individual PR, use: http://www.freebsd.org/cgi/query-pr.cgi?pr=(number). The following is a listing of current problems submitted by FreeBSD users. These represent problem reports covering all versions including experimental development code and obsolete releases. S Tracker Resp. Description -------------------------------------------------------------------------------- o arm/173617 arm Dreamplug exhibits eSATA file corruption using network o kern/171096 arm [arm][xscale][ixp]Allow 16bit access on PCI bus o arm/166256 arm build fail in pmap.c o arm/162159 arm [panic] USB errors leading to panic on DockStar 9.0-RC o arm/161110 arm /usr/src/sys/arm/include/signal.h is bad o arm/161044 arm devel/icu does not build on arm o arm/158950 arm arm/sheevaplug fails fsx when mmap operations are enab o arm/155894 arm [patch] Enable at91 booting from SDHC (high capacity) p arm/155214 arm [patch] MMC/SD IO slow on Atmel ARM with modern large o arm/154227 arm [geli] using GELI leads to panic on ARM o arm/153380 arm Panic / translation fault with wlan on ARM o arm/150581 arm [irq] Unknown error generates IRQ address decoding err o arm/149288 arm mail/dovecot causes panic during configure on Sheevapl o arm/134368 arm [patch] nslu2_led driver for the LEDs on the NSLU2 p arm/134338 arm [patch] Lock GPIO accesses on ixp425 15 problems total. From owner-freebsd-arm@FreeBSD.ORG Mon Nov 19 12:15:59 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id B3BE1BB for ; Mon, 19 Nov 2012 12:15:59 +0000 (UTC) (envelope-from ronald-freebsd8@klop.yi.org) Received: from smarthost1.greenhost.nl (smarthost1.greenhost.nl [195.190.28.78]) by mx1.freebsd.org (Postfix) with ESMTP id 637388FC15 for ; Mon, 19 Nov 2012 12:15:59 +0000 (UTC) Received: from smtp.greenhost.nl ([213.108.104.138]) by smarthost1.greenhost.nl with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1TaQGV-00066P-HY; Mon, 19 Nov 2012 13:15:51 +0100 Received: from [81.21.138.17] (helo=ronaldradial.versatec.local) by smtp.greenhost.nl with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1TaQGV-0001P1-2g; Mon, 19 Nov 2012 13:15:51 +0100 Content-Type: text/plain; charset=us-ascii; format=flowed; delsp=yes To: freebsd-arm@freebsd.org, "Muhammad Osama" Subject: Re: inquiry References: Date: Mon, 19 Nov 2012 13:15:51 +0100 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: "Ronald Klop" Message-ID: In-Reply-To: User-Agent: Opera Mail/12.10 (Win32) X-Virus-Scanned: by clamav at smarthost1.samage.net X-Spam-Level: / X-Spam-Score: 0.8 X-Spam-Status: No, score=0.8 required=5.0 tests=BAYES_50 autolearn=disabled version=3.3.1 X-Scan-Signature: 523f42b60907f92a5b98f162865e3e4b X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Nov 2012 12:15:59 -0000 On Mon, 19 Nov 2012 12:06:13 +0100, Muhammad Osama wrote: > hi, > > I am Muhammad a astudent at last year of electronics and communication > department faculty of engineering. > > i am very interested in Embedded system in general and developing in > linux > and unix . > i want to interact with freebsd ,but i am still a beginner > i have to do a graduation project this year so i want some develoment > ideas > in freebsd projects so i can choose one > thanks in advance. Take a look here. http://wiki.freebsd.org/IdeasPage Regards, Ronald. From owner-freebsd-arm@FreeBSD.ORG Mon Nov 19 13:53:59 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id C20C4308 for ; Mon, 19 Nov 2012 13:53:59 +0000 (UTC) (envelope-from lists@eitanadler.com) Received: from mail-lb0-f182.google.com (mail-lb0-f182.google.com [209.85.217.182]) by mx1.freebsd.org (Postfix) with ESMTP id 34CB68FC18 for ; Mon, 19 Nov 2012 13:53:58 +0000 (UTC) Received: by mail-lb0-f182.google.com with SMTP id go10so1982759lbb.13 for ; Mon, 19 Nov 2012 05:53:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=eitanadler.com; s=0xdeadbeef; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=DyMpTqPLMdNdaJuzBmgCnLLbJs/25Yb7UM0pJLmooVM=; b=AVw4avOmE4DCoT7btT9rKrHSkFxH2I7moZUGkXsvdnMA06DQ4gejH0HaSN0Um0SXU7 /iRmwWgezG53/y8X+xHR9gwI55g4iiEdBRd7qFbSM0knhbR0Bh6ABTeC55InDp1tVGJE pFbqIx8n3LEl57bsgXWZCdeLsq/IYTWyQGjTY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type:x-gm-message-state; bh=DyMpTqPLMdNdaJuzBmgCnLLbJs/25Yb7UM0pJLmooVM=; b=eLJR27HGoTHaQxAQKF29MaU5qI/hGJYEioKl8p0OX47OiVeCsv3nZo47jWXagSNBqz 1uqB41MEqwqjlZJYLuxay/aYMKwA77v/w0Owtp980vEh/xinGonJ6PYFyBbpmVSwjMW4 /PGUte3jbR+75KKlJMLocOVB3BMcMgsfhsTkH01iCHgW2lHzmQr++5ObQ84f/Jukmpkf c8kcj+4BJahu95rAu8bMbdk7lPw8S3iQihqio3gDykyYT1ledprBdKdxfGmQXkJUPtNA yZFbJt+JuRlfVlrUhCCohBSx4cSvqsX2ulOAfRItiI+qbTDK+tTYh7MCmeUpOhdh1B/y HH9w== Received: by 10.152.104.148 with SMTP id ge20mr11403691lab.51.1353333237996; Mon, 19 Nov 2012 05:53:57 -0800 (PST) MIME-Version: 1.0 Received: by 10.112.25.166 with HTTP; Mon, 19 Nov 2012 05:53:27 -0800 (PST) In-Reply-To: References: From: Eitan Adler Date: Mon, 19 Nov 2012 08:53:27 -0500 Message-ID: Subject: Re: inquiry To: Ronald Klop Content-Type: text/plain; charset=UTF-8 X-Gm-Message-State: ALoCoQmdp2b/kWK5Q5b8RGOHw07L9/cIVNUvBL2bfXIl40/fsy2d9kCrcMOMIv0nDXZhJzK7v82M Cc: Muhammad Osama , freebsd-arm@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Nov 2012 13:54:00 -0000 On 19 November 2012 07:15, Ronald Klop wrote: > On Mon, 19 Nov 2012 12:06:13 +0100, Muhammad Osama > wrote: > >> hi, >> >> I am Muhammad a astudent at last year of electronics and communication >> department faculty of engineering. >> >> i am very interested in Embedded system in general and developing in linux >> and unix . >> i want to interact with freebsd ,but i am still a beginner >> i have to do a graduation project this year so i want some develoment >> ideas >> in freebsd projects so i can choose one >> thanks in advance. > > > Take a look here. > http://wiki.freebsd.org/IdeasPage Some additional ideas can be found here: http://wiki.freebsd.org/GoogleCodeIn/2012Tasks Despite the name, some of the tasks there are quite challenging. -- Eitan Adler From owner-freebsd-arm@FreeBSD.ORG Mon Nov 19 15:28:06 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id E72685EB for ; Mon, 19 Nov 2012 15:28:06 +0000 (UTC) (envelope-from luk@semihalf.com) Received: from smtp.semihalf.com (smtp.semihalf.com [213.17.239.109]) by mx1.freebsd.org (Postfix) with ESMTP id 62AC18FC17 for ; Mon, 19 Nov 2012 15:28:05 +0000 (UTC) Received: from localhost (unknown [213.17.239.109]) by smtp.semihalf.com (Postfix) with ESMTP id 34FE2C4B9B for ; Mon, 19 Nov 2012 16:21:47 +0100 (CET) X-Virus-Scanned: by amavisd-new at semihalf.com Received: from smtp.semihalf.com ([213.17.239.109]) by localhost (smtp.semihalf.com [213.17.239.109]) (amavisd-new, port 10024) with ESMTP id fUYVFf2lpW8o for ; Mon, 19 Nov 2012 16:21:44 +0100 (CET) Received: from [10.0.2.115] (cardhu.semihalf.com [213.17.239.108]) by smtp.semihalf.com (Postfix) with ESMTPSA id 37E7FC4B99 for ; Mon, 19 Nov 2012 16:21:44 +0100 (CET) Message-ID: <50AA4E87.3000505@semihalf.com> Date: Mon, 19 Nov 2012 16:21:43 +0100 From: =?UTF-8?B?xYF1a2FzeiBQxYJhY2hubw==?= User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:16.0) Gecko/20121028 Thunderbird/16.0.2 MIME-Version: 1.0 To: freebsd-arm@freebsd.org Subject: ARM/SMP, Some patches for review. Content-Type: multipart/mixed; boundary="------------020100070900070501080600" X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Nov 2012 15:28:07 -0000 This is a multi-part message in MIME format. --------------020100070900070501080600 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi, I would like to propose few changes for ARM specific code. Three attached patches for freebsd-current allows building SMP-safe world for ARM targets and turns on TEX remap for ARMv6 and ARMv7 targets. More details inside patch files. Change introduced by "commit-2" removes armv7 targets (armv7 and pj4b) from kernel.tramp. AFAIK this feature is not working properly for armv7 targets and is causing problem during compilation: - LOCORE is defined during kernel compilation but not defined during kernel.tramp compilation, so #include pmap.h causes build errors. I do not think adding hack like this: #ifndef LOCORE #define LOCORE #endif to allow building something that is already broken is a good idea, so I removed cpufunc_asm_pj4b.S and cpufunc_asm_armv7.S from Makefile.arm Regards, Łukasz Płachno --------------020100070900070501080600 Content-Type: text/plain; charset=UTF-8; name="commit-2" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="commit-2" Y29tbWl0IDQ0MzdmZjM2ZDg0MzE4MTk4MzVjNjc3N2RmMjM5YzVjYzE5MzJlN2UKQXV0aG9y OiBMdWthc3ogUGxhY2hubyA8bHVrQHNlbWloYWxmLmNvbT4KRGF0ZTogICBNb24gTm92IDE5 IDEwOjI1OjUxIDIwMTIgKzAxMDAKCiAgICBhcm06IENsZWFudXAgaW4gQVJNIHNwZWNpZmlj IGNvZGUKICAgIAogICAgIC0gVW5pZnkgZGVzY3JpcHRpb25zIGZvciBjYWNoZSBhbmQgVExC IG1haW50ZW5hbmNlIG9wZXJhdGlvbnMKICAgICAtIFVzZSBhcmNoaXRlY3R1cmUgbWFjcm9z IGluc3RlYWQgb2YgQ1BVIHNwZWNpZmljIG9uZXMgaW4gZ2VuZXJpYyBjb2RlCiAgICAgLSBB ZGQgbWVtb3J5IGJhcnJpZXJzCiAgICAgLSBSZW1vdmUgYXJtdjcgdGFyZ2V0cyBmcm9tIGtl cm5lbC50cmFtcG9saW5lIChub3Qgd29ya2luZyBjdXJyZW50bHkpLAogICAgICAgYWRkIGRl YnVnIGtlcm5lbCBtYXAgZm9yIGJ1aWxkIHRhcmdldHMKCmRpZmYgLS1naXQgYS9zeXMvYXJt L2FybS9jcHVmdW5jX2FzbV9hcm12Ny5TIGIvc3lzL2FybS9hcm0vY3B1ZnVuY19hc21fYXJt djcuUwppbmRleCA1OGYyOTVjLi4wMzU2MWI4IDEwMDY0NAotLS0gYS9zeXMvYXJtL2FybS9j cHVmdW5jX2FzbV9hcm12Ny5TCisrKyBiL3N5cy9hcm0vYXJtL2NwdWZ1bmNfYXNtX2FybXY3 LlMKQEAgLTcxLDkgKzcxLDkgQEAgRU5UUlkoYXJtdjdfc2V0dHRiKQogCW9yciAJcjAsIHIw LCAjUFRfQVRUUgogIAltY3IJcDE1LCAwLCByMCwgYzIsIGMwLCAwCS8qIFRyYW5zbGF0aW9u IFRhYmxlIEJhc2UgUmVnaXN0ZXIgMCAoVFRCUjApICovCiAjaWZkZWYgU01QCi0gCW1jciAg ICAgcDE1LCAwLCByMCwgYzgsIGMzLCAwICAgLyogaW52YWxpZGF0ZSBJK0QgVExCcyBJbm5l ciBTaGFyZWFibGUqLworCW1jcglwMTUsIDAsIHIwLCBjOCwgYzMsIDAJLyogSW52YWxpZGF0 ZSBJK0QgVExCcyBJbm5lciBTaGFyZWFibGUgKi8KICNlbHNlCi0gCW1jciAgICAgcDE1LCAw LCByMCwgYzgsIGM3LCAwICAgLyogaW52YWxpZGF0ZSBJK0QgVExCcyAqLworCW1jcglwMTUs IDAsIHIwLCBjOCwgYzcsIDAJLyogSW52YWxpZGF0ZSBJK0QgVExCcyAqLwogI2VuZGlmCiAg CWRzYgogIAlpc2IKQEAgLTgyLDExICs4MiwxMSBAQCBFTlRSWShhcm12N19zZXR0dGIpCiBF TlRSWShhcm12N190bGJfZmx1c2hJRCkKIAlkc2IKICNpZmRlZiBTTVAKLQltY3IJcDE1LCAw LCByMCwgYzgsIGMzLCAwCS8qIGZsdXNoIEkrRCB0bGIgKi8KLQltY3IJcDE1LCAwLCByMCwg YzcsIGMxLCA2CS8qIGZsdXNoIEJUQiAqLworCW1jcglwMTUsIDAsIHIwLCBjOCwgYzMsIDAJ LyogSW52YWxpZGF0ZSBJK0QgVExCcyBJbm5lciBTaGFyZWFibGUgKi8KKwltY3IJcDE1LCAw LCByMCwgYzcsIGMxLCA2CS8qIEZsdXNoIEJUQiBJbm5lciBTaGFyZWFibGUgKi8KICNlbHNl Ci0JbWNyCXAxNSwgMCwgcjAsIGM4LCBjNywgMAkvKiBmbHVzaCBJK0QgdGxiICovCi0JbWNy CXAxNSwgMCwgcjAsIGM3LCBjNSwgNgkvKiBmbHVzaCBCVEIgKi8KKwltY3IJcDE1LCAwLCBy MCwgYzgsIGM3LCAwCS8qIEludmFsaWRhdGUgSStEIFRMQnMgKi8KKwltY3IJcDE1LCAwLCBy MCwgYzcsIGM1LCA2CS8qIEZsdXNoIEJUQiAqLwogI2VuZGlmCiAJZHNiCiAJaXNiCkBAIC05 NiwxMCArOTYsMTAgQEAgRU5UUlkoYXJtdjdfdGxiX2ZsdXNoSURfU0UpCiAJbGRyCXIxLCAu THBhZ2VfbWFzawogCWJpYwlyMCwgcjAsIHIxCiAjaWZkZWYgU01QCi0JbWNyCXAxNSwgMCwg cjAsIGM4LCBjMywgMQkvKiBmbHVzaCBEIHRsYiBzaW5nbGUgZW50cnkgSW5uZXIgU2hhcmVh YmxlKi8KKwltY3IJcDE1LCAwLCByMCwgYzgsIGMzLCAxCS8qIEludmFsaWRhdGUgSStEIFRM QiBzaW5nbGUgZW50cnkgSW5uZXIgU2hhcmVhYmxlICovCiAJbWNyCXAxNSwgMCwgcjAsIGM3 LCBjMSwgNgkvKiBmbHVzaCBCVEIgSW5uZXIgU2hhcmVhYmxlICovCiAjZWxzZQotCW1jcglw MTUsIDAsIHIwLCBjOCwgYzcsIDEJLyogZmx1c2ggRCB0bGIgc2luZ2xlIGVudHJ5ICovCisJ bWNyCXAxNSwgMCwgcjAsIGM4LCBjNywgMQkvKiBJbnZhbGlkYXRlIEkrRCBUTEIgc2luZ2xl IGVudHJ5IElubmVyIFNoYXJlYWJsZSAqLwogCW1jcglwMTUsIDAsIHIwLCBjNywgYzUsIDYJ LyogZmx1c2ggQlRCICovCiAjZW5kaWYKIAlkc2IKQEAgLTI2Miw5ICsyNjIsOSBAQCBFTlRS WShhcm12N19jb250ZXh0X3N3aXRjaCkKIAkJCQogCW1jcglwMTUsIDAsIHIwLCBjMiwgYzAs IDAJLyogc2V0IHRoZSBuZXcgVFRCICovCiAjaWZkZWYgU01QCi0JbWNyCXAxNSwgMCwgcjAs IGM4LCBjMywgMAkvKiBhbmQgZmx1c2ggdGhlIEkrRCB0bGJzIElubmVyIFNoYXJhYmxlICov CisJbWNyCXAxNSwgMCwgcjAsIGM4LCBjMywgMAkvKiBJbnZhbGlkYXRlIEkrRCBUTEJzIElu bmVyIFNoYXJlYWJsZSAqLwogI2Vsc2UKLQltY3IJcDE1LCAwLCByMCwgYzgsIGM3LCAwCS8q IGFuZCBmbHVzaCB0aGUgSStEIHRsYnMgKi8KKwltY3IJcDE1LCAwLCByMCwgYzgsIGM3LCAw CS8qIEludmFsaWRhdGUgSStEIFRMQnMgKi8KICNlbmRpZgogCWRzYgogCWlzYgpkaWZmIC0t Z2l0IGEvc3lzL2FybS9hcm0vbG9jb3JlLlMgYi9zeXMvYXJtL2FybS9sb2NvcmUuUwppbmRl eCA5OWIyMTRhLi4zZjgwM2YxIDEwMDY0NAotLS0gYS9zeXMvYXJtL2FybS9sb2NvcmUuUwor KysgYi9zeXMvYXJtL2FybS9sb2NvcmUuUwpAQCAtMTcyLDcgKzE3Miw3IEBAIEx1bm1hcHBl ZDoKIAltY3IJcDE1LCAwLCByMCwgYzgsIGM3LCAwCS8qIEludmFsaWRhdGUgSStEIFRMQnMg Ki8KICNlbmRpZgogCi0jaWYgZGVmaW5lZChDUFVfQVJNMTEpIHx8IGRlZmluZWQoQ1BVX0NP UlRFWEEpIHx8IGRlZmluZWQoQ1BVX01WX1BKNEIpCisjaWYgZGVmaW5lZChBUk1fQVJDSF82 KSB8fCBkZWZpbmVkKEFSTV9BUkNIXzdBKQogCW1vdglyMCwgIzAKIAltY3IJcDE1LCAwLCBy MCwgYzEzLCBjMCwgMQkvKiBTZXQgQVNJRCB0byAwICovCiAjZW5kaWYKQEAgLTE4Miw3ICsx ODIsNyBAQCBMdW5tYXBwZWQ6CiAJbWNyCXAxNSwgMCwgcjAsIGMzLCBjMCwgMAogCS8qIEVu YWJsZSBNTVUgKi8KIAltcmMJcDE1LCAwLCByMCwgYzEsIGMwLCAwCi0jaWYgZGVmaW5lZChD UFVfQVJNMTEpIHx8IGRlZmluZWQoQ1BVX0NPUlRFWEEpIHx8IGRlZmluZWQoQ1BVX01WX1BK NEIpCisjaWYgZGVmaW5lZChBUk1fQVJDSF82KSB8fCBkZWZpbmVkKEFSTV9BUkNIXzdBKQog CW9ycglyMCwgcjAsICNDUFVfQ09OVFJPTF9WNl9FWFRQQUdFCiAjZW5kaWYKIAlvcnIJcjAs IHIwLCAjKENQVV9DT05UUk9MX01NVV9FTkFCTEUgfCBDUFVfQ09OVFJPTF9EQ19FTkFCTEUp CkBAIC0zNzEsNyArMzcxLDcgQEAgTHRhZzoKIAltY3IJcDE1LCAwLCByMCwgYzgsIGM3LCAw CS8qIEludmFsaWRhdGUgSStEIFRMQnMgKi8KICNlbmRpZgogCi0jaWYgZGVmaW5lZChDUFVf QVJNMTEpIHx8IGRlZmluZWQoQ1BVX01WX1BKNEIpIHx8IGRlZmluZWQoQ1BVX0NPUlRFWEEp CisjaWYgZGVmaW5lZChBUk1fQVJDSF82KSB8fCBkZWZpbmVkKEFSTV9BUkNIXzdBKQogCW1v dglyMCwgIzAKIAltY3IJcDE1LCAwLCByMCwgYzEzLCBjMCwgMQkvKiBTZXQgQVNJRCB0byAw ICovCiAjZW5kaWYKQEAgLTM4Myw3ICszODMsNyBAQCBMdGFnOgogCW1jcglwMTUsIDAsIHIw LCBjMywgYzAsIDAKIAkvKiBFbmFibGUgTU1VICovCiAJbXJjCXAxNSwgMCwgcjAsIGMxLCBj MCwgMAotI2lmIGRlZmluZWQoQ1BVX0FSTTExKSB8fCBkZWZpbmVkKENQVV9NVl9QSjRCKSB8 fCBkZWZpbmVkKENQVV9DT1JURVhBKQorI2lmIGRlZmluZWQoQVJNX0FSQ0hfNikgfHwgZGVm aW5lZChBUk1fQVJDSF83QSkKIAlvcnIJcjAsIHIwLCAjQ1BVX0NPTlRST0xfVjZfRVhUUEFH RQogI2VuZGlmCiAJb3JyCXIwLCByMCwgIyhDUFVfQ09OVFJPTF9NTVVfRU5BQkxFIHwgQ1BV X0NPTlRST0xfRENfRU5BQkxFKQpkaWZmIC0tZ2l0IGEvc3lzL2FybS9hcm0vbWFjaGRlcC5j IGIvc3lzL2FybS9hcm0vbWFjaGRlcC5jCmluZGV4IDE3YTYwYzIuLjExNzE0ZGEgMTAwNjQ0 Ci0tLSBhL3N5cy9hcm0vYXJtL21hY2hkZXAuYworKysgYi9zeXMvYXJtL2FybS9tYWNoZGVw LmMKQEAgLTgzNCw3ICs4MzQsNyBAQCBmYWtlX3ByZWxvYWRfbWV0YWRhdGEoc3RydWN0IGFy bV9ib290X3BhcmFtcyAqYWJwIF9fdW51c2VkKQogdm9pZAogcGNwdTBfaW5pdCh2b2lkKQog ewotI2lmIEFSTV9BUkNIXzYgfHwgQVJNX0FSQ0hfN0EgfHwgZGVmaW5lZChDUFVfTVZfUEo0 QikKKyNpZiBBUk1fQVJDSF82IHx8IEFSTV9BUkNIXzdBCiAJc2V0X3BjcHUocGNwdXApOwog I2VuZGlmCiAJcGNwdV9pbml0KHBjcHVwLCAwLCBzaXplb2Yoc3RydWN0IHBjcHUpKTsKZGlm ZiAtLWdpdCBhL3N5cy9hcm0vaW5jbHVkZS9hdG9taWMuaCBiL3N5cy9hcm0vaW5jbHVkZS9h dG9taWMuaAppbmRleCAxYTk2MTc2Li5mMTIwMTkxIDEwMDY0NAotLS0gYS9zeXMvYXJtL2lu Y2x1ZGUvYXRvbWljLmgKKysrIGIvc3lzL2FybS9pbmNsdWRlL2F0b21pYy5oCkBAIC00Nyw5 ICs0NywyNSBAQAogI2luY2x1ZGUgPG1hY2hpbmUvY3B1Y29uZi5oPgogI2VuZGlmCiAKLSNk ZWZpbmUgbWIoKQotI2RlZmluZSB3bWIoKQotI2RlZmluZSBybWIoKQorI2lmIGRlZmluZWQo QVJNX0FSQ0hfNikgfHwgZGVmaW5lZChBUk1fQVJDSF83QSkKKyNkZWZpbmUJbWIoKQlkbyB7 IFwKKwl1aW50MzJfdCByZWcgPSAwOyBcCisJX19hc20gX192b2xhdGlsZSgibWNyCXAxNSwg MCwgJTAsIGM3LCBjMTAsIDQiIDogOiAiciIgKHJlZykpOyBcCisJfSB3aGlsZSAoMCkKKyNk ZWZpbmUJd21iKCkJZG8geyBcCisJdWludDMyX3QgcmVnID0gMDsgXAorCV9fYXNtIF9fdm9s YXRpbGUoIm1jcglwMTUsIDAsICUwLCBjNywgYzEwLCA0IiA6IDogInIiIChyZWcpKTsgXAor CX0gd2hpbGUgKDApCisjZGVmaW5lCXJtYigpCWRvIHsgXAorCXVpbnQzMl90IHJlZyA9IDA7 IFwKKwlfX2FzbSBfX3ZvbGF0aWxlKCJtY3IJcDE1LCAwLCAlMCwgYzcsIGMxMCwgNCIgOiA6 ICJyIiAocmVnKSk7IFwKKwl9IHdoaWxlICgwKQorI2Vsc2UKKyNkZWZpbmUJbWIoKQorI2Rl ZmluZQl3bWIoKQorI2RlZmluZQlybWIoKQorI2VuZGlmCisKIAogI2lmbmRlZiBJMzJfYml0 CiAjZGVmaW5lIEkzMl9iaXQgKDEgPDwgNykgICAgICAgIC8qIElSUSBkaXNhYmxlICovCmRp ZmYgLS1naXQgYS9zeXMvY29uZi9NYWtlZmlsZS5hcm0gYi9zeXMvY29uZi9NYWtlZmlsZS5h cm0KaW5kZXggNjI3MGFlZi4uMmY5ZTdlYyAxMDA2NDQKLS0tIGEvc3lzL2NvbmYvTWFrZWZp bGUuYXJtCisrKyBiL3N5cy9jb25mL01ha2VmaWxlLmFybQpAQCAtNTEsNiArNTEsNyBAQCBT WVNURU1fTERfVEFJTCArPTtzZWQgcy8iICsgU0laRU9GX0hFQURFUlMiLy8gbGRzY3JpcHQu JE1cCiAJCSR7U1lTVEVNX0xEX307IFwKIAkJJHtPQkpDT1BZfSAtUyAtTyBiaW5hcnkgJHtG VUxMS0VSTkVMfS5ub2hlYWRlciBcCiAJCSR7S0VSTkVMX0tPfS5iaW47IFwKKwkJJHtOTX0g JHtGVUxMS0VSTkVMfS5ub2hlYWRlciB8IHNvcnQgPiAke0ZVTExLRVJORUx9Lm1hcDsgXAog CQlybSAke0ZVTExLRVJORUx9Lm5vaGVhZGVyCiAKIC5pZiBkZWZpbmVkKE1GU19JTUFHRSkK QEAgLTYzLDcgKzY0LDYgQEAgRklMRVNfQ1BVX0ZVTkMgPQkkUy8kTS8kTS9jcHVmdW5jX2Fz bV9hcm03dGRtaS5TIFwKIAkkUy8kTS8kTS9jcHVmdW5jX2FzbV94c2NhbGUuUyAkUy8kTS8k TS9jcHVmdW5jX2FzbS5TIFwKIAkkUy8kTS8kTS9jcHVmdW5jX2FzbV94c2NhbGVfYzMuUyAk Uy8kTS8kTS9jcHVmdW5jX2FzbV9hcm12NV9lYy5TIFwKIAkkUy8kTS8kTS9jcHVmdW5jX2Fz bV9mYTUyNi5TICRTLyRNLyRNL2NwdWZ1bmNfYXNtX3NoZWV2YS5TIFwKLQkkUy8kTS8kTS9j cHVmdW5jX2FzbV9wajRiLlMgJFMvJE0vJE0vY3B1ZnVuY19hc21fYXJtdjcuUwogCiBLRVJO RUxfRVhUUkE9dHJhbXBvbGluZQogS0VSTkVMX0VYVFJBX0lOU1RBTEw9a2VybmVsLmd6LnRy YW1wCg== --------------020100070900070501080600 Content-Type: text/plain; charset=UTF-8; name="commit-3" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="commit-3" Y29tbWl0IDI4ODg3NDhkOTEzNGJiYWRlOGI4ZjYwN2M2ZWM5OWYwNzA5M2ZhZDcKQXV0aG9y OiBMdWthc3ogUGxhY2hubyA8bHVrQHNlbWloYWxmLmNvbT4KRGF0ZTogICBNb24gTm92IDE5 IDEyOjExOjI5IDIwMTIgKzAxMDAKCiAgICBhcm06IEltcGxlbWVudCBuZXcgd2F5IGZvciBw YWdldGFibGUgbWVtb3J5IGF0dHJpYnV0ZXMgbWFuYWdlbWVudAogICAgCiAgICAgLSBpbml0 aWFsaXplIFBSUlIgYW5kIE5NUlIgcmVnaXN0ZXJzIGluIGNwMTUKICAgICAtIGVuYWJsZSBU RVggcmVtYXBwaW5nCiAgICAgLSBjcmVhdGUgbWFjcm9zIGZvciBUVEIgYXR0cmlidXRlcwog ICAgIC0gYWRkIFBSUlIgYW5kIE5NUlIgdG8gc2hvdyBjcDE1IGRkYiBjb21tYW5kCgpkaWZm IC0tZ2l0IGEvc3lzL2FybS9hcm0vY3B1ZnVuYy5jIGIvc3lzL2FybS9hcm0vY3B1ZnVuYy5j CmluZGV4IGRkNDNjMjcuLjJhM2FjYjQgMTAwNjQ0Ci0tLSBhL3N5cy9hcm0vYXJtL2NwdWZ1 bmMuYworKysgYi9zeXMvYXJtL2FybS9jcHVmdW5jLmMKQEAgLTIzMjcsNiArMjMyNyw3IEBA IHBqNGJ2Nl9zZXR1cChjaGFyICphcmdzKQogCQljcHVjdHJsIHw9IENQVV9DT05UUk9MX1ZF Q1JFTE9DOwogCWNwdWN0cmwgfD0gKDB4NSA8PCAxNik7CiAJY3B1Y3RybCB8PSBDUFVfQ09O VFJPTF9WNl9FWFRQQUdFOworCWNwdWN0cmwgfD0gQ1BVX0NPTlRST0xfVEVYX1JFTUFQOwog CS8qIFhYWCBub3QgeWV0ICovCiAJLyogY3B1Y3RybCB8PSBDUFVfQ09OVFJPTF9MMl9FTkFC TEU7ICovCiAKQEAgLTIzNjIsNiArMjM2Myw3IEBAIHBqNGJ2N19zZXR1cChhcmdzKQogCQlj cHVjdHJsIHw9IENQVV9DT05UUk9MX1ZFQ1JFTE9DOwogCWNwdWN0cmwgfD0gKDB4NSA8PCAx NikgfCAoMSA8IDIyKTsKIAljcHVjdHJsIHw9IENQVV9DT05UUk9MX1Y2X0VYVFBBR0U7CisJ Y3B1Y3RybCB8PSBDUFVfQ09OVFJPTF9URVhfUkVNQVA7CiAKIAkvKiBDbGVhciBvdXQgdGhl IGNhY2hlICovCiAJY3B1X2lkY2FjaGVfd2JpbnZfYWxsKCk7CkBAIC0yMzkyLDcgKzIzOTQs OCBAQCBjb3J0ZXhhX3NldHVwKGNoYXIgKmFyZ3MpCiAJY3B1Y3RybCA9IENQVV9DT05UUk9M X01NVV9FTkFCTEUgfAogCSAgICBDUFVfQ09OVFJPTF9JQ19FTkFCTEUgfAogCSAgICBDUFVf Q09OVFJPTF9EQ19FTkFCTEUgfAotCSAgICBDUFVfQ09OVFJPTF9CUFJEX0VOQUJMRTsKKwkg ICAgQ1BVX0NPTlRST0xfQlBSRF9FTkFCTEUgfAorCSAgICBDUFVfQ09OVFJPTF9URVhfUkVN QVA7CiAJCiAjaWZuZGVmIEFSTTMyX0RJU0FCTEVfQUxJR05NRU5UX0ZBVUxUUwogCWNwdWN0 cmwgfD0gQ1BVX0NPTlRST0xfQUZMVF9FTkFCTEU7CmRpZmYgLS1naXQgYS9zeXMvYXJtL2Fy bS9jcHVmdW5jX2FzbV9hcm12Ny5TIGIvc3lzL2FybS9hcm0vY3B1ZnVuY19hc21fYXJtdjcu UwppbmRleCAwMzU2MWI4Li5kNmY5ZDU5IDEwMDY0NAotLS0gYS9zeXMvYXJtL2FybS9jcHVm dW5jX2FzbV9hcm12Ny5TCisrKyBiL3N5cy9hcm0vYXJtL2NwdWZ1bmNfYXNtX2FybXY3LlMK QEAgLTMyLDYgKzMyLDggQEAKICNpbmNsdWRlIDxtYWNoaW5lL2FzbS5oPgogX19GQlNESUQo IiRGcmVlQlNEJCIpOwogCisjaW5jbHVkZSA8bWFjaGluZS9wbWFwLmg+CisKIAkuY3B1IGNv cnRleC1hOAogCiAuTGNvaGVyZW5jeV9sZXZlbDoKQEAgLTQ1LDMwICs0NywxMyBAQCBfX0ZC U0RJRCgiJEZyZWVCU0QkIik7CiAuTHBhZ2VfbWFzazoKIAkud29yZAkweGZmZgogCi0jZGVm aW5lIFBUX05PUyAgICAgICAgICAoMSA8PCA1KQotI2RlZmluZSBQVF9TIAkgICAgICAgICgx IDw8IDEpCi0jZGVmaW5lIFBUX0lOTkVSX05DCTAKLSNkZWZpbmUgUFRfSU5ORVJfV1QJKDEg PDwgMCkKLSNkZWZpbmUgUFRfSU5ORVJfV0IJKCgxIDw8IDApIHwgKDEgPDwgNikpCi0jZGVm aW5lIFBUX0lOTkVSX1dCV0EJKDEgPDwgNikKLSNkZWZpbmUgUFRfT1VURVJfTkMJMAotI2Rl ZmluZSBQVF9PVVRFUl9XVAkoMiA8PCAzKQotI2RlZmluZSBQVF9PVVRFUl9XQgkoMyA8PCAz KQotI2RlZmluZSBQVF9PVVRFUl9XQldBCSgxIDw8IDMpCi0JCi0jaWZkZWYgU01QCi0jZGVm aW5lIFBUX0FUVFIJKFBUX1N8UFRfSU5ORVJfV1R8UFRfT1VURVJfV1R8UFRfTk9TKQotI2Vs c2UKLSNkZWZpbmUgUFRfQVRUUgkoUFRfSU5ORVJfV1R8UFRfT1VURVJfV1QpCi0jZW5kaWYK LQogRU5UUlkoYXJtdjdfc2V0dHRiKQogCXN0bWRiICAgc3AhLCB7cjAsIGxyfQogIAlibCAg ICAgIF9DX0xBQkVMKGFybXY3X2lkY2FjaGVfd2JpbnZfYWxsKSAvKiBjbGVhbiB0aGUgRCBj YWNoZSAqLwogIAlsZG1pYSAgIHNwISwge3IwLCBscn0KICAJZHNiCiAJCQkJCi0Jb3JyIAly MCwgcjAsICNQVF9BVFRSCisJb3JyIAlyMCwgcjAsICNUVEJfQVRUUgogIAltY3IJcDE1LCAw LCByMCwgYzIsIGMwLCAwCS8qIFRyYW5zbGF0aW9uIFRhYmxlIEJhc2UgUmVnaXN0ZXIgMCAo VFRCUjApICovCiAjaWZkZWYgU01QCiAJbWNyCXAxNSwgMCwgcjAsIGM4LCBjMywgMAkvKiBJ bnZhbGlkYXRlIEkrRCBUTEJzIElubmVyIFNoYXJlYWJsZSAqLwpAQCAtMjU4LDcgKzI0Myw3 IEBAIEVOVFJZKGFybXY3X2NwdV9zbGVlcCkKIAogRU5UUlkoYXJtdjdfY29udGV4dF9zd2l0 Y2gpCiAJZHNiCi0Jb3JyICAgICByMCwgcjAsICNQVF9BVFRSCisJb3JyCXIwLCByMCwgI1RU Ql9BVFRSCiAJCQkKIAltY3IJcDE1LCAwLCByMCwgYzIsIGMwLCAwCS8qIHNldCB0aGUgbmV3 IFRUQiAqLwogI2lmZGVmIFNNUApkaWZmIC0tZ2l0IGEvc3lzL2FybS9hcm0vY3B1ZnVuY19h c21fcGo0Yi5TIGIvc3lzL2FybS9hcm0vY3B1ZnVuY19hc21fcGo0Yi5TCmluZGV4IGY2ODkw ZDkuLmYyZWJhOTQgMTAwNjQ0Ci0tLSBhL3N5cy9hcm0vYXJtL2NwdWZ1bmNfYXNtX3BqNGIu UworKysgYi9zeXMvYXJtL2FybS9jcHVmdW5jX2FzbV9wajRiLlMKQEAgLTMzLDYgKzMzLDcg QEAKIF9fRkJTRElEKCIkRnJlZUJTRCQiKTsKIAogI2luY2x1ZGUgPG1hY2hpbmUvcGFyYW0u aD4KKyNpbmNsdWRlIDxtYWNoaW5lL3BtYXAuaD4KIAogLkxwajRiX2NhY2hlX2xpbmVfc2l6 ZToKIAkud29yZAlfQ19MQUJFTChhcm1fcGRjYWNoZV9saW5lX3NpemUpCkBAIC00MCw5ICs0 MSw3IEBAIF9fRkJTRElEKCIkRnJlZUJTRCQiKTsKIEVOVFJZKHBqNGJfc2V0dHRiKQogCS8q IENhY2hlIHN5bmNocm9uaXphdGlvbiBpcyBub3QgcmVxdWlyZWQgYXMgdGhpcyBjb3JlIGhh cyBQSVBUIGNhY2hlcyAqLwogCW1jcglwMTUsIDAsIHIxLCBjNywgYzEwLCA0CS8qIGRyYWlu IHRoZSB3cml0ZSBidWZmZXIgKi8KLSNpZmRlZiBTTVAKLQlvcnIgCXIwLCByMCwgIzIJCS8q IFNldCBUVEIgc2hhcmVkIG1lbW9yeSBmbGFnICovCi0jZW5kaWYKKwlvcnIJcjAsIHIwLCAj VFRCX0FUVFIJLyogU2V0IFRUQiBtZW1vcnkgZmxhZ3MgKi8KIAltY3IJcDE1LCAwLCByMCwg YzIsIGMwLCAwCS8qIGxvYWQgbmV3IFRUQiAqLwogCW1jcglwMTUsIDAsIHIwLCBjOCwgYzcs IDAJLyogaW52YWxpZGF0ZSBJK0QgVExCcyAqLwogCVJFVApAQCAtMTk5LDQgKzE5OCw1IEBA IEVOVFJZKHBqNGJfY29uZmlnKQogCW9ycglyMCwgcjAsICMoMSA8PCA1KQogCW1jcglwMTUs IDAsIHIwLCBjMSwgYzAsIDEKICNlbmRpZgorCiAJUkVUCmRpZmYgLS1naXQgYS9zeXMvYXJt L2FybS9sb2NvcmUuUyBiL3N5cy9hcm0vYXJtL2xvY29yZS5TCmluZGV4IDNmODAzZjEuLmIw OWUyMDIgMTAwNjQ0Ci0tLSBhL3N5cy9hcm0vYXJtL2xvY29yZS5TCisrKyBiL3N5cy9hcm0v YXJtL2xvY29yZS5TCkBAIC0zOCw2ICszOCw3IEBACiAjaW5jbHVkZSA8bWFjaGluZS9hc20u aD4KICNpbmNsdWRlIDxtYWNoaW5lL2FybXJlZy5oPgogI2luY2x1ZGUgPG1hY2hpbmUvcHRl Lmg+CisjaW5jbHVkZSA8bWFjaGluZS9wbWFwLmg+CiAKIF9fRkJTRElEKCIkRnJlZUJTRCQi KTsKIApAQCAtMTYyLDggKzE2Myw5IEBAIEx1bm1hcHBlZDoKIAlvcnJuZQlyNSwgcjUsICNQ SFlTQUREUgogCW1vdm5lCXBjLCByNQogCi0jaWYgZGVmaW5lZChTTVApCi0Jb3JyIAlyMCwg cjAsICMyCQkvKiBTZXQgVFRCIHNoYXJlZCBtZW1vcnkgZmxhZyAqLworI2lmIGRlZmluZWQo QVJNX0FSQ0hfNikgfHwgZGVmaW5lZChBUk1fQVJDSF83QSkKKwkvKiBGb3IgcHJpbWFyeSBw YWdldGFibGUgbm9ybWFsIG5vbi1jYWNoZWFibGUgbWVtb3J5IGlzIHVzZWQgKi8KKwlvcnIJ cjAsIHIwLCAjVFRCX0ZMQUdTXzIJLyogU2V0IFRUQiBtZW1vcnkgZmxhZ3MgKi8KICNlbmRp ZgogCW1jcglwMTUsIDAsIHIwLCBjMiwgYzAsIDAJLyogU2V0IFRUQiAqLwogI2lmZGVmIFNN UApAQCAtMTczLDYgKzE3NSwxNyBAQCBMdW5tYXBwZWQ6CiAjZW5kaWYKIAogI2lmIGRlZmlu ZWQoQVJNX0FSQ0hfNikgfHwgZGVmaW5lZChBUk1fQVJDSF83QSkKKwkvKiBTZXQgUFJSUiBh bmQgTk1SUiBjcDE1IHJlZ2lzdGVycyAqLworCWxkcglyMCwgPVBSUlIKKwltY3IJcDE1LCAw LCByMCwgYzEwLCBjMiwgMAorCWxkcglyMCwgPU5NUlIKKwltY3IJcDE1LCAwLCByMCwgYzEw LCBjMiwgMQorCisJLyogU2V0IFRFWCBSZW1hcCovCisJbXJjCXAxNSwgMCwgcjAsIGMxLCBj MCwgMAorCW9ycglyMCwgI0NQVV9DT05UUk9MX1RFWF9SRU1BUAorCW1jcglwMTUsIDAsIHIw LCBjMSwgYzAsIDAKKwogCW1vdglyMCwgIzAKIAltY3IJcDE1LCAwLCByMCwgYzEzLCBjMCwg MQkvKiBTZXQgQVNJRCB0byAwICovCiAjZW5kaWYKQEAgLTI1Nyw3ICsyNzAsNyBAQCBtbXVf aW5pdF90YWJsZToKIAkvKiBtYXAgVkEgMHhjMDAwMDAwMC4uMHhjM2ZmZmZmZiB0byBQQSAq LwogCU1NVV9JTklUKEtFUk5CQVNFLCBQSFlTQUREUiwgNjQsIEwxX1RZUEVfU3xMMV9TSEFS RUR8TDFfU19DfEwxX1NfQVAoQVBfS1JXKSkKIAlNTVVfSU5JVCgweDQ4MDAwMDAwLCAweDQ4 MDAwMDAwLCAxLCBMMV9UWVBFX1N8TDFfU0hBUkVEfEwxX1NfQ3xMMV9TX0FQKEFQX0tSVykp Ci0jZW5kaWYKKyNlbmRpZiAvKiBTTVAgKi8KIAkud29yZCAwCS8qIGVuZCBvZiB0YWJsZSAq LwogI2VuZGlmCiAuTHN0YXJ0OgpAQCAtMzYxLDggKzM3NCwxMCBAQCBMdGFnOgogCWJpYwly MCwgcjAsICMweGYwMDAwMDAwCiAJb3JyCXIwLCByMCwgI1BIWVNBRERSCiAJbGRyCXIwLCBb cjBdCi0jaWYgZGVmaW5lZChTTVApCi0Jb3JyIAlyMCwgcjAsICMwCQkvKiBTZXQgVFRCIHNo YXJlZCBtZW1vcnkgZmxhZyAqLworCisjaWYgZGVmaW5lZChBUk1fQVJDSF82KSB8fCBkZWZp bmVkKEFSTV9BUkNIXzdBKQorCS8qIEZvciBwcmltYXJ5IHBhZ2V0YWJsZSBub3JtYWwgbm9u LWNhY2hlYWJsZSBtZW1vcnkgaXMgdXNlZCAqLworCW9ycglyMCwgcjAsICNUVEJfRkxBR1Nf MgkvKiBTZXQgVFRCIG1lbW9yeSBmbGFncyAqLwogI2VuZGlmCiAJbWNyCXAxNSwgMCwgcjAs IGMyLCBjMCwgMAkvKiBTZXQgVFRCICovCiAjaWZkZWYgU01QCkBAIC0zNzIsNiArMzg3LDE3 IEBAIEx0YWc6CiAjZW5kaWYKIAogI2lmIGRlZmluZWQoQVJNX0FSQ0hfNikgfHwgZGVmaW5l ZChBUk1fQVJDSF83QSkKKwkvKiBTZXQgUFJSUiBhbmQgTk1SUiBjcDE1IHJlZ2lzdGVycyAq LworCWxkcglyMCwgPVBSUlIKKwltY3IJcDE1LCAwLCByMCwgYzEwLCBjMiwgMAorCWxkcgly MCwgPU5NUlIKKwltY3IJcDE1LCAwLCByMCwgYzEwLCBjMiwgMQorCisJLyogU2V0IFRFWCBS ZW1hcCovCisJbXJjCXAxNSwgMCwgcjAsIGMxLCBjMCwgMAorCW9ycglyMCwgI0NQVV9DT05U Uk9MX1RFWF9SRU1BUAorCW1jcglwMTUsIDAsIHIwLCBjMSwgYzAsIDAKKwogCW1vdglyMCwg IzAKIAltY3IJcDE1LCAwLCByMCwgYzEzLCBjMCwgMQkvKiBTZXQgQVNJRCB0byAwICovCiAj ZW5kaWYKZGlmZiAtLWdpdCBhL3N5cy9hcm0vYXJtL21wX21hY2hkZXAuYyBiL3N5cy9hcm0v YXJtL21wX21hY2hkZXAuYwppbmRleCAzMGU2YjYzLi43MzM1YWRiIDEwMDY0NAotLS0gYS9z eXMvYXJtL2FybS9tcF9tYWNoZGVwLmMKKysrIGIvc3lzL2FybS9hcm0vbXBfbWFjaGRlcC5j CkBAIC0xMTYsMTIgKzExNiwxMiBAQCBjcHVfbXBfc3RhcnQodm9pZCkKIAlhZGRyX2VuZCA9 ICh2bV9vZmZzZXRfdCkmX2VuZCAtIEtFUk5WSVJUQUREUiArIEtFUk5QSFlTQUREUjsKIAlh ZGRyX2VuZCAmPSB+TDFfU19PRkZTRVQ7CiAJYWRkcl9lbmQgKz0gTDFfU19TSVpFOwotCWJ6 ZXJvKCh2b2lkICopdGVtcF9wYWdldGFibGVfdmEsICBMMV9UQUJMRV9TSVpFKTsKKwliemVy bygodm9pZCAqKXRlbXBfcGFnZXRhYmxlX3ZhLCBMMV9UQUJMRV9TSVpFKTsKIAlmb3IgKGFk ZHIgPSBLRVJOUEhZU0FERFI7IGFkZHIgPD0gYWRkcl9lbmQ7IGFkZHIgKz0gTDFfU19TSVpF KSB7IAogCQkoKGludCAqKSh0ZW1wX3BhZ2V0YWJsZV92YSkpW2FkZHIgPj4gTDFfU19TSElG VF0gPQogCQkgICAgTDFfVFlQRV9TfEwxX1NIQVJFRHxMMV9TX0N8TDFfU19BUChBUF9LUlcp fEwxX1NfRE9NKFBNQVBfRE9NQUlOX0tFUk5FTCl8YWRkcjsKIAkJKChpbnQgKikodGVtcF9w YWdldGFibGVfdmEpKVsoYWRkciAtCi0JCQlLRVJOUEhZU0FERFIgKyBLRVJOVklSVEFERFIp ID4+IEwxX1NfU0hJRlRdID0gCisJCSAgICBLRVJOUEhZU0FERFIgKyBLRVJOVklSVEFERFIp ID4+IEwxX1NfU0hJRlRdID0KIAkJICAgIEwxX1RZUEVfU3xMMV9TSEFSRUR8TDFfU19DfEwx X1NfQVAoQVBfS1JXKXxMMV9TX0RPTShQTUFQX0RPTUFJTl9LRVJORUwpfGFkZHI7CiAJfQog CXRlbXBfcGFnZXRhYmxlID0gKHZvaWQqKSh2dG9waHlzKHRlbXBfcGFnZXRhYmxlX3ZhKSk7 CmRpZmYgLS1naXQgYS9zeXMvYXJtL2FybS9wbWFwLXY2LmMgYi9zeXMvYXJtL2FybS9wbWFw LXY2LmMKaW5kZXggYTQ0YmRiZi4uYTAxZWY0NSAxMDA2NDQKLS0tIGEvc3lzL2FybS9hcm0v cG1hcC12Ni5jCisrKyBiL3N5cy9hcm0vYXJtL3BtYXAtdjYuYwpAQCAtMzg2LDM0ICszODYs NDUgQEAgc3RhdGljIHN0cnVjdCB2bV9vYmplY3QgcHZ6b25lX29iajsKIHN0YXRpYyBpbnQg cHZfZW50cnlfY291bnQ9MCwgcHZfZW50cnlfbWF4PTAsIHB2X2VudHJ5X2hpZ2hfd2F0ZXI9 MDsKIHN0YXRpYyBzdHJ1Y3Qgcndsb2NrIHB2aF9nbG9iYWxfbG9jazsKIAorI2lmIGRlZmlu ZWQoU01QKQorI2RlZmluZSBMMV9TSEFSRUFCTEUJTDFfU0hBUkVECisjZGVmaW5lIEwyX1NI QVJFQUJMRQlMMl9TSEFSRUQKKyNlbHNlCisjZGVmaW5lIEwxX1NIQVJFQUJMRQkwCisjZGVm aW5lIEwyX1NIQVJFQUJMRQkwCisjZW5kaWYgLyogU01QICovCisKIGludCBsMV9tZW1fdHlw ZXNbXSA9IHsKLQlBUk1fTDFTX1NUUk9OR19PUkQsCi0JQVJNX0wxU19ERVZJQ0VfTk9TSEFS RSwKLQlBUk1fTDFTX0RFVklDRV9TSEFSRSwKLQlBUk1fTDFTX05STUxfTk9DQUNIRSwKLQlB Uk1fTDFTX05STUxfSVdUX09XVCwKLQlBUk1fTDFTX05STUxfSVdCX09XQiwKLQlBUk1fTDFT X05STUxfSVdCQV9PV0JBCisJKEwxX1NIQVJFQUJMRSksCisJKEwxX1NIQVJFQUJMRSB8IEwx X1NfQiksCisJKEwxX1NIQVJFQUJMRSB8IEwxX1NfQyksCisJKEwxX1NIQVJFQUJMRSB8IEwx X1NfQyB8IEwxX1NfQiksCisJKEwxX1NIQVJFQUJMRSB8IEwxX1NfVEVYKDEpKSwKKwkoTDFf U0hBUkVBQkxFIHwgTDFfU19URVgoMSkgfCBMMV9TX0IpLAorCShMMV9TSEFSRUFCTEUpLAor CShMMV9TSEFSRUFCTEUgfCBMMV9TX1RFWCgxKSB8IEwxX1NfQyB8IEwxX1NfQikKIH07CiAK IGludCBsMmxfbWVtX3R5cGVzW10gPSB7Ci0JQVJNX0wyTF9TVFJPTkdfT1JELAotCUFSTV9M MkxfREVWSUNFX05PU0hBUkUsCi0JQVJNX0wyTF9ERVZJQ0VfU0hBUkUsCi0JQVJNX0wyTF9O Uk1MX05PQ0FDSEUsCi0JQVJNX0wyTF9OUk1MX0lXVF9PV1QsCi0JQVJNX0wyTF9OUk1MX0lX Ql9PV0IsCi0JQVJNX0wyTF9OUk1MX0lXQkFfT1dCQQorCShMMl9TSEFSRUFCTEUpLAorCShM Ml9TSEFSRUFCTEUgfCBMMl9CKSwKKwkoTDJfU0hBUkVBQkxFIHwgTDJfQyksCisJKEwyX1NI QVJFQUJMRSB8IEwyX0MgfCBMMl9CKSwKKwkoTDJfU0hBUkVBQkxFIHwgTDJfTF9URVgoMSkp LAorCShMMl9TSEFSRUFCTEUgfCBMMl9MX1RFWCgxKSB8IEwyX0IpLAorCShMMl9TSEFSRUFC TEUpLAorCShMMl9TSEFSRUFCTEUgfCBMMl9MX1RFWCgxKSB8IEwyX0MgfCBMMl9CKQogfTsK IAogaW50IGwyc19tZW1fdHlwZXNbXSA9IHsKLQlBUk1fTDJTX1NUUk9OR19PUkQsCi0JQVJN X0wyU19ERVZJQ0VfTk9TSEFSRSwKLQlBUk1fTDJTX0RFVklDRV9TSEFSRSwKLQlBUk1fTDJT X05STUxfTk9DQUNIRSwKLQlBUk1fTDJTX05STUxfSVdUX09XVCwKLQlBUk1fTDJTX05STUxf SVdCX09XQiwKLQlBUk1fTDJTX05STUxfSVdCQV9PV0JBCisJKEwyX1NIQVJFQUJMRSksCisJ KEwyX1NIQVJFQUJMRSB8IEwyX0IpLAorCShMMl9TSEFSRUFCTEUgfCBMMl9DKSwKKwkoTDJf U0hBUkVBQkxFIHwgTDJfQyB8IEwyX0IpLAorCShMMl9TSEFSRUFCTEUgfCBMMl9TX1RFWCgx KSksCisJKEwyX1NIQVJFQUJMRSB8IEwyX1NfVEVYKDEpIHwgTDJfQiksCisJKEwyX1NIQVJF QUJMRSksCisJKEwyX1NIQVJFQUJMRSB8IEwyX1NfVEVYKDEpIHwgTDJfQyB8IEwyX0IpCiB9 OwogCiAvKgpkaWZmIC0tZ2l0IGEvc3lzL2FybS9pbmNsdWRlL2FybXJlZy5oIGIvc3lzL2Fy bS9pbmNsdWRlL2FybXJlZy5oCmluZGV4IDA1YjM4NDYuLmY1Y2NmYjkgMTAwNjQ0Ci0tLSBh L3N5cy9hcm0vaW5jbHVkZS9hcm1yZWcuaAorKysgYi9zeXMvYXJtL2luY2x1ZGUvYXJtcmVn LmgKQEAgLTI4Niw2ICsyODYsNyBAQAogI2RlZmluZSBDUFVfQ09OVFJPTF9WNENPTVBBVAkw eDAwMDA4MDAwIC8qIEw0OiBBUk12NCBjb21wYXQgTERSIFIxNSBldGMgKi8KICNkZWZpbmUg Q1BVX0NPTlRST0xfVjZfRVhUUEFHRQkweDAwODAwMDAwIC8qIFhQOiBBUk12NiBleHRlbmRl ZCBwYWdlIHRhYmxlcyAqLwogI2RlZmluZSBDUFVfQ09OVFJPTF9MMl9FTkFCTEUJMHgwNDAw MDAwMCAvKiBMMiBDYWNoZSBlbmFibGVkICovCisjZGVmaW5lIENQVV9DT05UUk9MX1RFWF9S RU1BUAkweDEwMDAwMDAwIC8qIFRFWCBSZW1hcCBlbmFibGVkICovCiAKICNkZWZpbmUgQ1BV X0NPTlRST0xfSURDX0VOQUJMRQlDUFVfQ09OVFJPTF9EQ19FTkFCTEUKIApkaWZmIC0tZ2l0 IGEvc3lzL2FybS9pbmNsdWRlL3BtYXAuaCBiL3N5cy9hcm0vaW5jbHVkZS9wbWFwLmgKaW5k ZXggZTIwYmYxOC4uZDdiNDJiOCAxMDA2NDQKLS0tIGEvc3lzL2FybS9pbmNsdWRlL3BtYXAu aAorKysgYi9zeXMvYXJtL2luY2x1ZGUvcG1hcC5oCkBAIC01MiwzMyArNTIsMTI3IEBACiAK ICNpbmNsdWRlIDxtYWNoaW5lL3B0ZS5oPgogI2luY2x1ZGUgPG1hY2hpbmUvY3B1Y29uZi5o PgorCiAvKgotICogUHRlIHJlbGF0ZWQgbWFjcm9zCisgKiBXaGVuIFRFWCByZW1hcCBpcyBl bmFibGVkIChTQ1RMUi5UUkUgaXMgc2V0IHRvIDEpLAorICogUFJSUiBhbmQgTk1SUiB2YWx1 ZXMgbmVlZHMgdG8gYmUgaW5pdGlhbGl6ZWQgYmVmb3JlIE1NVSBpcyB1c2VkLgorICoKKyAq IFRFWFswXSxDLEIJLT4gaW5kZXgobikKKyAqCisgKiBQTVJSCQktPiBtZW1vcnkgdHlwZSAo c3Ryb25nbHkgb3JkZXJlZCwgZGV2aWNlLCBub3JtYWwpLCBzaGFyZWFiaWxpdHkKKyAqCVRS IChQUlJSWzJuKzE6Mm5dKQktPiBtZW1vcnkgdHlwZQorICoJTk9TIChQUk1SUlsyNCtuXSkJ LT4gbm9uIG91dGVyIHNoYXJlYWJsZSBhdHRyaWJ1dGUKKyAqCURTMCAoUFJSUlsxNl0pCQkt PiBkZXZpY2UgbWVtb3J5IHNoYXJlYWJsZSBhdHRyaWJ1dGUgKFMgPSAwKQorICoJRFMxIChQ UlJSWzE3XSkJCS0+IGRldmljZSBtZW1vcnkgc2hhcmVhYmxlIGF0dHJpYnV0ZSAoUyA9IDEp CisgKglOUzAgKFBSUlJbMThdKQkJLT4gbm9ybWFsIG1lbW9yeSBzaGFyZWFibGUgYXR0cmli dXRlIChTID0gMCkKKyAqCU5TMSAoUFJSUlsxOV0pCQktPiBub3JtYWwgbWVtb3J5IHNoYXJl YWJsZSBhdHRyaWJ1dGUgKFMgPSAxKQorICoKKyAqIE5NUlIJCS0+IGNhY2hlIHBvbGljeSAo bm8gY2FjaGUsIFdULCBXQiwgV0JXQSkKKyAqCUlSIChOTVJSWzJuKzE7Mm5dKQktPiBpbm5l ciBjYWNoZSBwcm9wZXJ0eQorICoJT1IgKE5NUlJbMm4rMTc7Mm4rMTZdKQktPiBvdXRlciBj YWNoZSBwcm9wZXJ0eQorICoKKyAqIE1lbW9yeSB0eXBlCQlpbmRleAlUUglJUglPUgorICog U1RST05HTFlfT1JERVJFRAkwCTAwCisgKiBERVZJQ0UJCTEJMDEKKyAqIE5PQ0FDSEUJCTIJ MTAJMDAJMDAKKyAqIElXVF9PV1QJCTMJMTAJMTAJMTAKKyAqIElXQl9PV0IJCTQJMTAJMTEJ MTEKKyAqIElXQkFfT1dCQQkJNQkxMAkwMQkwMQorICogUkVTRVJWRUQJCTYKKyAqIElXQkFf T1dCCQk3CTEwCTAxCTExCisgKgorICogT3RoZXIgYXR0cmlidXRlczoKKyAqCURTMCA9IDAK KyAqCURTMSA9IDEKKyAqCU5TMCA9IDAKKyAqCU5TMSA9IDEKKyAqCisgKglPdXRlciBzaGFy ZWFiaWxpdHkgaXMgaW1wbGVtZW50YXRpb24gZGVwZW5kZW50IGZlYXR1cmUgaW4gYXJtdjcK KyAqCXNwZWNpZmljYXRpb24sIGZvciBub3cgc2FmZSB2YWx1ZSAoZGlzYWJsZSBvdXRlciBz aGFyZWFiaWxpdHkgaXMgdXNlZCkKKyAqCU5PU1swOjddID0gMQogICovCi0jaWYgQVJNX0FS Q0hfNiB8fCBBUk1fQVJDSF83QQotI2lmZGVmIFNNUAotI2RlZmluZSBQVEVfTk9DQUNIRQky Ci0jZWxzZQotI2RlZmluZSBQVEVfTk9DQUNIRQkxCi0jZW5kaWYKLSNkZWZpbmUgUFRFX0NB Q0hFCTQKLSNkZWZpbmUgUFRFX0RFVklDRQkyCi0jZGVmaW5lIFBURV9QQUdFVEFCTEUJNAor CisjZGVmaW5lIFBSUlIJMHhmZjBhOGFhNAorI2RlZmluZSBOTVJSCTB4Yzc4MDQ3ODAKKwor LyoKKyAqIEFSTV9WNiBhbmQgQVJNX1Y3IFRUQlIgYml0IGRlZmluaXRpb24KKyAqLworI2lm IGRlZmluZWQoQVJNX01NVV9WNikgfHwgZGVmaW5lZCAoQVJNX01NVV9WNykKKyNkZWZpbmUg UFRfTk9TCQkoMSA8PCA1KQorI2RlZmluZSBQVF9TCQkoMSA8PCAxKQorI2RlZmluZSBQVF9P VVRFUl9OQwkwCisjZGVmaW5lIFBUX09VVEVSX1dUCSgyIDw8IDMpCisjZGVmaW5lIFBUX09V VEVSX1dCCSgzIDw8IDMpCisjZGVmaW5lIFBUX09VVEVSX1dCV0EJKDEgPDwgMykKKyNpZiBk ZWZpbmVkKFNNUCkKKyNkZWZpbmUgUFRfU0hBUkVBQkxFCShQVF9TKQorI2RlZmluZSBQVF9J Tk5FUl9OQwkwCisjZGVmaW5lIFBUX0lOTkVSX1dUCSgxIDw8IDApCisjZGVmaW5lIFBUX0lO TkVSX1dCCSgoMSA8PCAwKSB8ICgxIDw8IDYpKQorI2RlZmluZSBQVF9JTk5FUl9XQldBCSgx IDw8IDYpCiAjZWxzZQorI2RlZmluZSBQVF9TSEFSRUFCTEUJMAorCisvKgorICogSW4gQVJN djYgYW5kIEFSTVY3IHdpdGhvdXQgbXVsdGlwcm9jZXNzb3IgZXh0ZW5zaW9uLAorICogcGFn ZXRhYmxlIG1lbW9yeSBpbm5lciBjYWNoZWFiaWxpdHkgcG9saWN5IGlzIGltcGxlbWVudGF0 aW9uIGRlZmluZWQKKyAqLworI2RlZmluZSBQVF9JTk5FUl9OQwkwCisjZGVmaW5lIFBUX0lO TkVSX1dUCSgxIDw8IDApCisjZGVmaW5lIFBUX0lOTkVSX1dCCSgxIDw8IDApCisjZGVmaW5l IFBUX0lOTkVSX1dCV0EJKDEgPDwgMCkKKyNlbmRpZiAvKiBTTVAgKi8KKworI2RlZmluZSBU VEJfRkxBR1NfMAkoUFRfU0hBUkVBQkxFIHwgUFRfTk9TIHwgUFRfSU5ORVJfTkMgfCBQVF9P VVRFUl9OQykKKyNkZWZpbmUgVFRCX0ZMQUdTXzEJKFBUX1NIQVJFQUJMRSB8IFBUX05PUyB8 IFBUX0lOTkVSX05DIHwgUFRfT1VURVJfTkMpCisjZGVmaW5lIFRUQl9GTEFHU18yCShQVF9T SEFSRUFCTEUgfCBQVF9OT1MgfCBQVF9JTk5FUl9OQyB8IFBUX09VVEVSX05DKQorI2RlZmlu ZSBUVEJfRkxBR1NfMwkoUFRfU0hBUkVBQkxFIHwgUFRfTk9TIHwgUFRfSU5ORVJfV1QgfCBQ VF9PVVRFUl9XVCkKKyNkZWZpbmUgVFRCX0ZMQUdTXzQJKFBUX1NIQVJFQUJMRSB8IFBUX05P UyB8IFBUX0lOTkVSX1dCIHwgUFRfT1VURVJfV0IpCisjZGVmaW5lIFRUQl9GTEFHU181CShQ VF9TSEFSRUFCTEUgfCBQVF9OT1MgfCBQVF9JTk5FUl9XQldBIHwgUFRfT1VURVJfV0JXQSkK KyNkZWZpbmUgVFRCX0ZMQUdTXzYJKFBUX1NIQVJFQUJMRSB8IFBUX05PUyB8IFBUX0lOTkVS X05DIHwgUFRfT1VURVJfTkMpCisjZGVmaW5lIFRUQl9GTEFHU183CShQVF9TSEFSRUFCTEUg fCBQVF9OT1MgfCBQVF9JTk5FUl9XQldBIHwgUFRfT1VURVJfV0IpCisjZW5kaWYgLyogQVJN X01NVV9WNiB8fCBBUk1fTU1VX1Y3ICovCisKKy8qCisgKglQdGUgcmVsYXRlZCBtYWNyb3MK KyAqCisgKglNZW1vcnkgdHlwZXMgd2hlbiB0ZXggcmVtYXAgaXMgZW5hYmxlZCAoYXJtdjYg YW5kIGFybXY3KToKKyAqCTAgLSBzdHJvbmdseSBvcmRlcmVkCisgKgkxIC0gZGV2aWNlIG1l bW9yeSwKKyAqCTIgLSBub3JtYWwgbWVtb3J5LCBub24gY2FjaGVhYmxlCisgKgkzIC0gbm9y bWFsIG1lbW9yeSwgaW5uZXIgd3JpdGUtdGhyb3VnaCwgb3V0ZXIgd3JpdGUtdGhyb3VnaAor ICoJNCAtIG5vcm1hbCBtZW1vcnksIGlubmVyIHdyaXRlLWJhY2ssIG91dGVyIHdyaXRlLWJh Y2sKKyAqCTUgLSBub3JtYWwgbWVtb3J5LCBpbm5lciB3cml0ZS1iYWNrIHdyaXRlLWFsbG9j YXRlLAorICoJCW91dGVyIHdyaXRlLWJhY2sgd3JpdGUtYWxsb2NhdGUKKyAqCTYgLSByZXNl cnZlZCB2YWx1ZQorICoJNyAtIG5vcm1hbCBtZW1vcnksIGlubmVyIHdyaXRlLWJhY2sgd3Jp dGUtYWxsb2NhdGUsIG91dGVyIHdyaXRlLWJhY2sKKyAqCisgKglNZW1vcnkgdHlwZXMgd2hl biB0ZXggcmVtYXAgaXMgZGlzYWJsZWQgLyBub3Qgc3VwcG9ydGVkOgorICoJMCAtIHN0cm9u Z2x5IG9yZGVyZWQKKyAqCTEgLSBkZXZpY2UgbWVtb3J5LCBub24gc2hhcmVhYmxlCisgKgky IC0gZGV2aWNlIG1lbW9yeSwgc2hhcmVhYmxlCisgKgkzIC0gbm9ybWFsIG1lbW9yeSwgbm9u IGNhY2hlYWJsZQorICoJNCAtIG5vcm1hbCBtZW1vcnksIGlubmVyIHdyaXRlLXRocm91Z2gs IG91dGVyIHdyaXRlLXRocm91Z2gKKyAqCTUgLSBub3JtYWwgbWVtb3J5LCBpbm5lciB3cml0 ZS1iYWNrLCBvdXRlciB3cml0ZS1iYWNrCisgKgk2IC0gbm9ybWFsIG1lbW9yeSwgaW5uZXIg d3JpdGUtYmFjayB3cml0ZS1hbGxvY2F0ZSwKKyAqCQlvdXRlciB3cml0ZS1iYWNrIHdyaXRl LWFsbG9jYXRlCisgKi8KKworI2lmIGRlZmluZWQoQVJNX01NVV9WNikgfHwgZGVmaW5lZCAo QVJNX01NVV9WNykKKyNkZWZpbmUgUFRFX05PQ0FDSEUJMgorI2RlZmluZSBQVEVfQ0FDSEUJ MworI2RlZmluZSBQVEVfREVWSUNFCTEKKworLyogVFRCX0ZMQUdTIG51bWJlciBtdXN0IGJl IHRoZSBzYW1lIGFzIFBURV9QQUdFVEFCTEUgdmFsdWUgKi8KKyNkZWZpbmUgUFRFX1BBR0VU QUJMRQkzCisjZGVmaW5lIFRUQl9BVFRSCVRUQl9GTEFHU18zCisjZWxzZSAvKiBBUk1fTU1V X1Y2IHx8IEFSTV9NTVVfVjcgKi8KICNkZWZpbmUgUFRFX05PQ0FDSEUJMQogI2RlZmluZSBQ VEVfQ0FDSEUJMgogI2RlZmluZSBQVEVfUEFHRVRBQkxFCTMKLSNlbmRpZgorI2VuZGlmIC8q IEFSTV9NTVVfVjYgfHwgQVJNX01NVV9WNyAqLwogCi1lbnVtIG1lbV90eXBlIHsKLQlTVFJP TkdfT1JEID0gMCwKLQlERVZJQ0VfTk9TSEFSRSwKLQlERVZJQ0VfU0hBUkUsCi0JTlJNTF9O T0NBQ0hFLAotCU5STUxfSVdUX09XVCwKLQlOUk1MX0lXQl9PV0IsCi0JTlJNTF9JV0JBX09X QkEKLX07CiAKICNpZm5kZWYgTE9DT1JFCiAKQEAgLTM3MCw1NSArNDY0LDYgQEAgZXh0ZXJu IGludCBwbWFwX25lZWRzX3B0ZV9zeW5jOwogI2RlZmluZQlMMV9DX1BST1RPCQkoTDFfVFlQ RV9DKQogI2RlZmluZQlMMl9TX1BST1RPCQkoTDJfVFlQRV9TKQogCi0jaWZuZGVmIFNNUAot I2RlZmluZSBBUk1fTDFTX1NUUk9OR19PUkQJKDApCi0jZGVmaW5lIEFSTV9MMVNfREVWSUNF X05PU0hBUkUJKEwxX1NfVEVYKDIpKQotI2RlZmluZSBBUk1fTDFTX0RFVklDRV9TSEFSRQko TDFfU19CKQotI2RlZmluZSBBUk1fTDFTX05STUxfTk9DQUNIRQkoTDFfU19URVgoMSkpCi0j ZGVmaW5lIEFSTV9MMVNfTlJNTF9JV1RfT1dUCShMMV9TX0MpCi0jZGVmaW5lIEFSTV9MMVNf TlJNTF9JV0JfT1dCCShMMV9TX0N8TDFfU19CKQotI2RlZmluZSBBUk1fTDFTX05STUxfSVdC QV9PV0JBCShMMV9TX1RFWCgxKXxMMV9TX0N8TDFfU19CKQotCi0jZGVmaW5lIEFSTV9MMkxf U1RST05HX09SRAkoMCkKLSNkZWZpbmUgQVJNX0wyTF9ERVZJQ0VfTk9TSEFSRQkoTDJfTF9U RVgoMikpCi0jZGVmaW5lIEFSTV9MMkxfREVWSUNFX1NIQVJFCShMMl9CKQotI2RlZmluZSBB Uk1fTDJMX05STUxfTk9DQUNIRQkoTDJfTF9URVgoMSkpCi0jZGVmaW5lIEFSTV9MMkxfTlJN TF9JV1RfT1dUCShMMl9DKQotI2RlZmluZSBBUk1fTDJMX05STUxfSVdCX09XQgkoTDJfQ3xM Ml9CKQotI2RlZmluZSBBUk1fTDJMX05STUxfSVdCQV9PV0JBCShMMl9MX1RFWCgxKXxMMl9D fEwyX0IpCi0KLSNkZWZpbmUgQVJNX0wyU19TVFJPTkdfT1JECSgwKQotI2RlZmluZSBBUk1f TDJTX0RFVklDRV9OT1NIQVJFCShMMl9TX1RFWCgyKSkKLSNkZWZpbmUgQVJNX0wyU19ERVZJ Q0VfU0hBUkUJKEwyX0IpCi0jZGVmaW5lIEFSTV9MMlNfTlJNTF9OT0NBQ0hFCShMMl9TX1RF WCgxKSkKLSNkZWZpbmUgQVJNX0wyU19OUk1MX0lXVF9PV1QJKEwyX0MpCi0jZGVmaW5lIEFS TV9MMlNfTlJNTF9JV0JfT1dCCShMMl9DfEwyX0IpCi0jZGVmaW5lIEFSTV9MMlNfTlJNTF9J V0JBX09XQkEJKEwyX1NfVEVYKDEpfEwyX0N8TDJfQikKLSNlbHNlCi0jZGVmaW5lIEFSTV9M MVNfU1RST05HX09SRAkoMCkKLSNkZWZpbmUgQVJNX0wxU19ERVZJQ0VfTk9TSEFSRQkoTDFf U19URVgoMikpCi0jZGVmaW5lIEFSTV9MMVNfREVWSUNFX1NIQVJFCShMMV9TX0IpCi0jZGVm aW5lIEFSTV9MMVNfTlJNTF9OT0NBQ0hFCShMMV9TX1RFWCgxKXxMMV9TSEFSRUQpCi0jZGVm aW5lIEFSTV9MMVNfTlJNTF9JV1RfT1dUCShMMV9TX0N8TDFfU0hBUkVEKQotI2RlZmluZSBB Uk1fTDFTX05STUxfSVdCX09XQgkoTDFfU19DfEwxX1NfQnxMMV9TSEFSRUQpCi0jZGVmaW5l IEFSTV9MMVNfTlJNTF9JV0JBX09XQkEJKEwxX1NfVEVYKDEpfEwxX1NfQ3xMMV9TX0J8TDFf U0hBUkVEKQotCi0jZGVmaW5lIEFSTV9MMkxfU1RST05HX09SRAkoMCkKLSNkZWZpbmUgQVJN X0wyTF9ERVZJQ0VfTk9TSEFSRQkoTDJfTF9URVgoMikpCi0jZGVmaW5lIEFSTV9MMkxfREVW SUNFX1NIQVJFCShMMl9CKQotI2RlZmluZSBBUk1fTDJMX05STUxfTk9DQUNIRQkoTDJfTF9U RVgoMSl8TDJfU0hBUkVEKQotI2RlZmluZSBBUk1fTDJMX05STUxfSVdUX09XVAkoTDJfQ3xM Ml9TSEFSRUQpCi0jZGVmaW5lIEFSTV9MMkxfTlJNTF9JV0JfT1dCCShMMl9DfEwyX0J8TDJf U0hBUkVEKQotI2RlZmluZSBBUk1fTDJMX05STUxfSVdCQV9PV0JBCShMMl9MX1RFWCgxKXxM Ml9DfEwyX0J8TDJfU0hBUkVEKQotCi0jZGVmaW5lIEFSTV9MMlNfU1RST05HX09SRAkoMCkK LSNkZWZpbmUgQVJNX0wyU19ERVZJQ0VfTk9TSEFSRQkoTDJfU19URVgoMikpCi0jZGVmaW5l IEFSTV9MMlNfREVWSUNFX1NIQVJFCShMMl9CKQotI2RlZmluZSBBUk1fTDJTX05STUxfTk9D QUNIRQkoTDJfU19URVgoMSl8TDJfU0hBUkVEKQotI2RlZmluZSBBUk1fTDJTX05STUxfSVdU X09XVAkoTDJfQ3xMMl9TSEFSRUQpCi0jZGVmaW5lIEFSTV9MMlNfTlJNTF9JV0JfT1dCCShM Ml9DfEwyX0J8TDJfU0hBUkVEKQotI2RlZmluZSBBUk1fTDJTX05STUxfSVdCQV9PV0JBCShM Ml9TX1RFWCgxKXxMMl9DfEwyX0J8TDJfU0hBUkVEKQotI2VuZGlmIC8qIFNNUCAqLwogI2Vu ZGlmIC8qIEFSTV9OTU1VUyA+IDEgKi8KIAogI2lmIChBUk1fTU1VX1NBMSA9PSAxKSAmJiAo QVJNX05NTVVTID09IDEpCkBAIC00MjcsNiArNDcyLDEyIEBAIGV4dGVybiBpbnQgcG1hcF9u ZWVkc19wdGVfc3luYzsKICNlbGlmIGRlZmluZWQoQ1BVX1hTQ0FMRV84MTM0MikKICNkZWZp bmUgUE1BUF9ORUVEU19QVEVfU1lOQwkxCiAjZGVmaW5lIFBNQVBfSU5DTFVERV9QVEVfU1lO QworI2VsaWYgZGVmaW5lZChBUk1fQVJDSF82KSB8fCBkZWZpbmVkKEFSTV9BUkNIXzdBKQor I2lmIFBURV9QQUdFVEFCTEUgPiAyCisjZGVmaW5lIFBNQVBfTkVFRFNfUFRFX1NZTkMJMQor I2Vsc2UKKyNkZWZpbmUgUE1BUF9ORUVEU19QVEVfU1lOQwkwCisjZW5kaWYgLyogUFRFX1BB R0VUQUJMRSA+IDIgKi8KICNlbGlmIChBUk1fTU1VX1NBMSA9PSAwKQogI2RlZmluZQlQTUFQ X05FRURTX1BURV9TWU5DCTAKICNlbmRpZgo= --------------020100070900070501080600 Content-Type: text/plain; charset=UTF-8; name="commit-1" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="commit-1" Y29tbWl0IGM5ZDY2Njg1MzVkZDRhMThhMWE3NzNiMzdmMDJmODQ0ODJmOWRiODQKQXV0aG9y OiBMdWthc3ogUGxhY2hubyA8bHVrQHNlbWloYWxmLmNvbT4KRGF0ZTogICBNb24gTm92IDE5 IDEwOjE0OjQxIDIwMTIgKzAxMDAKCiAgICBhcm0vc21wOiBWYXJpb3VzIGZpeGVzIGZvciBl bmFibGluZyBTTVAgb3BlcmF0aW9uIG9uIEFSTSBzeXN0ZW1zCiAgICAKICAgICAtIEN1cnJl bnRseSBsaWJjIGlzIGJ1aWx0IHdpdGggQVJNIFNNUCBzdXBwb3J0IG9ubHkgaWYgc3BlY2lm aWVkIGFyY2hpdGVjdHVyZSBpcyBvbmUKICAgICAgIG9mIHRoZSBmb2xsb3dpbmc6CiAgICAg ICAgLSBhcm12NmsKICAgICAgICAtIGFybXY2emsKICAgICAgICAtIGFybXY3CiAgICAgICAg LSBhcm12N2EKICAgICAtIE5vbmUgb2YgY3VycmVudGx5IGF2YWlsYWJsZSBDUFVUWVBFIG9w dGlvbnMgYWxsb3dzIHVzIHRvIGNob29zZSBvbmUgb2YgYXJjaGl0ZWN0dXJlcwogICAgICAg YWJvdmUsIHRodXMgYWRkaXRpb25hbCB0YXJnZXQgaXMgbmVlZGVkLiBGcm9tIG5vdyBvbiB3 b3JsZCBmb3IgbXVsdGljb3JlIEFSTSB0YXJnZXRzCiAgICAgICBzaG91bGQgYmUgYnVpbHQg d2l0aCAtQ1BVVFlQRT1hcm12Nmsgb3IgLUNQVVRZUEU9Y29ydGV4YQogICAgIC0gQ29tcGxl dGVseSByZW1vdmUgb3B0aW9uIEFSTV9UUF9BRERSRVNTIChubyBsb25nZXIgdXNlZCkKICAg ICAtIFByb3BhZ2F0ZSBUTEIgbWFpbnRlbmFuY2Ugb3BlcmF0aW9ucyBpbiBTTVAgbW9kZSAo Zm9sbG93IHVwIGZvciBjaGFuZ2VzIHByb3Bvc2VkCiAgICAgICBieSBHaW92YW5uaSBUcmVt YXRlcnJhKQogICAgIC0gcGNwdXAgcG9pbnRlciBpcyBjb21tb24gZm9yIGV2ZXJ5IGNvcmUs IHRodXMgdXNpbmcgaXQgaXMgbm90IFNNUCBzYWZlCgpkaWZmIC0tZ2l0IGEvc2hhcmUvbWsv YnNkLmNwdS5tayBiL3NoYXJlL21rL2JzZC5jcHUubWsKaW5kZXggNGY5NTI3Yy4uNDdjNDdj NyAxMDA2NDQKLS0tIGEvc2hhcmUvbWsvYnNkLmNwdS5taworKysgYi9zaGFyZS9tay9ic2Qu Y3B1Lm1rCkBAIC05NywxMyArOTcsMTUgQEAgX0NQVUNGTEFHUyA9IC1tYXJjaD0ke0NQVVRZ UEV9CiAuICBpZiAke0NQVVRZUEV9ID09ICJ4c2NhbGUiCiAjWFhYOiBnY2MgZG9lc24ndCBz ZWVtIHRvIGxpa2UgLW1jcHU9eHNjYWxlLCBhbmQgZGllcyB3aGlsZSByZWJ1aWxkaW5nIGl0 c2VsZgogI19DUFVDRkxBR1MgPSAtbWNwdT14c2NhbGUKLV9DUFVDRkxBR1MgPSAtbWFyY2g9 YXJtdjV0ZSAtRF9fWFNDQUxFX18gLURBUk1fV0FOVF9UUF9BRERSRVNTCitfQ1BVQ0ZMQUdT ID0gLW1hcmNoPWFybXY1dGUgLURfX1hTQ0FMRV9fCiAuIGVsaWYgJHtDUFVUWVBFfSA9PSAi YXJtdjYiCiBfQ1BVQ0ZMQUdTID0gLW1hcmNoPSR7Q1BVVFlQRX0gLURBUk1fQVJDSF82PTEK Ky4gZWxpZiAke0NQVVRZUEV9ID09ICJhcm12NmsiCitfQ1BVQ0ZMQUdTID0gLW1hcmNoPSR7 Q1BVVFlQRX0gLURBUk1fQVJDSF82PTEKIC4gZWxpZiAke0NQVVRZUEV9ID09ICJjb3J0ZXhh IgotX0NQVUNGTEFHUyA9IC1tYXJjaD1hcm12NiAtREFSTV9BUkNIXzY9MSAtbWZwdT12ZnAK K19DUFVDRkxBR1MgPSAtbWFyY2g9YXJtdjZrIC1EQVJNX0FSQ0hfNj0xIC1tZnB1PXZmcAog LiAgZWxzZQotX0NQVUNGTEFHUyA9IC1tY3B1PSR7Q1BVVFlQRX0gLURBUk1fV0FOVF9UUF9B RERSRVNTCitfQ1BVQ0ZMQUdTID0gLW1jcHU9JHtDUFVUWVBFfQogLiAgZW5kaWYKIC4gZWxp ZiAke01BQ0hJTkVfQVJDSH0gPT0gInBvd2VycGMiCiAuICBpZiAke0NQVVRZUEV9ID09ICJl NTAwIgpkaWZmIC0tZ2l0IGEvc3lzL2FybS9hcm0vbG9jb3JlLlMgYi9zeXMvYXJtL2FybS9s b2NvcmUuUwppbmRleCBlODE5MTJjLi45OWIyMTRhIDEwMDY0NAotLS0gYS9zeXMvYXJtL2Fy bS9sb2NvcmUuUworKysgYi9zeXMvYXJtL2FybS9sb2NvcmUuUwpAQCAtMTY2LDcgKzE2Niwx MSBAQCBMdW5tYXBwZWQ6CiAJb3JyIAlyMCwgcjAsICMyCQkvKiBTZXQgVFRCIHNoYXJlZCBt ZW1vcnkgZmxhZyAqLwogI2VuZGlmCiAJbWNyCXAxNSwgMCwgcjAsIGMyLCBjMCwgMAkvKiBT ZXQgVFRCICovCi0JbWNyCXAxNSwgMCwgcjAsIGM4LCBjNywgMAkvKiBGbHVzaCBUTEIgKi8K KyNpZmRlZiBTTVAKKwltY3IJcDE1LCAwLCByMCwgYzgsIGMzLCAwCS8qIEludmFsaWRhdGUg SStEIFRMQnMgSW5uZXIgU2hhcmVhYmxlICovCisjZWxzZQorCW1jcglwMTUsIDAsIHIwLCBj OCwgYzcsIDAJLyogSW52YWxpZGF0ZSBJK0QgVExCcyAqLworI2VuZGlmCiAKICNpZiBkZWZp bmVkKENQVV9BUk0xMSkgfHwgZGVmaW5lZChDUFVfQ09SVEVYQSkgfHwgZGVmaW5lZChDUFVf TVZfUEo0QikKIAltb3YJcjAsICMwCkBAIC0zNjEsNyArMzY1LDExIEBAIEx0YWc6CiAJb3Jy IAlyMCwgcjAsICMwCQkvKiBTZXQgVFRCIHNoYXJlZCBtZW1vcnkgZmxhZyAqLwogI2VuZGlm CiAJbWNyCXAxNSwgMCwgcjAsIGMyLCBjMCwgMAkvKiBTZXQgVFRCICovCi0JbWNyCXAxNSwg MCwgcjAsIGM4LCBjNywgMAkvKiBGbHVzaCBUTEIgKi8KKyNpZmRlZiBTTVAKKwltY3IJcDE1 LCAwLCByMCwgYzgsIGMzLCAwCS8qIEludmFsaWRhdGUgSStEIFRMQnMgSW5uZXIgU2hhcmVh YmxlICovCisjZWxzZQorCW1jcglwMTUsIDAsIHIwLCBjOCwgYzcsIDAJLyogSW52YWxpZGF0 ZSBJK0QgVExCcyAqLworI2VuZGlmCiAKICNpZiBkZWZpbmVkKENQVV9BUk0xMSkgfHwgZGVm aW5lZChDUFVfTVZfUEo0QikgfHwgZGVmaW5lZChDUFVfQ09SVEVYQSkKIAltb3YJcjAsICMw CmRpZmYgLS1naXQgYS9zeXMvYXJtL2luY2x1ZGUvcGNwdS5oIGIvc3lzL2FybS9pbmNsdWRl L3BjcHUuaAppbmRleCBmMTJmOTAzLi40M2ZmYjQ0IDEwMDY0NAotLS0gYS9zeXMvYXJtL2lu Y2x1ZGUvcGNwdS5oCisrKyBiL3N5cy9hcm0vaW5jbHVkZS9wY3B1LmgKQEAgLTEwMCw4ICsx MDAsOCBAQCBzZXRfdGxzKHZvaWQgKnRscykKICNkZWZpbmUJUENQVV9HRVQobWVtYmVyKQko Z2V0X3BjcHUoKS0+cGNfICMjIG1lbWJlcikKICNkZWZpbmUJUENQVV9BREQobWVtYmVyLCB2 YWx1ZSkJKGdldF9wY3B1KCktPnBjXyAjIyBtZW1iZXIgKz0gKHZhbHVlKSkKICNkZWZpbmUJ UENQVV9JTkMobWVtYmVyKQlQQ1BVX0FERChtZW1iZXIsIDEpCi0jZGVmaW5lCVBDUFVfUFRS KG1lbWJlcikJKCZwY3B1cC0+cGNfICMjIG1lbWJlcikKLSNkZWZpbmUJUENQVV9TRVQobWVt YmVyLHZhbHVlKQkocGNwdXAtPnBjXyAjIyBtZW1iZXIgPSAodmFsdWUpKQorI2RlZmluZQlQ Q1BVX1BUUihtZW1iZXIpCSgmZ2V0X3BjcHUoKS0+cGNfICMjIG1lbWJlcikKKyNkZWZpbmUJ UENQVV9TRVQobWVtYmVyLHZhbHVlKQkoZ2V0X3BjcHUoKS0+cGNfICMjIG1lbWJlciA9ICh2 YWx1ZSkpCiAKIHZvaWQgcGNwdTBfaW5pdCh2b2lkKTsKICNlbmRpZgkvKiBfS0VSTkVMICov CmRpZmYgLS1naXQgYS9zeXMvY29uZi9vcHRpb25zLmFybSBiL3N5cy9jb25mL29wdGlvbnMu YXJtCmluZGV4IDJmZTdiOWYuLmU5YzgxODcgMTAwNjQ0Ci0tLSBhL3N5cy9jb25mL29wdGlv bnMuYXJtCisrKyBiL3N5cy9jb25mL29wdGlvbnMuYXJtCkBAIC03LDcgKzcsNiBAQCBBUk1f TDJfUElQVAkJb3B0X2dsb2JhbC5oCiBBUk1fTUFOWV9CT0FSRAkJb3B0X2dsb2JhbC5oCiBB Uk1fVVNFX1NNQUxMX0FMTE9DCW9wdF9nbG9iYWwuaAogQVJNX1ZGUF9TVVBQT1JUCQlvcHRf Z2xvYmFsLmgKLUFSTV9XQU5UX1RQX0FERFJFU1MJb3B0X2dsb2JhbC5oCiBDT1VOVFNfUEVS X1NFQwkJb3B0X3RpbWVyLmgKIENQVV9BUk05CQlvcHRfZ2xvYmFsLmgKIENQVV9BUk05RQkJ b3B0X2dsb2JhbC5oCg== --------------020100070900070501080600-- From owner-freebsd-arm@FreeBSD.ORG Mon Nov 19 23:08:47 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id B4AE6F79 for ; Mon, 19 Nov 2012 23:08:47 +0000 (UTC) (envelope-from giovanni.trematerra@gmail.com) Received: from mail-qa0-f54.google.com (mail-qa0-f54.google.com [209.85.216.54]) by mx1.freebsd.org (Postfix) with ESMTP id 608488FC0C for ; Mon, 19 Nov 2012 23:08:47 +0000 (UTC) Received: by mail-qa0-f54.google.com with SMTP id g24so467118qab.13 for ; Mon, 19 Nov 2012 15:08:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=LD3XMV7oX//XuTXt9RTF3TiiuHVUNOTiaK6Mr1PQeIY=; b=EZvIorFRcsymJRbGm3bPC1oubkGWh0SG88ft1iqHbzPte/z+UU8jK23TQzOHavc/Nu 7IoOdDY+6kt4gwI0a/i89Yo1us61C11Zbw9pmFr0yyGVP5+AeLvKcqDuxmEFuncQUARq FxuLz9h2fbvUUR33DOrAMBtaXCWbOswRdVQ+jmEG2PMh7hg1UCo43i7P30YpI0YpDFit fFe3Uwq06ZtR5lDziSc39NcbzYZ4n+JaX9JtA78avCPSC307iikkki4eO/A6K5/Hc0Av jjNzchXvVNGrYHVYShigyatH0x4veb9vpKHiUkRMzU5cFfWpCjwE/Uije8xQRFaYXxcs Xhuw== MIME-Version: 1.0 Received: by 10.49.97.3 with SMTP id dw3mr15051447qeb.35.1353366521299; Mon, 19 Nov 2012 15:08:41 -0800 (PST) Sender: giovanni.trematerra@gmail.com Received: by 10.229.117.1 with HTTP; Mon, 19 Nov 2012 15:08:41 -0800 (PST) In-Reply-To: <50AA4E87.3000505@semihalf.com> References: <50AA4E87.3000505@semihalf.com> Date: Tue, 20 Nov 2012 00:08:41 +0100 X-Google-Sender-Auth: a0nWk7xQf_fjLskjRfUgZOrampI Message-ID: Subject: Re: ARM/SMP, Some patches for review. From: Giovanni Trematerra To: =?UTF-8?B?xYF1a2FzeiBQxYJhY2hubw==?= Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Cc: freebsd-arm@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Nov 2012 23:08:47 -0000 On Mon, Nov 19, 2012 at 4:21 PM, =C5=81ukasz P=C5=82achno wrote: > Hi, > > I would like to propose few changes for ARM specific code. > Three attached patches for freebsd-current allows building SMP-safe world > for ARM targets and turns on TEX remap for ARMv6 and ARMv7 targets. > > More details inside patch files. > > Change introduced by "commit-2" removes armv7 targets (armv7 and pj4b) fr= om > kernel.tramp. > AFAIK this feature is not working properly for armv7 targets and is causi= ng > problem during compilation: > - LOCORE is defined during kernel compilation but not defined during > kernel.tramp compilation, so #include pmap.h causes build errors. > > I do not think adding hack like this: > #ifndef LOCORE > #define LOCORE > #endif > > to allow building something that is already broken is a good idea, so I > removed cpufunc_asm_pj4b.S and cpufunc_asm_armv7.S from Makefile.arm In commit-2.txt you should include style changes in sys/arm/arm/cpufunc_asm_armv7.S into a different patch. @@ -63,7 +64,6 @@ FILES_CPU_FUNC =3D $S/$M/$M/cpufunc_asm_arm7tdmi.S \ $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S \ $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S You left a trailing back slash but beside that you should clean up sys/arm/arm/elf_trampoline.c and not make kernel.tramp to build at all for armv7 cpus or you'll end up with a linker error during generation of the kernel.tramp. -- Gianni From owner-freebsd-arm@FreeBSD.ORG Wed Nov 21 14:18:34 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 2F711F76; Wed, 21 Nov 2012 14:18:34 +0000 (UTC) (envelope-from luk@semihalf.com) Received: from smtp.semihalf.com (smtp.semihalf.com [213.17.239.109]) by mx1.freebsd.org (Postfix) with ESMTP id DEFBC8FC13; Wed, 21 Nov 2012 14:18:32 +0000 (UTC) Received: from localhost (unknown [213.17.239.109]) by smtp.semihalf.com (Postfix) with ESMTP id B4641C401C; Wed, 21 Nov 2012 15:18:31 +0100 (CET) X-Virus-Scanned: by amavisd-new at semihalf.com Received: from smtp.semihalf.com ([213.17.239.109]) by localhost (smtp.semihalf.com [213.17.239.109]) (amavisd-new, port 10024) with ESMTP id iWzam9ziDlA0; Wed, 21 Nov 2012 15:18:28 +0100 (CET) Received: from [10.0.2.115] (cardhu.semihalf.com [213.17.239.108]) by smtp.semihalf.com (Postfix) with ESMTPSA id 9FD97C3846; Wed, 21 Nov 2012 15:18:28 +0100 (CET) Message-ID: <50ACE2B4.8010904@semihalf.com> Date: Wed, 21 Nov 2012 15:18:28 +0100 From: =?UTF-8?B?xYF1a2FzeiBQxYJhY2hubw==?= User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:16.0) Gecko/20121028 Thunderbird/16.0.2 MIME-Version: 1.0 To: Giovanni Trematerra Subject: Re: ARM/SMP, Some patches for review. References: <50AA4E87.3000505@semihalf.com> In-Reply-To: Content-Type: multipart/mixed; boundary="------------040005010806010909090200" Cc: freebsd-arm@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Nov 2012 14:18:34 -0000 This is a multi-part message in MIME format. --------------040005010806010909090200 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 20.11.2012 00:08, Giovanni Trematerra wrote: > On Mon, Nov 19, 2012 at 4:21 PM, Łukasz Płachno wrote: >> Hi, >> >> I would like to propose few changes for ARM specific code. >> Three attached patches for freebsd-current allows building SMP-safe world >> for ARM targets and turns on TEX remap for ARMv6 and ARMv7 targets. >> >> More details inside patch files. >> >> Change introduced by "commit-2" removes armv7 targets (armv7 and pj4b) from >> kernel.tramp. >> AFAIK this feature is not working properly for armv7 targets and is causing >> problem during compilation: >> - LOCORE is defined during kernel compilation but not defined during >> kernel.tramp compilation, so #include pmap.h causes build errors. >> >> I do not think adding hack like this: >> #ifndef LOCORE >> #define LOCORE >> #endif >> >> to allow building something that is already broken is a good idea, so I >> removed cpufunc_asm_pj4b.S and cpufunc_asm_armv7.S from Makefile.arm > > In commit-2.txt > you should include style changes in sys/arm/arm/cpufunc_asm_armv7.S > into a different patch. fixed > > @@ -63,7 +64,6 @@ FILES_CPU_FUNC = $S/$M/$M/cpufunc_asm_arm7tdmi.S \ > $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ > $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S \ > $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ > - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S > > You left a trailing back slash but beside that you should clean up > sys/arm/arm/elf_trampoline.c > and not make kernel.tramp to build at all for armv7 cpus or you'll end > up with a linker error > during generation of the kernel.tramp. > Fixed, updated set of patches is attached. - TEX remap is supported only for armv6 (changed to avoid breaking armv6 targets) - Fixed issues with build for pre-armv6 targets (tested with make tinderbox TARGETS=arm Regards, Łukasz Płachno --------------040005010806010909090200 Content-Type: text/x-patch; name="1_SMP_fixes.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="1_SMP_fixes.diff" commit 6d33f52444f4b52563c470b2a4c1e82a8b8dae25 Author: Lukasz Plachno Date: Mon Nov 19 10:14:41 2012 +0100 arm/smp: Various fixes for enabling SMP operation on ARM systems - Currently libc is built with ARM SMP support only if specified architecture is one of the following: - armv6k - armv6zk - armv7 - armv7a - None of currently available CPUTYPE options allows us to choose one of architectures above, thus additional target is needed. From now on world for multicore ARM targets should be built with -CPUTYPE=armv6k or -CPUTYPE=cortexa - Completely remove option ARM_TP_ADDRESS (no longer used) - Propagate TLB maintenance operations in SMP mode (follow up for changes proposed by Giovanni Trematerra) - pcpup pointer is common for every core, thus using it is not SMP safe diff --git a/share/mk/bsd.cpu.mk b/share/mk/bsd.cpu.mk index 747dd29..76d7cfc 100644 --- a/share/mk/bsd.cpu.mk +++ b/share/mk/bsd.cpu.mk @@ -98,13 +98,15 @@ _CPUCFLAGS = -march=${CPUTYPE} . if ${CPUTYPE} == "xscale" #XXX: gcc doesn't seem to like -mcpu=xscale, and dies while rebuilding itself #_CPUCFLAGS = -mcpu=xscale -_CPUCFLAGS = -march=armv5te -D__XSCALE__ -DARM_WANT_TP_ADDRESS +_CPUCFLAGS = -march=armv5te -D__XSCALE__ . elif ${CPUTYPE} == "armv6" _CPUCFLAGS = -march=${CPUTYPE} -DARM_ARCH_6=1 +. elif ${CPUTYPE} == "armv6k" +_CPUCFLAGS = -march=${CPUTYPE} -DARM_ARCH_6=1 . elif ${CPUTYPE} == "cortexa" -_CPUCFLAGS = -march=armv6 -DARM_ARCH_6=1 -mfpu=vfp +_CPUCFLAGS = -march=armv6k -DARM_ARCH_6=1 -mfpu=vfp . else -_CPUCFLAGS = -mcpu=${CPUTYPE} -DARM_WANT_TP_ADDRESS +_CPUCFLAGS = -mcpu=${CPUTYPE} . endif . elif ${MACHINE_ARCH} == "powerpc" . if ${CPUTYPE} == "e500" diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S index e81912c..99b214a 100644 --- a/sys/arm/arm/locore.S +++ b/sys/arm/arm/locore.S @@ -166,7 +166,11 @@ Lunmapped: orr r0, r0, #2 /* Set TTB shared memory flag */ #endif mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ - mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ +#ifdef SMP + mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */ +#else + mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ +#endif #if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) mov r0, #0 @@ -361,7 +365,11 @@ Ltag: orr r0, r0, #0 /* Set TTB shared memory flag */ #endif mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ - mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ +#ifdef SMP + mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */ +#else + mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ +#endif #if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) mov r0, #0 diff --git a/sys/arm/include/pcpu.h b/sys/arm/include/pcpu.h index f12f903..43ffb44 100644 --- a/sys/arm/include/pcpu.h +++ b/sys/arm/include/pcpu.h @@ -100,8 +100,8 @@ set_tls(void *tls) #define PCPU_GET(member) (get_pcpu()->pc_ ## member) #define PCPU_ADD(member, value) (get_pcpu()->pc_ ## member += (value)) #define PCPU_INC(member) PCPU_ADD(member, 1) -#define PCPU_PTR(member) (&pcpup->pc_ ## member) -#define PCPU_SET(member,value) (pcpup->pc_ ## member = (value)) +#define PCPU_PTR(member) (&get_pcpu()->pc_ ## member) +#define PCPU_SET(member,value) (get_pcpu()->pc_ ## member = (value)) void pcpu0_init(void); #endif /* _KERNEL */ diff --git a/sys/conf/options.arm b/sys/conf/options.arm index 2fe7b9f..e9c8187 100644 --- a/sys/conf/options.arm +++ b/sys/conf/options.arm @@ -7,7 +7,6 @@ ARM_L2_PIPT opt_global.h ARM_MANY_BOARD opt_global.h ARM_USE_SMALL_ALLOC opt_global.h ARM_VFP_SUPPORT opt_global.h -ARM_WANT_TP_ADDRESS opt_global.h COUNTS_PER_SEC opt_timer.h CPU_ARM9 opt_global.h CPU_ARM9E opt_global.h --------------040005010806010909090200 Content-Type: text/x-patch; name="2_ARM_cleanup.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="2_ARM_cleanup.diff" commit 7d7949d069def8824c549fd22fe51ba44fba9030 Author: Lukasz Plachno Date: Tue Nov 20 09:20:35 2012 +0100 arm: Cleanup in ARM specific code - Unify descriptions for cache and TLB maintenance operations - Use architecture macros instead of CPU specific ones in generic code diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S index 58f295c..03561b8 100644 --- a/sys/arm/arm/cpufunc_asm_armv7.S +++ b/sys/arm/arm/cpufunc_asm_armv7.S @@ -71,9 +71,9 @@ ENTRY(armv7_setttb) orr r0, r0, #PT_ATTR mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */ #ifdef SMP - mcr p15, 0, r0, c8, c3, 0 /* invalidate I+D TLBs Inner Shareable*/ + mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */ #else - mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ + mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ #endif dsb isb @@ -82,11 +82,11 @@ ENTRY(armv7_setttb) ENTRY(armv7_tlb_flushID) dsb #ifdef SMP - mcr p15, 0, r0, c8, c3, 0 /* flush I+D tlb */ - mcr p15, 0, r0, c7, c1, 6 /* flush BTB */ + mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */ + mcr p15, 0, r0, c7, c1, 6 /* Flush BTB Inner Shareable */ #else - mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ - mcr p15, 0, r0, c7, c5, 6 /* flush BTB */ + mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ + mcr p15, 0, r0, c7, c5, 6 /* Flush BTB */ #endif dsb isb @@ -96,10 +96,10 @@ ENTRY(armv7_tlb_flushID_SE) ldr r1, .Lpage_mask bic r0, r0, r1 #ifdef SMP - mcr p15, 0, r0, c8, c3, 1 /* flush D tlb single entry Inner Shareable*/ + mcr p15, 0, r0, c8, c3, 1 /* Invalidate I+D TLB single entry Inner Shareable */ mcr p15, 0, r0, c7, c1, 6 /* flush BTB Inner Shareable */ #else - mcr p15, 0, r0, c8, c7, 1 /* flush D tlb single entry */ + mcr p15, 0, r0, c8, c7, 1 /* Invalidate I+D TLB single entry Inner Shareable */ mcr p15, 0, r0, c7, c5, 6 /* flush BTB */ #endif dsb @@ -262,9 +262,9 @@ ENTRY(armv7_context_switch) mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ #ifdef SMP - mcr p15, 0, r0, c8, c3, 0 /* and flush the I+D tlbs Inner Sharable */ + mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */ #else - mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */ + mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ #endif dsb isb diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S index 99b214a..d541f39 100644 --- a/sys/arm/arm/locore.S +++ b/sys/arm/arm/locore.S @@ -172,7 +172,7 @@ Lunmapped: mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ #endif -#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) +#if (ARM_ARCH_6 + ARM_ARCH_7A) != 0 mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ #endif @@ -182,7 +182,7 @@ Lunmapped: mcr p15, 0, r0, c3, c0, 0 /* Enable MMU */ mrc p15, 0, r0, c1, c0, 0 -#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) +#if (ARM_ARCH_6 + ARM_ARCH_7A) != 0 orr r0, r0, #CPU_CONTROL_V6_EXTPAGE #endif orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE) @@ -371,7 +371,7 @@ Ltag: mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ #endif -#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) +#if (ARM_ARCH_6 + ARM_ARCH_7A) != 0 mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ #endif @@ -383,7 +383,7 @@ Ltag: mcr p15, 0, r0, c3, c0, 0 /* Enable MMU */ mrc p15, 0, r0, c1, c0, 0 -#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) +#if (ARM_ARCH_6 + ARM_ARCH_7A) != 0 orr r0, r0, #CPU_CONTROL_V6_EXTPAGE #endif orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE) diff --git a/sys/arm/arm/machdep.c b/sys/arm/arm/machdep.c index 17a60c2..11714da 100644 --- a/sys/arm/arm/machdep.c +++ b/sys/arm/arm/machdep.c @@ -834,7 +834,7 @@ fake_preload_metadata(struct arm_boot_params *abp __unused) void pcpu0_init(void) { -#if ARM_ARCH_6 || ARM_ARCH_7A || defined(CPU_MV_PJ4B) +#if ARM_ARCH_6 || ARM_ARCH_7A set_pcpu(pcpup); #endif pcpu_init(pcpup, 0, sizeof(struct pcpu)); --------------040005010806010909090200 Content-Type: text/x-patch; name="3_kernel_trampoline.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="3_kernel_trampoline.diff" commit a9c6363aa6e49ba667d145a5ffa0b4c87a551e7c Author: Lukasz Plachno Date: Tue Nov 20 13:14:18 2012 +0100 arm: Remove armv7 targets from kernel.trampoline - armv7 targets are not working currently - add debug kernel map for build targets diff --git a/sys/arm/arm/elf_trampoline.c b/sys/arm/arm/elf_trampoline.c index 2a218bf..c47afa6 100644 --- a/sys/arm/arm/elf_trampoline.c +++ b/sys/arm/arm/elf_trampoline.c @@ -74,26 +74,18 @@ void __startC(void); #define cpu_idcache_wbinv_all xscale_cache_purgeID #elif defined(CPU_XSCALE_81342) #define cpu_idcache_wbinv_all xscalec3_cache_purgeID -#elif defined(CPU_MV_PJ4B) -#if !defined(SOC_MV_ARMADAXP) -#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all #else -#define cpu_idcache_wbinv_all() armadaxp_idcache_wbinv_all +#define cpu_idcache_wbinv_all() #endif -#endif /* CPU_MV_PJ4B */ + #ifdef CPU_XSCALE_81342 #define cpu_l2cache_wbinv_all xscalec3_l2cache_purge #elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) #define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all -#elif defined(CPU_CORTEXA) -#define cpu_idcache_wbinv_all armv7_idcache_wbinv_all -#define cpu_l2cache_wbinv_all() #else -#define cpu_l2cache_wbinv_all() +#define cpu_l2cache_wbinv_all() #endif -static void armadaxp_idcache_wbinv_all(void); - int arm_picache_size; int arm_picache_line_size; int arm_picache_ways; @@ -354,18 +346,6 @@ arm9_setup(void) arm9_dcache_index_max = 0U - arm9_dcache_index_inc; } -static void -armadaxp_idcache_wbinv_all(void) -{ - uint32_t feat; - - __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (feat)); - if (feat & ARM_PFR0_THUMBEE_MASK) - armv7_idcache_wbinv_all(); - else - armv6_idcache_wbinv_all(); - -} #ifdef KZIP static unsigned char *orig_input, *i_input, *i_output; diff --git a/sys/conf/Makefile.arm b/sys/conf/Makefile.arm index 6270aef..7140249 100644 --- a/sys/conf/Makefile.arm +++ b/sys/conf/Makefile.arm @@ -51,6 +51,7 @@ SYSTEM_LD_TAIL +=;sed s/" + SIZEOF_HEADERS"// ldscript.$M\ ${SYSTEM_LD_}; \ ${OBJCOPY} -S -O binary ${FULLKERNEL}.noheader \ ${KERNEL_KO}.bin; \ + ${NM} ${FULLKERNEL}.noheader | sort > ${FULLKERNEL}.map; \ rm ${FULLKERNEL}.noheader .if defined(MFS_IMAGE) @@ -63,7 +64,7 @@ FILES_CPU_FUNC = $S/$M/$M/cpufunc_asm_arm7tdmi.S \ $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S \ $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S + $S/$M/$M/cpufunc_asm_armv6.S KERNEL_EXTRA=trampoline KERNEL_EXTRA_INSTALL=kernel.gz.tramp --------------040005010806010909090200 Content-Type: text/x-patch; name="4_tex_remap.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="4_tex_remap.diff" commit 6752aeb2f7a2c1ddc5e2ec515a280f550c0be2b3 Author: Lukasz Plachno Date: Wed Nov 21 11:46:30 2012 +0100 arm: Implement new way for pagetable memory attributes management - initialize PRRR and NMRR registers in cp15 - enable TEX remapping - create macros for TTB attributes diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c index dd43c27..2a3acb4 100644 --- a/sys/arm/arm/cpufunc.c +++ b/sys/arm/arm/cpufunc.c @@ -2327,6 +2327,7 @@ pj4bv6_setup(char *args) cpuctrl |= CPU_CONTROL_VECRELOC; cpuctrl |= (0x5 << 16); cpuctrl |= CPU_CONTROL_V6_EXTPAGE; + cpuctrl |= CPU_CONTROL_TEX_REMAP; /* XXX not yet */ /* cpuctrl |= CPU_CONTROL_L2_ENABLE; */ @@ -2362,6 +2363,7 @@ pj4bv7_setup(args) cpuctrl |= CPU_CONTROL_VECRELOC; cpuctrl |= (0x5 << 16) | (1 < 22); cpuctrl |= CPU_CONTROL_V6_EXTPAGE; + cpuctrl |= CPU_CONTROL_TEX_REMAP; /* Clear out the cache */ cpu_idcache_wbinv_all(); @@ -2392,7 +2394,8 @@ cortexa_setup(char *args) cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE | - CPU_CONTROL_BPRD_ENABLE; + CPU_CONTROL_BPRD_ENABLE | + CPU_CONTROL_TEX_REMAP; #ifndef ARM32_DISABLE_ALIGNMENT_FAULTS cpuctrl |= CPU_CONTROL_AFLT_ENABLE; diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S index 03561b8..d6f9d59 100644 --- a/sys/arm/arm/cpufunc_asm_armv7.S +++ b/sys/arm/arm/cpufunc_asm_armv7.S @@ -32,6 +32,8 @@ #include __FBSDID("$FreeBSD$"); +#include + .cpu cortex-a8 .Lcoherency_level: @@ -45,30 +47,13 @@ __FBSDID("$FreeBSD$"); .Lpage_mask: .word 0xfff -#define PT_NOS (1 << 5) -#define PT_S (1 << 1) -#define PT_INNER_NC 0 -#define PT_INNER_WT (1 << 0) -#define PT_INNER_WB ((1 << 0) | (1 << 6)) -#define PT_INNER_WBWA (1 << 6) -#define PT_OUTER_NC 0 -#define PT_OUTER_WT (2 << 3) -#define PT_OUTER_WB (3 << 3) -#define PT_OUTER_WBWA (1 << 3) - -#ifdef SMP -#define PT_ATTR (PT_S|PT_INNER_WT|PT_OUTER_WT|PT_NOS) -#else -#define PT_ATTR (PT_INNER_WT|PT_OUTER_WT) -#endif - ENTRY(armv7_setttb) stmdb sp!, {r0, lr} bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */ ldmia sp!, {r0, lr} dsb - orr r0, r0, #PT_ATTR + orr r0, r0, #TTB_ATTR mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */ #ifdef SMP mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */ @@ -258,7 +243,7 @@ ENTRY(armv7_cpu_sleep) ENTRY(armv7_context_switch) dsb - orr r0, r0, #PT_ATTR + orr r0, r0, #TTB_ATTR mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ #ifdef SMP diff --git a/sys/arm/arm/cpufunc_asm_pj4b.S b/sys/arm/arm/cpufunc_asm_pj4b.S index f6890d9..f2eba94 100644 --- a/sys/arm/arm/cpufunc_asm_pj4b.S +++ b/sys/arm/arm/cpufunc_asm_pj4b.S @@ -33,6 +33,7 @@ __FBSDID("$FreeBSD$"); #include +#include .Lpj4b_cache_line_size: .word _C_LABEL(arm_pdcache_line_size) @@ -40,9 +41,7 @@ __FBSDID("$FreeBSD$"); ENTRY(pj4b_setttb) /* Cache synchronization is not required as this core has PIPT caches */ mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */ -#ifdef SMP - orr r0, r0, #2 /* Set TTB shared memory flag */ -#endif + orr r0, r0, #TTB_ATTR /* Set TTB memory flags */ mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ RET @@ -199,4 +198,5 @@ ENTRY(pj4b_config) orr r0, r0, #(1 << 5) mcr p15, 0, r0, c1, c0, 1 #endif + RET diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S index d541f39..e382c00 100644 --- a/sys/arm/arm/locore.S +++ b/sys/arm/arm/locore.S @@ -38,6 +38,7 @@ #include #include #include +#include __FBSDID("$FreeBSD$"); @@ -162,8 +163,9 @@ Lunmapped: orrne r5, r5, #PHYSADDR movne pc, r5 -#if defined(SMP) - orr r0, r0, #2 /* Set TTB shared memory flag */ +#if ARM_MMU_V7 != 0 + /* For primary pagetable normal non-cacheable memory is used */ + orr r0, r0, #TTB_FLAGS_2 /* Set TTB memory flags */ #endif mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ #ifdef SMP @@ -172,6 +174,19 @@ Lunmapped: mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ #endif +#if ARM_MMU_V7 != 0 + /* Set PRRR and NMRR cp15 registers */ + ldr r0, =PRRR + mcr p15, 0, r0, c10, c2, 0 + ldr r0, =NMRR + mcr p15, 0, r0, c10, c2, 1 + + /* Set TEX Remap */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, #CPU_CONTROL_TEX_REMAP + mcr p15, 0, r0, c1, c0, 0 +#endif + #if (ARM_ARCH_6 + ARM_ARCH_7A) != 0 mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ @@ -361,8 +376,10 @@ Ltag: bic r0, r0, #0xf0000000 orr r0, r0, #PHYSADDR ldr r0, [r0] -#if defined(SMP) - orr r0, r0, #0 /* Set TTB shared memory flag */ + +#if ARM_MMU_V7 != 0 + /* For primary pagetable normal non-cacheable memory is used */ + orr r0, r0, #TTB_FLAGS_2 /* Set TTB memory flags */ #endif mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ #ifdef SMP @@ -371,6 +388,19 @@ Ltag: mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ #endif +#if ARM_MMU_V7 != 0 + /* Set PRRR and NMRR cp15 registers */ + ldr r0, =PRRR + mcr p15, 0, r0, c10, c2, 0 + ldr r0, =NMRR + mcr p15, 0, r0, c10, c2, 1 + + /* Set TEX Remap */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, #CPU_CONTROL_TEX_REMAP + mcr p15, 0, r0, c1, c0, 0 +#endif + #if (ARM_ARCH_6 + ARM_ARCH_7A) != 0 mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ diff --git a/sys/arm/arm/pmap-v6.c b/sys/arm/arm/pmap-v6.c index a44bdbf..aafb1e4 100644 --- a/sys/arm/arm/pmap-v6.c +++ b/sys/arm/arm/pmap-v6.c @@ -386,6 +386,48 @@ static struct vm_object pvzone_obj; static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0; static struct rwlock pvh_global_lock; +#if defined(SMP) +#define L1_SHAREABLE L1_SHARED +#define L2_SHAREABLE L2_SHARED +#else +#define L1_SHAREABLE 0 +#define L2_SHAREABLE 0 +#endif /* SMP */ + +#if ARM_MMU_V7 != 0 +int l1_mem_types[] = { + (L1_SHAREABLE), + (L1_SHAREABLE | L1_S_B), + (L1_SHAREABLE | L1_S_C), + (L1_SHAREABLE | L1_S_C | L1_S_B), + (L1_SHAREABLE | L1_S_TEX(1)), + (L1_SHAREABLE | L1_S_TEX(1) | L1_S_B), + (L1_SHAREABLE), + (L1_SHAREABLE | L1_S_TEX(1) | L1_S_C | L1_S_B) +}; + +int l2l_mem_types[] = { + (L2_SHAREABLE), + (L2_SHAREABLE | L2_B), + (L2_SHAREABLE | L2_C), + (L2_SHAREABLE | L2_C | L2_B), + (L2_SHAREABLE | L2_L_TEX(1)), + (L2_SHAREABLE | L2_L_TEX(1) | L2_B), + (L2_SHAREABLE), + (L2_SHAREABLE | L2_L_TEX(1) | L2_C | L2_B) +}; + +int l2s_mem_types[] = { + (L2_SHAREABLE), + (L2_SHAREABLE | L2_B), + (L2_SHAREABLE | L2_C), + (L2_SHAREABLE | L2_C | L2_B), + (L2_SHAREABLE | L2_S_TEX(1)), + (L2_SHAREABLE | L2_S_TEX(1) | L2_B), + (L2_SHAREABLE), + (L2_SHAREABLE | L2_S_TEX(1) | L2_C | L2_B) +}; +#else int l1_mem_types[] = { ARM_L1S_STRONG_ORD, ARM_L1S_DEVICE_NOSHARE, @@ -415,6 +457,7 @@ int l2s_mem_types[] = { ARM_L2S_NRML_IWB_OWB, ARM_L2S_NRML_IWBA_OWBA }; +#endif /* * This list exists for the benefit of pmap_map_chunk(). It keeps track diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h index 05b3846..f5ccfb9 100644 --- a/sys/arm/include/armreg.h +++ b/sys/arm/include/armreg.h @@ -286,6 +286,7 @@ #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ #define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ #define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ +#define CPU_CONTROL_TEX_REMAP 0x10000000 /* TEX Remap enabled */ #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE diff --git a/sys/arm/include/pmap.h b/sys/arm/include/pmap.h index e20bf18..c3ffe2c 100644 --- a/sys/arm/include/pmap.h +++ b/sys/arm/include/pmap.h @@ -52,33 +52,140 @@ #include #include + +/* + * When TEX remap is enabled (SCTLR.TRE is set to 1), + * PRRR and NMRR values needs to be initialized before MMU is used. + * + * TEX[0],C,B -> index(n) + * + * PMRR -> memory type (strongly ordered, device, normal), shareability + * TR (PRRR[2n+1:2n]) -> memory type + * NOS (PRMRR[24+n]) -> non outer shareable attribute + * DS0 (PRRR[16]) -> device memory shareable attribute (S = 0) + * DS1 (PRRR[17]) -> device memory shareable attribute (S = 1) + * NS0 (PRRR[18]) -> normal memory shareable attribute (S = 0) + * NS1 (PRRR[19]) -> normal memory shareable attribute (S = 1) + * + * NMRR -> cache policy (no cache, WT, WB, WBWA) + * IR (NMRR[2n+1;2n]) -> inner cache property + * OR (NMRR[2n+17;2n+16]) -> outer cache property + * + * Memory type index TR IR OR + * STRONGLY_ORDERED 0 00 + * DEVICE 1 01 + * NOCACHE 2 10 00 00 + * IWT_OWT 3 10 10 10 + * IWB_OWB 4 10 11 11 + * IWBA_OWBA 5 10 01 01 + * RESERVED 6 + * IWBA_OWB 7 10 01 11 + * + * Other attributes: + * DS0 = 0 + * DS1 = 1 + * NS0 = 0 + * NS1 = 1 + * + * Outer shareability is implementation dependent feature in armv7 + * specification, for now safe value (disable outer shareability) is used + * NOS[0:7] = 1 + */ + +#define PRRR 0xff0a8aa4 +#define NMRR 0xc7804780 + +/* + * ARMv7 TTBR bit definition + */ +#if ARM_MMU_V7 != 0 +#define PT_NOS (1 << 5) +#define PT_S (1 << 1) +#define PT_OUTER_NC 0 +#define PT_OUTER_WT (2 << 3) +#define PT_OUTER_WB (3 << 3) +#define PT_OUTER_WBWA (1 << 3) +#if defined(SMP) +#define PT_SHAREABLE (PT_S) +#define PT_INNER_NC 0 +#define PT_INNER_WT (1 << 0) +#define PT_INNER_WB ((1 << 0) | (1 << 6)) +#define PT_INNER_WBWA (1 << 6) +#else +#define PT_SHAREABLE 0 + +/* + * In ARMv6 and ARMV7 without multiprocessor extension, + * pagetable memory inner cacheability policy is implementation defined + */ +#define PT_INNER_NC 0 +#define PT_INNER_WT (1 << 0) +#define PT_INNER_WB (1 << 0) +#define PT_INNER_WBWA (1 << 0) +#endif /* SMP */ + +#define TTB_FLAGS_0 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC) +#define TTB_FLAGS_1 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC) +#define TTB_FLAGS_2 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC) +#define TTB_FLAGS_3 (PT_SHAREABLE | PT_NOS | PT_INNER_WT | PT_OUTER_WT) +#define TTB_FLAGS_4 (PT_SHAREABLE | PT_NOS | PT_INNER_WB | PT_OUTER_WB) +#define TTB_FLAGS_5 (PT_SHAREABLE | PT_NOS | PT_INNER_WBWA | PT_OUTER_WBWA) +#define TTB_FLAGS_6 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC) +#define TTB_FLAGS_7 (PT_SHAREABLE | PT_NOS | PT_INNER_WBWA | PT_OUTER_WB) +#endif /* (ARM_MMU_V7) != 0 */ + /* - * Pte related macros + * Pte related macros + * + * Memory types when tex remap is enabled (armv6 and armv7): + * 0 - strongly ordered + * 1 - device memory, + * 2 - normal memory, non cacheable + * 3 - normal memory, inner write-through, outer write-through + * 4 - normal memory, inner write-back, outer write-back + * 5 - normal memory, inner write-back write-allocate, + * outer write-back write-allocate + * 6 - reserved value + * 7 - normal memory, inner write-back write-allocate, outer write-back + * + * Memory types when tex remap is disabled / not supported: + * 0 - strongly ordered + * 1 - device memory, non shareable + * 2 - device memory, shareable + * 3 - normal memory, non cacheable + * 4 - normal memory, inner write-through, outer write-through + * 5 - normal memory, inner write-back, outer write-back + * 6 - normal memory, inner write-back write-allocate, + * outer write-back write-allocate */ -#if ARM_ARCH_6 || ARM_ARCH_7A + +#if ARM_MMU_V7 != 0 +#define PTE_NOCACHE 2 +#define PTE_CACHE 5 +#define PTE_DEVICE 1 + +/* TTB_FLAGS number must be the same as PTE_PAGETABLE value */ +#define PTE_PAGETABLE 5 +#define TTB_ATTR TTB_FLAGS_5 +#elif ARM_MMU_V6 != 0 #ifdef SMP #define PTE_NOCACHE 2 #else #define PTE_NOCACHE 1 -#endif +#endif /* SMP */ #define PTE_CACHE 4 #define PTE_DEVICE 2 #define PTE_PAGETABLE 4 -#else + +#define TTB_ATTR 0 +#else /* ARM_MMU_V6 == 0 && ARM_MMU_V7 == 0 */ #define PTE_NOCACHE 1 #define PTE_CACHE 2 #define PTE_PAGETABLE 3 + +#define TTB_ATTR 0 #endif -enum mem_type { - STRONG_ORD = 0, - DEVICE_NOSHARE, - DEVICE_SHARE, - NRML_NOCACHE, - NRML_IWT_OWT, - NRML_IWB_OWB, - NRML_IWBA_OWBA -}; #ifndef LOCORE @@ -427,6 +534,8 @@ extern int pmap_needs_pte_sync; #elif defined(CPU_XSCALE_81342) #define PMAP_NEEDS_PTE_SYNC 1 #define PMAP_INCLUDE_PTE_SYNC +#elif ARM_MMU_V7 != 0 +#define PMAP_NEEDS_PTE_SYNC 1 #elif (ARM_MMU_SA1 == 0) #define PMAP_NEEDS_PTE_SYNC 0 #endif --------------040005010806010909090200 Content-Type: text/x-patch; name="5_memory_barriers.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="5_memory_barriers.diff" commit 0e88c1b42d405480fbac4ee1b6758a8e5648932a Author: Lukasz Plachno Date: Tue Nov 20 09:21:03 2012 +0100 arm: Add macros for memory barriers - In armv6 "dsb" operation is not supported - In armv7 use of register r7 in cp15 is deprecated diff --git a/sys/arm/include/atomic.h b/sys/arm/include/atomic.h index 1a96176..2050b55 100644 --- a/sys/arm/include/atomic.h +++ b/sys/arm/include/atomic.h @@ -47,9 +47,35 @@ #include #endif -#define mb() -#define wmb() -#define rmb() +#if ARM_ARCH_7A != 0 +#define mb() do { \ + __asm __volatile("dsb"); \ + } while (0) +#define wmb() do { \ + __asm __volatile("dsb"); \ + } while (0) +#define rmb() do { \ + __asm __volatile("dsb"); \ + } while (0) +#elif ARM_ARCH_6 != 0 +#define mb() do { \ + uint32_t reg = 0; \ + __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (reg)); \ + } while (0) +#define wmb() do { \ + uint32_t reg = 0; \ + __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (reg)); \ + } while (0) +#define rmb() do { \ + uint32_t reg = 0; \ + __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (reg)); \ + } while (0) +#else +#define mb() +#define wmb() +#define rmb() +#endif + #ifndef I32_bit #define I32_bit (1 << 7) /* IRQ disable */ --------------040005010806010909090200-- From owner-freebsd-arm@FreeBSD.ORG Wed Nov 21 16:00:03 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 4A3CA7B; Wed, 21 Nov 2012 16:00:03 +0000 (UTC) (envelope-from giovanni.trematerra@gmail.com) Received: from mail-qc0-f182.google.com (mail-qc0-f182.google.com [209.85.216.182]) by mx1.freebsd.org (Postfix) with ESMTP id E16D78FC14; Wed, 21 Nov 2012 16:00:02 +0000 (UTC) Received: by mail-qc0-f182.google.com with SMTP id k19so6270280qcs.13 for ; Wed, 21 Nov 2012 08:00:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=pKTvd6kgakN3WuEDuztAtrd1YZzqM9ERqrzRVZDymh0=; b=TBvQe+VhUCQUlTUrPNX+mzJZcA7eipNXR0frkN5e9kqher0xD5uhozAiH6fZp114nT tvF50NKxC/rvxvXqi7GIiO71yuzSJ+Ezl+M5zRKuhHGs3J2qDzCnalpIZRwGTy6xQsQQ ySZLDyZBfWIeVB4/73KPDZIPSiRkUPn0wttcIYYwBa7eUvEq36owe2k1VrFZCKCeS5bQ ksG4dXFTk72yaadD+efrncody7TpAENem3KOT0zQDOgQImu/oyrQJN067PJLyUVtsjV+ v9TfvDvUtBZWMXacsyYGF2dABvhLw3Uflvi7hv7w0UNQngk1GhHilvndWr4CcJ6pzbQo oVGQ== MIME-Version: 1.0 Received: by 10.224.185.79 with SMTP id cn15mr18621534qab.14.1353513602024; Wed, 21 Nov 2012 08:00:02 -0800 (PST) Sender: giovanni.trematerra@gmail.com Received: by 10.229.117.1 with HTTP; Wed, 21 Nov 2012 08:00:01 -0800 (PST) In-Reply-To: <50ACE2B4.8010904@semihalf.com> References: <50AA4E87.3000505@semihalf.com> <50ACE2B4.8010904@semihalf.com> Date: Wed, 21 Nov 2012 17:00:01 +0100 X-Google-Sender-Auth: AmnGVRxrMDbLkMK_PtAPFMPNj40 Message-ID: Subject: Re: ARM/SMP, Some patches for review. From: Giovanni Trematerra To: =?UTF-8?B?xYF1a2FzeiBQxYJhY2hubw==?= Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Cc: freebsd-arm@freebsd.org, cognet@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Nov 2012 16:00:03 -0000 On Wed, Nov 21, 2012 at 3:18 PM, =C5=81ukasz P=C5=82achno wrote: > On 20.11.2012 00:08, Giovanni Trematerra wrote: >> >> On Mon, Nov 19, 2012 at 4:21 PM, =C5=81ukasz P=C5=82achno wrote: >>> >>> Hi, >>> >>> I would like to propose few changes for ARM specific code. >>> Three attached patches for freebsd-current allows building SMP-safe wor= ld >>> for ARM targets and turns on TEX remap for ARMv6 and ARMv7 targets. >>> >>> More details inside patch files. >>> >>> Change introduced by "commit-2" removes armv7 targets (armv7 and pj4b) >>> from >>> kernel.tramp. >>> AFAIK this feature is not working properly for armv7 targets and is >>> causing >>> problem during compilation: >>> - LOCORE is defined during kernel compilation but not defined during >>> kernel.tramp compilation, so #include pmap.h causes build errors. >>> >>> I do not think adding hack like this: >>> #ifndef LOCORE >>> #define LOCORE >>> #endif >>> >>> to allow building something that is already broken is a good idea, so I >>> removed cpufunc_asm_pj4b.S and cpufunc_asm_armv7.S from Makefile.arm >> >> >> In commit-2.txt >> you should include style changes in sys/arm/arm/cpufunc_asm_armv7.S >> into a different patch. > > > fixed > > >> >> @@ -63,7 +64,6 @@ FILES_CPU_FUNC =3D $S/$M/$M/cpufunc_asm_arm7tdmi.= S \ >> $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ >> $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.= S >> \ >> $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ >> - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S >> >> You left a trailing back slash but beside that you should clean up >> sys/arm/arm/elf_trampoline.c >> and not make kernel.tramp to build at all for armv7 cpus or you'll end >> up with a linker error >> during generation of the kernel.tramp. >> > > Fixed, updated set of patches is attached. > > - TEX remap is supported only for armv6 (changed to avoid breaking armv6 > targets) > - Fixed issues with build for pre-armv6 targets (tested with make tinder= box > TARGETS=3Darm > 1_SMP_fixes.diff You'll endup to get a panic for PandaBoard systems. The arm11 functions don't handle the SMP case. So I propose to merge the changes below or commit them first. Index: sys/arm/arm/cpufunc.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- sys/arm/arm/cpufunc.c (revision 243182) +++ sys/arm/arm/cpufunc.c (working copy) @@ -1079,18 +1079,18 @@ struct cpu_functions cortexa_cpufuncs =3D { /* Other functions */ cpufunc_nullop, /* flush_prefetchbuf */ - arm11_drain_writebuf, /* drain_writebuf */ + armv7_drain_writebuf, /* drain_writebuf */ cpufunc_nullop, /* flush_brnchtgt_C */ (void *)cpufunc_nullop, /* flush_brnchtgt_E */ - arm11_sleep, /* sleep */ + armv7_cpu_sleep, /* sleep */ /* Soft functions */ cpufunc_null_fixup, /* dataabt_fixup */ cpufunc_null_fixup, /* prefetchabt_fixup */ - arm11_context_switch, /* context_switch */ + armv7_context_switch, /* context_switch */ cortexa_setup /* cpu setup */ }; 2_ARM_cleanup.diff Changes to sys/arm/arm/machdep.c don't seem style changes and they should live in a separate patch with a different motivation. I'm not sure changes in sys/arm/arm/locore.S are style ones. I think that things like this aren't so readable. #if (ARM_ARCH_6 + ARM_ARCH_7A) !=3D 0 Instead of things like that wouldn't be better to define different macros when the sum is zero or non zero and stick with the #if defined/!defined thing? I mean in sys/arm/arm/cpuconf.h we could make something like this #if (ARM_ARCH_6 + ARM_ARCH_7A) !=3D 0 #define ARM_ARCH_6_7A #endif 3_kernel_trampoline.diff I think we should not make kernel_trampoline at all for the unsupported CPU= s. I propose this change to Makefile.arm Index: sys/conf/Makefile.arm =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- sys/conf/Makefile.arm (revision 243182) +++ sys/conf/Makefile.arm (working copy) @@ -51,6 +51,7 @@ SYSTEM_LD_TAIL +=3D;sed s/" + SIZEOF_HEADERS"// ldsc ${SYSTEM_LD_}; \ ${OBJCOPY} -S -O binary ${FULLKERNEL}.noheader \ ${KERNEL_KO}.bin; \ + ${NM} ${FULLKERNEL}.noheader | sort > ${FULLKERNEL}.map; \ rm ${FULLKERNEL}.noheader .if defined(MFS_IMAGE) @@ -62,9 +63,11 @@ FILES_CPU_FUNC =3D $S/$M/$M/cpufunc_asm_arm7tdmi.S \ $S/$M/$M/cpufunc_asm_sa1.S $S/$M/$M/cpufunc_asm_arm10.S \ $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S \ $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S + $S/$M/$M/cpufunc_asm_armv6.S +NO_TRAMP!=3D grep 'CPU_CORTEXA\|CPU_MV_PJ4B' opt_global.h || true ; echo + +.if ${NO_TRAMP} =3D=3D "" KERNEL_EXTRA=3Dtrampoline KERNEL_EXTRA_INSTALL=3Dkernel.gz.tramp trampoline: ${KERNEL_KO}.tramp @@ -110,6 +113,7 @@ ${KERNEL_KO}.tramp: ${KERNEL_KO} $S/$M/$M/inckern. ${KERNEL_KO}.gz.tramp.bin rm ${KERNEL_KO}.tmp.gz ${KERNEL_KO}.tramp.noheader opt_kernname.h \ inflate-tramp.o tmphack.S +.endif MKMODULESENV+=3D MACHINE=3D${MACHINE} 4_tex-remap.diff Some style(9) consideration. #include(s) should be grouped together in alphabetical order. So you should fix the pmap.h includes that you made. I'll try to test the pachset ASAP. -- Gianni From owner-freebsd-arm@FreeBSD.ORG Wed Nov 21 18:18:42 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 80CC0E3C; Wed, 21 Nov 2012 18:18:42 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-wi0-f174.google.com (mail-wi0-f174.google.com [209.85.212.174]) by mx1.freebsd.org (Postfix) with ESMTP id A98858FC13; Wed, 21 Nov 2012 18:18:41 +0000 (UTC) Received: by mail-wi0-f174.google.com with SMTP id hm9so76776wib.13 for ; Wed, 21 Nov 2012 10:18:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=HYcsY5EWNZk2+K/bsxxLLB22sXXYG8NYNnGRK3SBflU=; b=Y8x/9zpObYPgkLdHP1uZ3mBmcvktLv6BB42XX1A2KYAMasvDBe6k7oiAFrqKa9MwcC kkd1hUr9aTUTO7K04mJkHhzLS4o8iNW63jygCd21Gntu66x1r00hCqObqZsHlObt+GX2 jJ2WrERERhJX1oI9A+WQw9AxaAEOiqpwuhwx4BEhmc9TlqaCRJEFO5+KoEArGccAiJtk 8WO7C6u2PqQw404A0nCGbttU6dEAcjJmpP7+d9ynycsH8jX+hZfGOpdEaZOTpwrse2Jg Xq35Bpp/5MoxXBhtR+QeEpjzd7/aVPUC/LXwASh6+V5ebUWQnP6XY1M2dPTq74LPB1kr ehKw== MIME-Version: 1.0 Received: by 10.180.103.106 with SMTP id fv10mr273890wib.19.1353521474311; Wed, 21 Nov 2012 10:11:14 -0800 (PST) Sender: adrian.chadd@gmail.com Received: by 10.216.21.211 with HTTP; Wed, 21 Nov 2012 10:11:13 -0800 (PST) In-Reply-To: References: <50AA4E87.3000505@semihalf.com> <50ACE2B4.8010904@semihalf.com> Date: Wed, 21 Nov 2012 10:11:13 -0800 X-Google-Sender-Auth: YXRFEXSZKAPZHbFR2br31VbeZJI Message-ID: Subject: Re: ARM/SMP, Some patches for review. From: Adrian Chadd To: Giovanni Trematerra Content-Type: text/plain; charset=ISO-8859-1 Cc: freebsd-arm@freebsd.org, cognet@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Nov 2012 18:18:42 -0000 Why can't you just #if ARM_a || ARM_b #define ARM_a_b #endif ? Adrian From owner-freebsd-arm@FreeBSD.ORG Wed Nov 21 18:44:05 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 81936A6C for ; Wed, 21 Nov 2012 18:44:05 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from mail-ie0-f182.google.com (mail-ie0-f182.google.com [209.85.223.182]) by mx1.freebsd.org (Postfix) with ESMTP id 2C4BC8FC12 for ; Wed, 21 Nov 2012 18:44:04 +0000 (UTC) Received: by mail-ie0-f182.google.com with SMTP id s9so5397423iec.13 for ; Wed, 21 Nov 2012 10:44:04 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:subject:mime-version:content-type:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to:x-mailer :x-gm-message-state; bh=fhcvz67zV2vWZXzR7VJ+9x72g0L1/cBFylchQlbtWlU=; b=HD1AQjf9bOdXa1gCrk9/W8QW15DJi+HcVx9LJl04mgcp8e/q0d2HZKC6y2h09zycEZ 8jcabv+ILoUk5O5B3w1X2oq6bxGNxWG4nbKqal3Xlwr27zu6ouScJr0TZsDS8+dpW7MK 5jJELlFdscFz13RQXuSr6sk9f9wd6VDvmb08L2QYrkkq8i8sAcDqB2tuEuChppA1qHaW 3QOwnqd1Lvmq0RIx994ecrS6+QmdeOVL9nAcJK/VUt9aUlsshbD+6r0qtaXkUt23Dhtc 4v39ETs0p87Kj5JmzZKKFDzH5pW9gRDPDiTTTq7Kab61MKPcq/mvUMhxCXpRpyBnkKQc ss2Q== Received: by 10.50.140.38 with SMTP id rd6mr509549igb.35.1353523444583; Wed, 21 Nov 2012 10:44:04 -0800 (PST) Received: from 53.imp.bsdimp.com (50-78-194-198-static.hfc.comcastbusiness.net. [50.78.194.198]) by mx.google.com with ESMTPS id s3sm279840igb.14.2012.11.21.10.44.01 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 21 Nov 2012 10:44:03 -0800 (PST) Sender: Warner Losh Subject: Re: ARM/SMP, Some patches for review. Mime-Version: 1.0 (Apple Message framework v1085) Content-Type: text/plain; charset=us-ascii From: Warner Losh In-Reply-To: Date: Wed, 21 Nov 2012 11:44:00 -0700 Content-Transfer-Encoding: quoted-printable Message-Id: References: <50AA4E87.3000505@semihalf.com> <50ACE2B4.8010904@semihalf.com> To: Adrian Chadd X-Mailer: Apple Mail (2.1085) X-Gm-Message-State: ALoCoQm72fVtLGnmQKDKqcab/iY3RBSBT7tLN4WfCGLnovsb1e7ReqZ/jm8cza0+kLBNbkmgWjXO Cc: freebsd-arm@freebsd.org, cognet@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Nov 2012 18:44:05 -0000 Too bad it isn't a strict ordering, because then you could assign = numbers to the sequence and use >=3D. armv8 kinda puts a kink into = that, from what I've heard so far... Warner On Nov 21, 2012, at 11:11 AM, Adrian Chadd wrote: > Why can't you just >=20 > #if ARM_a || ARM_b > #define ARM_a_b > #endif >=20 > ? >=20 >=20 >=20 > Adrian > _______________________________________________ > freebsd-arm@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-arm > To unsubscribe, send any mail to "freebsd-arm-unsubscribe@freebsd.org" From owner-freebsd-arm@FreeBSD.ORG Thu Nov 22 10:39:33 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 18B55FDE; Thu, 22 Nov 2012 10:39:33 +0000 (UTC) (envelope-from andrew@fubar.geek.nz) Received: from smtp4.clear.net.nz (smtp4.clear.net.nz [203.97.37.64]) by mx1.freebsd.org (Postfix) with ESMTP id CD89C8FC08; Thu, 22 Nov 2012 10:39:32 +0000 (UTC) Received: from mxin2-orange.clear.net.nz (lb2-srcnat.clear.net.nz [203.97.32.237]) by smtp4.clear.net.nz (CLEAR Net Mail) with ESMTP id <0MDV007CLXLPPM50@smtp4.clear.net.nz>; Thu, 22 Nov 2012 23:39:25 +1300 (NZDT) Received: from 202-0-48-19.paradise.net.nz (HELO localhost) ([202.0.48.19]) by smtpin2.paradise.net.nz with ESMTP; Thu, 22 Nov 2012 23:39:25 +1300 Date: Thu, 22 Nov 2012 23:39:09 +1300 From: Andrew Turner Subject: Re: ARM/SMP, Some patches for review. In-reply-to: To: Warner Losh Message-id: <20121122233909.66c7f479@fubar.geek.nz> MIME-version: 1.0 X-Mailer: Claws Mail 3.8.0 (GTK+ 2.24.6; i386-portbld-freebsd8.1) Content-type: text/plain; charset=US-ASCII Content-transfer-encoding: 7bit X-Pirate: Arrrr References: <50AA4E87.3000505@semihalf.com> <50ACE2B4.8010904@semihalf.com> Cc: freebsd-arm@freebsd.org, cognet@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 22 Nov 2012 10:39:33 -0000 On Wed, 21 Nov 2012 11:44:00 -0700 Warner Losh wrote: > Too bad it isn't a strict ordering, because then you could assign > numbers to the sequence and use >=. armv8 kinda puts a kink into > that, from what I've heard so far... It won't work for the 64-bit stuff but my understanding is the 32-bit side of ARMv8 is similar enough to ARMv7 that a sequence would work. It will need to be decided how we handle AArch64 (arm64) as some parts are different, e.g. the instruction set and assembly is incompatible, while other parts are shared, e.g. the page table layout are similar to the long format in Cortex-A. Andrew From owner-freebsd-arm@FreeBSD.ORG Thu Nov 22 14:52:14 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 0458ED28; Thu, 22 Nov 2012 14:52:14 +0000 (UTC) (envelope-from luk@semihalf.com) Received: from smtp.semihalf.com (smtp.semihalf.com [213.17.239.109]) by mx1.freebsd.org (Postfix) with ESMTP id 85A708FC13; Thu, 22 Nov 2012 14:52:11 +0000 (UTC) Received: from localhost (unknown [213.17.239.109]) by smtp.semihalf.com (Postfix) with ESMTP id 5AD7CC401C; Thu, 22 Nov 2012 15:52:04 +0100 (CET) X-Virus-Scanned: by amavisd-new at semihalf.com Received: from smtp.semihalf.com ([213.17.239.109]) by localhost (smtp.semihalf.com [213.17.239.109]) (amavisd-new, port 10024) with ESMTP id fwkMK87phWSY; Thu, 22 Nov 2012 15:52:00 +0100 (CET) Received: from [10.0.2.115] (cardhu.semihalf.com [213.17.239.108]) by smtp.semihalf.com (Postfix) with ESMTPSA id 632F7C384A; Thu, 22 Nov 2012 15:52:00 +0100 (CET) Message-ID: <50AE3C0F.20809@semihalf.com> Date: Thu, 22 Nov 2012 15:51:59 +0100 From: =?UTF-8?B?xYF1a2FzeiBQxYJhY2hubw==?= User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:16.0) Gecko/20121028 Thunderbird/16.0.2 MIME-Version: 1.0 To: Giovanni Trematerra Subject: Re: ARM/SMP, Some patches for review. References: <50AA4E87.3000505@semihalf.com> <50ACE2B4.8010904@semihalf.com> In-Reply-To: Content-Type: multipart/mixed; boundary="------------090609080402090500000504" Cc: freebsd-arm@freebsd.org, cognet@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 22 Nov 2012 14:52:14 -0000 This is a multi-part message in MIME format. --------------090609080402090500000504 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 21.11.2012 17:00, Giovanni Trematerra wrote: > On Wed, Nov 21, 2012 at 3:18 PM, Łukasz Płachno wrote: >> On 20.11.2012 00:08, Giovanni Trematerra wrote: >>> >>> On Mon, Nov 19, 2012 at 4:21 PM, Łukasz Płachno wrote: >>>> >>>> Hi, >>>> >>>> I would like to propose few changes for ARM specific code. >>>> Three attached patches for freebsd-current allows building SMP-safe world >>>> for ARM targets and turns on TEX remap for ARMv6 and ARMv7 targets. >>>> >>>> More details inside patch files. >>>> >>>> Change introduced by "commit-2" removes armv7 targets (armv7 and pj4b) >>>> from >>>> kernel.tramp. >>>> AFAIK this feature is not working properly for armv7 targets and is >>>> causing >>>> problem during compilation: >>>> - LOCORE is defined during kernel compilation but not defined during >>>> kernel.tramp compilation, so #include pmap.h causes build errors. >>>> >>>> I do not think adding hack like this: >>>> #ifndef LOCORE >>>> #define LOCORE >>>> #endif >>>> >>>> to allow building something that is already broken is a good idea, so I >>>> removed cpufunc_asm_pj4b.S and cpufunc_asm_armv7.S from Makefile.arm >>> >>> >>> In commit-2.txt >>> you should include style changes in sys/arm/arm/cpufunc_asm_armv7.S >>> into a different patch. >> >> >> fixed >> >> >>> >>> @@ -63,7 +64,6 @@ FILES_CPU_FUNC = $S/$M/$M/cpufunc_asm_arm7tdmi.S \ >>> $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ >>> $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S >>> \ >>> $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ >>> - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S >>> >>> You left a trailing back slash but beside that you should clean up >>> sys/arm/arm/elf_trampoline.c >>> and not make kernel.tramp to build at all for armv7 cpus or you'll end >>> up with a linker error >>> during generation of the kernel.tramp. >>> >> >> Fixed, updated set of patches is attached. >> >> - TEX remap is supported only for armv6 (changed to avoid breaking armv6 >> targets) >> - Fixed issues with build for pre-armv6 targets (tested with make tinderbox >> TARGETS=arm >> > > 1_SMP_fixes.diff > You'll endup to get a panic for PandaBoard systems. > The arm11 functions don't handle the SMP case. > So I propose to merge the changes below or commit them first. > > Index: sys/arm/arm/cpufunc.c > =================================================================== > --- sys/arm/arm/cpufunc.c (revision 243182) > +++ sys/arm/arm/cpufunc.c (working copy) > @@ -1079,18 +1079,18 @@ struct cpu_functions cortexa_cpufuncs = { > /* Other functions */ > > cpufunc_nullop, /* flush_prefetchbuf */ > - arm11_drain_writebuf, /* drain_writebuf */ > + armv7_drain_writebuf, /* drain_writebuf */ > cpufunc_nullop, /* flush_brnchtgt_C */ > (void *)cpufunc_nullop, /* flush_brnchtgt_E */ > > - arm11_sleep, /* sleep */ > + armv7_cpu_sleep, /* sleep */ > > /* Soft functions */ > > cpufunc_null_fixup, /* dataabt_fixup */ > cpufunc_null_fixup, /* prefetchabt_fixup */ > > - arm11_context_switch, /* context_switch */ > + armv7_context_switch, /* context_switch */ > > cortexa_setup /* cpu setup */ > }; > I agree, but with this change I included also: diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c index dd43c27..1d6f93f 100644 --- a/sys/arm/arm/cpufunc.c +++ b/sys/arm/arm/cpufunc.c @@ -1049,14 +1049,14 @@ struct cpu_functions cortexa_cpufuncs = { armv7_tlb_flushID, /* tlb_flushID */ armv7_tlb_flushID_SE, /* tlb_flushID_SE */ - arm11_tlb_flushI, /* tlb_flushI */ - arm11_tlb_flushI_SE, /* tlb_flushI_SE */ - arm11_tlb_flushD, /* tlb_flushD */ - arm11_tlb_flushD_SE, /* tlb_flushD_SE */ + armv7_tlb_flushID, /* tlb_flushI */ + armv7_tlb_flushID_SE, /* tlb_flushI_SE */ + armv7_tlb_flushID, /* tlb_flushD */ + armv7_tlb_flushID_SE, /* tlb_flushD_SE */ Changes merged into patch 1_SMP_fixes.diff > > 2_ARM_cleanup.diff > Changes to sys/arm/arm/machdep.c don't seem style changes and > they should live in a separate patch with a different motivation. > > I'm not sure changes in sys/arm/arm/locore.S are style ones. None of changes in this patch are related to style. In this patch I wanted to improve code readability, not remove style conflicts. > > I think that things like this aren't so readable. > #if (ARM_ARCH_6 + ARM_ARCH_7A) != 0 > > Instead of things like that wouldn't be better to define different > macros when the sum is zero or non zero and stick with the > #if defined/!defined thing? > > I mean in sys/arm/arm/cpuconf.h we could make something like this > > #if (ARM_ARCH_6 + ARM_ARCH_7A) != 0 > #define ARM_ARCH_6_7A > #endif Changed to ARM_ARCH_6_7A > > 3_kernel_trampoline.diff > I think we should not make kernel_trampoline at all for the unsupported CPUs. > I propose this change to Makefile.arm > > Index: sys/conf/Makefile.arm > =================================================================== > --- sys/conf/Makefile.arm (revision 243182) > +++ sys/conf/Makefile.arm (working copy) > @@ -51,6 +51,7 @@ SYSTEM_LD_TAIL +=;sed s/" + SIZEOF_HEADERS"// ldsc > ${SYSTEM_LD_}; \ > ${OBJCOPY} -S -O binary ${FULLKERNEL}.noheader \ > ${KERNEL_KO}.bin; \ > + ${NM} ${FULLKERNEL}.noheader | sort > ${FULLKERNEL}.map; \ > rm ${FULLKERNEL}.noheader > > .if defined(MFS_IMAGE) > @@ -62,9 +63,11 @@ FILES_CPU_FUNC = $S/$M/$M/cpufunc_asm_arm7tdmi.S \ > $S/$M/$M/cpufunc_asm_sa1.S $S/$M/$M/cpufunc_asm_arm10.S \ > $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ > $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S \ > $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ > - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S > + $S/$M/$M/cpufunc_asm_armv6.S > > +NO_TRAMP!= grep 'CPU_CORTEXA\|CPU_MV_PJ4B' opt_global.h || true ; echo > + > +.if ${NO_TRAMP} == "" > KERNEL_EXTRA=trampoline > KERNEL_EXTRA_INSTALL=kernel.gz.tramp > trampoline: ${KERNEL_KO}.tramp > @@ -110,6 +113,7 @@ ${KERNEL_KO}.tramp: ${KERNEL_KO} $S/$M/$M/inckern. > ${KERNEL_KO}.gz.tramp.bin > rm ${KERNEL_KO}.tmp.gz ${KERNEL_KO}.tramp.noheader opt_kernname.h \ > inflate-tramp.o tmphack.S > +.endif > > MKMODULESENV+= MACHINE=${MACHINE} > Change merged into commit 3. > 4_tex-remap.diff > Some style(9) consideration. > #include(s) should be grouped together in alphabetical order. > So you should fix the pmap.h includes that you made. > #defines reordered > I'll try to test the pachset ASAP. > New set of patches attached. Regards, Łukasz Płachno --------------090609080402090500000504 Content-Type: text/x-patch; name="1_SMP_fixes.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="1_SMP_fixes.diff" commit f54fe0a3d5dd5577eb811a6f3aaef8fdf0d638e9 Author: Lukasz Plachno Date: Thu Nov 22 15:04:32 2012 +0100 arm/smp: Various fixes for enabling SMP operation on ARM systems - Currently libc is built with ARM SMP support only if specified architecture is one of the following: - armv6k - armv6zk - armv7 - armv7a - None of currently available CPUTYPE options allows us to choose one of architectures above, thus additional target is needed. From now on world for multicore ARM targets should be built with -CPUTYPE=armv6k or -CPUTYPE=cortexa - Completely remove option ARM_TP_ADDRESS (no longer used) - Propagate TLB maintenance operations in SMP mode (follow up for changes proposed by Giovanni Trematerra) - pcpup pointer is common for every core, thus using it is not SMP safe - use proper cpufunctions for cortexa processors diff --git a/share/mk/bsd.cpu.mk b/share/mk/bsd.cpu.mk index 747dd29..76d7cfc 100644 --- a/share/mk/bsd.cpu.mk +++ b/share/mk/bsd.cpu.mk @@ -98,13 +98,15 @@ _CPUCFLAGS = -march=${CPUTYPE} . if ${CPUTYPE} == "xscale" #XXX: gcc doesn't seem to like -mcpu=xscale, and dies while rebuilding itself #_CPUCFLAGS = -mcpu=xscale -_CPUCFLAGS = -march=armv5te -D__XSCALE__ -DARM_WANT_TP_ADDRESS +_CPUCFLAGS = -march=armv5te -D__XSCALE__ . elif ${CPUTYPE} == "armv6" _CPUCFLAGS = -march=${CPUTYPE} -DARM_ARCH_6=1 +. elif ${CPUTYPE} == "armv6k" +_CPUCFLAGS = -march=${CPUTYPE} -DARM_ARCH_6=1 . elif ${CPUTYPE} == "cortexa" -_CPUCFLAGS = -march=armv6 -DARM_ARCH_6=1 -mfpu=vfp +_CPUCFLAGS = -march=armv6k -DARM_ARCH_6=1 -mfpu=vfp . else -_CPUCFLAGS = -mcpu=${CPUTYPE} -DARM_WANT_TP_ADDRESS +_CPUCFLAGS = -mcpu=${CPUTYPE} . endif . elif ${MACHINE_ARCH} == "powerpc" . if ${CPUTYPE} == "e500" diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c index dd43c27..1d6f93f 100644 --- a/sys/arm/arm/cpufunc.c +++ b/sys/arm/arm/cpufunc.c @@ -1049,14 +1049,14 @@ struct cpu_functions cortexa_cpufuncs = { armv7_tlb_flushID, /* tlb_flushID */ armv7_tlb_flushID_SE, /* tlb_flushID_SE */ - arm11_tlb_flushI, /* tlb_flushI */ - arm11_tlb_flushI_SE, /* tlb_flushI_SE */ - arm11_tlb_flushD, /* tlb_flushD */ - arm11_tlb_flushD_SE, /* tlb_flushD_SE */ + armv7_tlb_flushID, /* tlb_flushI */ + armv7_tlb_flushID_SE, /* tlb_flushI_SE */ + armv7_tlb_flushID, /* tlb_flushD */ + armv7_tlb_flushID_SE, /* tlb_flushD_SE */ /* Cache operations */ - armv7_idcache_wbinv_all, /* icache_sync_all */ + armv7_idcache_wbinv_all, /* icache_sync_all */ armv7_icache_sync_range, /* icache_sync_range */ armv7_dcache_wbinv_all, /* dcache_wbinv_all */ @@ -1079,20 +1079,20 @@ struct cpu_functions cortexa_cpufuncs = { /* Other functions */ cpufunc_nullop, /* flush_prefetchbuf */ - arm11_drain_writebuf, /* drain_writebuf */ + armv7_drain_writebuf, /* drain_writebuf */ cpufunc_nullop, /* flush_brnchtgt_C */ (void *)cpufunc_nullop, /* flush_brnchtgt_E */ - arm11_sleep, /* sleep */ + armv7_cpu_sleep, /* sleep */ /* Soft functions */ cpufunc_null_fixup, /* dataabt_fixup */ cpufunc_null_fixup, /* prefetchabt_fixup */ - arm11_context_switch, /* context_switch */ + armv7_context_switch, /* context_switch */ - cortexa_setup /* cpu setup */ + cortexa_setup /* cpu setup */ }; #endif /* CPU_CORTEXA */ diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S index e81912c..99b214a 100644 --- a/sys/arm/arm/locore.S +++ b/sys/arm/arm/locore.S @@ -166,7 +166,11 @@ Lunmapped: orr r0, r0, #2 /* Set TTB shared memory flag */ #endif mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ - mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ +#ifdef SMP + mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */ +#else + mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ +#endif #if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) mov r0, #0 @@ -361,7 +365,11 @@ Ltag: orr r0, r0, #0 /* Set TTB shared memory flag */ #endif mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ - mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ +#ifdef SMP + mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */ +#else + mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ +#endif #if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) mov r0, #0 diff --git a/sys/arm/include/pcpu.h b/sys/arm/include/pcpu.h index f12f903..43ffb44 100644 --- a/sys/arm/include/pcpu.h +++ b/sys/arm/include/pcpu.h @@ -100,8 +100,8 @@ set_tls(void *tls) #define PCPU_GET(member) (get_pcpu()->pc_ ## member) #define PCPU_ADD(member, value) (get_pcpu()->pc_ ## member += (value)) #define PCPU_INC(member) PCPU_ADD(member, 1) -#define PCPU_PTR(member) (&pcpup->pc_ ## member) -#define PCPU_SET(member,value) (pcpup->pc_ ## member = (value)) +#define PCPU_PTR(member) (&get_pcpu()->pc_ ## member) +#define PCPU_SET(member,value) (get_pcpu()->pc_ ## member = (value)) void pcpu0_init(void); #endif /* _KERNEL */ diff --git a/sys/conf/options.arm b/sys/conf/options.arm index 2fe7b9f..e9c8187 100644 --- a/sys/conf/options.arm +++ b/sys/conf/options.arm @@ -7,7 +7,6 @@ ARM_L2_PIPT opt_global.h ARM_MANY_BOARD opt_global.h ARM_USE_SMALL_ALLOC opt_global.h ARM_VFP_SUPPORT opt_global.h -ARM_WANT_TP_ADDRESS opt_global.h COUNTS_PER_SEC opt_timer.h CPU_ARM9 opt_global.h CPU_ARM9E opt_global.h --------------090609080402090500000504 Content-Type: text/x-patch; name="2_ARM_cleanup.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="2_ARM_cleanup.diff" commit 3ad13773d26bffe4212858c38280d1bb874548e6 Author: Lukasz Plachno Date: Thu Nov 22 09:41:09 2012 +0100 arm: Cleanup in ARM specific code - Unify descriptions for cache and TLB maintenance operations - Use architecture macros instead of CPU specific ones in generic code diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S index 58f295c..03561b8 100644 --- a/sys/arm/arm/cpufunc_asm_armv7.S +++ b/sys/arm/arm/cpufunc_asm_armv7.S @@ -71,9 +71,9 @@ ENTRY(armv7_setttb) orr r0, r0, #PT_ATTR mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */ #ifdef SMP - mcr p15, 0, r0, c8, c3, 0 /* invalidate I+D TLBs Inner Shareable*/ + mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */ #else - mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ + mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ #endif dsb isb @@ -82,11 +82,11 @@ ENTRY(armv7_setttb) ENTRY(armv7_tlb_flushID) dsb #ifdef SMP - mcr p15, 0, r0, c8, c3, 0 /* flush I+D tlb */ - mcr p15, 0, r0, c7, c1, 6 /* flush BTB */ + mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */ + mcr p15, 0, r0, c7, c1, 6 /* Flush BTB Inner Shareable */ #else - mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ - mcr p15, 0, r0, c7, c5, 6 /* flush BTB */ + mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ + mcr p15, 0, r0, c7, c5, 6 /* Flush BTB */ #endif dsb isb @@ -96,10 +96,10 @@ ENTRY(armv7_tlb_flushID_SE) ldr r1, .Lpage_mask bic r0, r0, r1 #ifdef SMP - mcr p15, 0, r0, c8, c3, 1 /* flush D tlb single entry Inner Shareable*/ + mcr p15, 0, r0, c8, c3, 1 /* Invalidate I+D TLB single entry Inner Shareable */ mcr p15, 0, r0, c7, c1, 6 /* flush BTB Inner Shareable */ #else - mcr p15, 0, r0, c8, c7, 1 /* flush D tlb single entry */ + mcr p15, 0, r0, c8, c7, 1 /* Invalidate I+D TLB single entry Inner Shareable */ mcr p15, 0, r0, c7, c5, 6 /* flush BTB */ #endif dsb @@ -262,9 +262,9 @@ ENTRY(armv7_context_switch) mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ #ifdef SMP - mcr p15, 0, r0, c8, c3, 0 /* and flush the I+D tlbs Inner Sharable */ + mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */ #else - mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */ + mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ #endif dsb isb diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S index 99b214a..e6349e6 100644 --- a/sys/arm/arm/locore.S +++ b/sys/arm/arm/locore.S @@ -38,6 +38,7 @@ #include #include #include +#include __FBSDID("$FreeBSD$"); @@ -172,7 +173,7 @@ Lunmapped: mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ #endif -#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) +#if defined(ARM_ARCH_6_7A) mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ #endif @@ -182,7 +183,7 @@ Lunmapped: mcr p15, 0, r0, c3, c0, 0 /* Enable MMU */ mrc p15, 0, r0, c1, c0, 0 -#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) +#if defined(ARM_ARCH_6_7A) orr r0, r0, #CPU_CONTROL_V6_EXTPAGE #endif orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE) @@ -371,7 +372,7 @@ Ltag: mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ #endif -#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) +#if defined(ARM_ARCH_6_7A) mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ #endif @@ -383,7 +384,7 @@ Ltag: mcr p15, 0, r0, c3, c0, 0 /* Enable MMU */ mrc p15, 0, r0, c1, c0, 0 -#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) +#if defined(ARM_ARCH_6_7A) orr r0, r0, #CPU_CONTROL_V6_EXTPAGE #endif orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE) diff --git a/sys/arm/arm/machdep.c b/sys/arm/arm/machdep.c index 17a60c2..7ebbbb0 100644 --- a/sys/arm/arm/machdep.c +++ b/sys/arm/arm/machdep.c @@ -834,7 +834,7 @@ fake_preload_metadata(struct arm_boot_params *abp __unused) void pcpu0_init(void) { -#if ARM_ARCH_6 || ARM_ARCH_7A || defined(CPU_MV_PJ4B) +#if defined(ARM_ARCH_6_7A) set_pcpu(pcpup); #endif pcpu_init(pcpup, 0, sizeof(struct pcpu)); diff --git a/sys/arm/include/cpuconf.h b/sys/arm/include/cpuconf.h index 95d4b91..18954b3 100644 --- a/sys/arm/include/cpuconf.h +++ b/sys/arm/include/cpuconf.h @@ -102,6 +102,10 @@ #define ARM_ARCH_7A 0 #endif +#if ARM_ARCH_6 || ARM_ARCH_7A +#define ARM_ARCH_6_7A +#endif + #define ARM_NARCH (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 | ARM_ARCH_7A) #if ARM_NARCH == 0 && !defined(KLD_MODULE) && defined(_KERNEL) #error ARM_NARCH is 0 diff --git a/sys/arm/include/pcpu.h b/sys/arm/include/pcpu.h index 43ffb44..3626014 100644 --- a/sys/arm/include/pcpu.h +++ b/sys/arm/include/pcpu.h @@ -60,7 +60,7 @@ struct pcb; struct pcpu; extern struct pcpu *pcpup; -#if ARM_ARCH_6 || ARM_ARCH_7A +#if defined(ARM_ARCH_6_7A) /* or ARM_TP_ADDRESS mark REMOVE ME NOTE */ static inline struct pcpu * get_pcpu(void) --------------090609080402090500000504 Content-Type: text/x-patch; name="3_trampoline.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="3_trampoline.diff" commit 429593cf4808f288aeb171e8ce6863f3cd23358b Author: Lukasz Plachno Date: Thu Nov 22 10:05:16 2012 +0100 arm: Remove armv7 targets from kernel.trampoline - armv7 targets are not working currently - add debug kernel map for build targets - disable building kernel trampoline for not supported targets diff --git a/sys/arm/arm/elf_trampoline.c b/sys/arm/arm/elf_trampoline.c index 2a218bf..c47afa6 100644 --- a/sys/arm/arm/elf_trampoline.c +++ b/sys/arm/arm/elf_trampoline.c @@ -74,26 +74,18 @@ void __startC(void); #define cpu_idcache_wbinv_all xscale_cache_purgeID #elif defined(CPU_XSCALE_81342) #define cpu_idcache_wbinv_all xscalec3_cache_purgeID -#elif defined(CPU_MV_PJ4B) -#if !defined(SOC_MV_ARMADAXP) -#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all #else -#define cpu_idcache_wbinv_all() armadaxp_idcache_wbinv_all +#define cpu_idcache_wbinv_all() #endif -#endif /* CPU_MV_PJ4B */ + #ifdef CPU_XSCALE_81342 #define cpu_l2cache_wbinv_all xscalec3_l2cache_purge #elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) #define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all -#elif defined(CPU_CORTEXA) -#define cpu_idcache_wbinv_all armv7_idcache_wbinv_all -#define cpu_l2cache_wbinv_all() #else -#define cpu_l2cache_wbinv_all() +#define cpu_l2cache_wbinv_all() #endif -static void armadaxp_idcache_wbinv_all(void); - int arm_picache_size; int arm_picache_line_size; int arm_picache_ways; @@ -354,18 +346,6 @@ arm9_setup(void) arm9_dcache_index_max = 0U - arm9_dcache_index_inc; } -static void -armadaxp_idcache_wbinv_all(void) -{ - uint32_t feat; - - __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (feat)); - if (feat & ARM_PFR0_THUMBEE_MASK) - armv7_idcache_wbinv_all(); - else - armv6_idcache_wbinv_all(); - -} #ifdef KZIP static unsigned char *orig_input, *i_input, *i_output; diff --git a/sys/conf/Makefile.arm b/sys/conf/Makefile.arm index 6270aef..78c7b32 100644 --- a/sys/conf/Makefile.arm +++ b/sys/conf/Makefile.arm @@ -51,6 +51,7 @@ SYSTEM_LD_TAIL +=;sed s/" + SIZEOF_HEADERS"// ldscript.$M\ ${SYSTEM_LD_}; \ ${OBJCOPY} -S -O binary ${FULLKERNEL}.noheader \ ${KERNEL_KO}.bin; \ + ${NM} ${FULLKERNEL}.noheader | sort > ${FULLKERNEL}.map; \ rm ${FULLKERNEL}.noheader .if defined(MFS_IMAGE) @@ -63,8 +64,11 @@ FILES_CPU_FUNC = $S/$M/$M/cpufunc_asm_arm7tdmi.S \ $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S \ $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S + $S/$M/$M/cpufunc_asm_armv6.S +NO_TRAMP!= grep 'CPU_CORTEXA\|CPU_MV_PJ4B' opt_global.h || true ; echo + +.if ${NO_TRAMP} == "" KERNEL_EXTRA=trampoline KERNEL_EXTRA_INSTALL=kernel.gz.tramp trampoline: ${KERNEL_KO}.tramp @@ -110,6 +114,7 @@ ${KERNEL_KO}.tramp: ${KERNEL_KO} $S/$M/$M/inckern.S $S/$M/$M/elf_trampoline.c ${KERNEL_KO}.gz.tramp.bin rm ${KERNEL_KO}.tmp.gz ${KERNEL_KO}.tramp.noheader opt_kernname.h \ inflate-tramp.o tmphack.S +.endif MKMODULESENV+= MACHINE=${MACHINE} --------------090609080402090500000504 Content-Type: text/x-patch; name="4_tex_remap.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="4_tex_remap.diff" commit dc9a9b9e970d51a28ceaf71d3d0cf24f69375329 Author: Lukasz Plachno Date: Thu Nov 22 09:57:32 2012 +0100 arm: Implement new way for pagetable memory attributes management - initialize PRRR and NMRR registers in cp15 - enable TEX remapping - create macros for TTB attributes diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c index 1d6f93f..c35becc 100644 --- a/sys/arm/arm/cpufunc.c +++ b/sys/arm/arm/cpufunc.c @@ -2327,6 +2327,7 @@ pj4bv6_setup(char *args) cpuctrl |= CPU_CONTROL_VECRELOC; cpuctrl |= (0x5 << 16); cpuctrl |= CPU_CONTROL_V6_EXTPAGE; + cpuctrl |= CPU_CONTROL_TEX_REMAP; /* XXX not yet */ /* cpuctrl |= CPU_CONTROL_L2_ENABLE; */ @@ -2362,6 +2363,7 @@ pj4bv7_setup(args) cpuctrl |= CPU_CONTROL_VECRELOC; cpuctrl |= (0x5 << 16) | (1 < 22); cpuctrl |= CPU_CONTROL_V6_EXTPAGE; + cpuctrl |= CPU_CONTROL_TEX_REMAP; /* Clear out the cache */ cpu_idcache_wbinv_all(); @@ -2392,7 +2394,8 @@ cortexa_setup(char *args) cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE | - CPU_CONTROL_BPRD_ENABLE; + CPU_CONTROL_BPRD_ENABLE | + CPU_CONTROL_TEX_REMAP; #ifndef ARM32_DISABLE_ALIGNMENT_FAULTS cpuctrl |= CPU_CONTROL_AFLT_ENABLE; diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S index 03561b8..d6f9d59 100644 --- a/sys/arm/arm/cpufunc_asm_armv7.S +++ b/sys/arm/arm/cpufunc_asm_armv7.S @@ -32,6 +32,8 @@ #include __FBSDID("$FreeBSD$"); +#include + .cpu cortex-a8 .Lcoherency_level: @@ -45,30 +47,13 @@ __FBSDID("$FreeBSD$"); .Lpage_mask: .word 0xfff -#define PT_NOS (1 << 5) -#define PT_S (1 << 1) -#define PT_INNER_NC 0 -#define PT_INNER_WT (1 << 0) -#define PT_INNER_WB ((1 << 0) | (1 << 6)) -#define PT_INNER_WBWA (1 << 6) -#define PT_OUTER_NC 0 -#define PT_OUTER_WT (2 << 3) -#define PT_OUTER_WB (3 << 3) -#define PT_OUTER_WBWA (1 << 3) - -#ifdef SMP -#define PT_ATTR (PT_S|PT_INNER_WT|PT_OUTER_WT|PT_NOS) -#else -#define PT_ATTR (PT_INNER_WT|PT_OUTER_WT) -#endif - ENTRY(armv7_setttb) stmdb sp!, {r0, lr} bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */ ldmia sp!, {r0, lr} dsb - orr r0, r0, #PT_ATTR + orr r0, r0, #TTB_ATTR mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */ #ifdef SMP mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */ @@ -258,7 +243,7 @@ ENTRY(armv7_cpu_sleep) ENTRY(armv7_context_switch) dsb - orr r0, r0, #PT_ATTR + orr r0, r0, #TTB_ATTR mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ #ifdef SMP diff --git a/sys/arm/arm/cpufunc_asm_pj4b.S b/sys/arm/arm/cpufunc_asm_pj4b.S index f6890d9..f2eba94 100644 --- a/sys/arm/arm/cpufunc_asm_pj4b.S +++ b/sys/arm/arm/cpufunc_asm_pj4b.S @@ -33,6 +33,7 @@ __FBSDID("$FreeBSD$"); #include +#include .Lpj4b_cache_line_size: .word _C_LABEL(arm_pdcache_line_size) @@ -40,9 +41,7 @@ __FBSDID("$FreeBSD$"); ENTRY(pj4b_setttb) /* Cache synchronization is not required as this core has PIPT caches */ mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */ -#ifdef SMP - orr r0, r0, #2 /* Set TTB shared memory flag */ -#endif + orr r0, r0, #TTB_ATTR /* Set TTB memory flags */ mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ RET @@ -199,4 +198,5 @@ ENTRY(pj4b_config) orr r0, r0, #(1 << 5) mcr p15, 0, r0, c1, c0, 1 #endif + RET diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S index e6349e6..88a85ac 100644 --- a/sys/arm/arm/locore.S +++ b/sys/arm/arm/locore.S @@ -163,8 +163,9 @@ Lunmapped: orrne r5, r5, #PHYSADDR movne pc, r5 -#if defined(SMP) - orr r0, r0, #2 /* Set TTB shared memory flag */ +#if ARM_MMU_V7 != 0 + /* For primary pagetable normal non-cacheable memory is used */ + orr r0, r0, #TTB_FLAGS_2 /* Set TTB memory flags */ #endif mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ #ifdef SMP @@ -173,6 +174,19 @@ Lunmapped: mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ #endif +#if ARM_MMU_V7 != 0 + /* Set PRRR and NMRR cp15 registers */ + ldr r0, =PRRR + mcr p15, 0, r0, c10, c2, 0 + ldr r0, =NMRR + mcr p15, 0, r0, c10, c2, 1 + + /* Set TEX Remap */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, #CPU_CONTROL_TEX_REMAP + mcr p15, 0, r0, c1, c0, 0 +#endif + #if defined(ARM_ARCH_6_7A) mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ @@ -362,8 +376,10 @@ Ltag: bic r0, r0, #0xf0000000 orr r0, r0, #PHYSADDR ldr r0, [r0] -#if defined(SMP) - orr r0, r0, #0 /* Set TTB shared memory flag */ + +#if ARM_MMU_V7 != 0 + /* For primary pagetable normal non-cacheable memory is used */ + orr r0, r0, #TTB_FLAGS_2 /* Set TTB memory flags */ #endif mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ #ifdef SMP @@ -372,6 +388,19 @@ Ltag: mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */ #endif +#if ARM_MMU_V7 != 0 + /* Set PRRR and NMRR cp15 registers */ + ldr r0, =PRRR + mcr p15, 0, r0, c10, c2, 0 + ldr r0, =NMRR + mcr p15, 0, r0, c10, c2, 1 + + /* Set TEX Remap */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, #CPU_CONTROL_TEX_REMAP + mcr p15, 0, r0, c1, c0, 0 +#endif + #if defined(ARM_ARCH_6_7A) mov r0, #0 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ diff --git a/sys/arm/arm/pmap-v6.c b/sys/arm/arm/pmap-v6.c index a44bdbf..aafb1e4 100644 --- a/sys/arm/arm/pmap-v6.c +++ b/sys/arm/arm/pmap-v6.c @@ -386,6 +386,48 @@ static struct vm_object pvzone_obj; static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0; static struct rwlock pvh_global_lock; +#if defined(SMP) +#define L1_SHAREABLE L1_SHARED +#define L2_SHAREABLE L2_SHARED +#else +#define L1_SHAREABLE 0 +#define L2_SHAREABLE 0 +#endif /* SMP */ + +#if ARM_MMU_V7 != 0 +int l1_mem_types[] = { + (L1_SHAREABLE), + (L1_SHAREABLE | L1_S_B), + (L1_SHAREABLE | L1_S_C), + (L1_SHAREABLE | L1_S_C | L1_S_B), + (L1_SHAREABLE | L1_S_TEX(1)), + (L1_SHAREABLE | L1_S_TEX(1) | L1_S_B), + (L1_SHAREABLE), + (L1_SHAREABLE | L1_S_TEX(1) | L1_S_C | L1_S_B) +}; + +int l2l_mem_types[] = { + (L2_SHAREABLE), + (L2_SHAREABLE | L2_B), + (L2_SHAREABLE | L2_C), + (L2_SHAREABLE | L2_C | L2_B), + (L2_SHAREABLE | L2_L_TEX(1)), + (L2_SHAREABLE | L2_L_TEX(1) | L2_B), + (L2_SHAREABLE), + (L2_SHAREABLE | L2_L_TEX(1) | L2_C | L2_B) +}; + +int l2s_mem_types[] = { + (L2_SHAREABLE), + (L2_SHAREABLE | L2_B), + (L2_SHAREABLE | L2_C), + (L2_SHAREABLE | L2_C | L2_B), + (L2_SHAREABLE | L2_S_TEX(1)), + (L2_SHAREABLE | L2_S_TEX(1) | L2_B), + (L2_SHAREABLE), + (L2_SHAREABLE | L2_S_TEX(1) | L2_C | L2_B) +}; +#else int l1_mem_types[] = { ARM_L1S_STRONG_ORD, ARM_L1S_DEVICE_NOSHARE, @@ -415,6 +457,7 @@ int l2s_mem_types[] = { ARM_L2S_NRML_IWB_OWB, ARM_L2S_NRML_IWBA_OWBA }; +#endif /* * This list exists for the benefit of pmap_map_chunk(). It keeps track diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h index 05b3846..f5ccfb9 100644 --- a/sys/arm/include/armreg.h +++ b/sys/arm/include/armreg.h @@ -286,6 +286,7 @@ #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ #define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ #define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ +#define CPU_CONTROL_TEX_REMAP 0x10000000 /* TEX Remap enabled */ #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE diff --git a/sys/arm/include/pmap.h b/sys/arm/include/pmap.h index e20bf18..b46e3b1 100644 --- a/sys/arm/include/pmap.h +++ b/sys/arm/include/pmap.h @@ -52,33 +52,140 @@ #include #include + +/* + * When TEX remap is enabled (SCTLR.TRE is set to 1), + * PRRR and NMRR values needs to be initialized before MMU is used. + * + * TEX[0],C,B -> index(n) + * + * PMRR -> memory type (strongly ordered, device, normal), shareability + * TR (PRRR[2n+1:2n]) -> memory type + * NOS (PRRR[24+n]) -> non outer shareable attribute + * DS0 (PRRR[16]) -> device memory shareable attribute (S = 0) + * DS1 (PRRR[17]) -> device memory shareable attribute (S = 1) + * NS0 (PRRR[18]) -> normal memory shareable attribute (S = 0) + * NS1 (PRRR[19]) -> normal memory shareable attribute (S = 1) + * + * NMRR -> cache policy (no cache, WT, WB, WBWA) + * IR (NMRR[2n+1;2n]) -> inner cache property + * OR (NMRR[2n+17;2n+16]) -> outer cache property + * + * Memory type index TR IR OR + * STRONGLY_ORDERED 0 00 + * DEVICE 1 01 + * NOCACHE 2 10 00 00 + * IWT_OWT 3 10 10 10 + * IWB_OWB 4 10 11 11 + * IWBA_OWBA 5 10 01 01 + * RESERVED 6 + * IWBA_OWB 7 10 01 11 + * + * Other attributes: + * DS0 = 0 + * DS1 = 1 + * NS0 = 0 + * NS1 = 1 + * + * Outer shareability is implementation dependent feature in armv7 + * specification, for now safe value (disable outer shareability) is used + * NOS[0:7] = 1 + */ + +#define NMRR 0xc7804780 +#define PRRR 0xff0a8aa4 + +/* + * ARMv7 TTBR bit definition + */ +#if ARM_MMU_V7 != 0 +#define PT_NOS (1 << 5) +#define PT_OUTER_NC 0 +#define PT_OUTER_WB (3 << 3) +#define PT_OUTER_WBWA (1 << 3) +#define PT_OUTER_WT (2 << 3) +#define PT_S (1 << 1) +#if defined(SMP) +#define PT_INNER_NC 0 +#define PT_INNER_WB ((1 << 0) | (1 << 6)) +#define PT_INNER_WBWA (1 << 6) +#define PT_INNER_WT (1 << 0) +#define PT_SHAREABLE (PT_S) +#else + +/* + * In ARMv6 and ARMV7 without multiprocessor extension, + * pagetable memory inner cacheability policy is implementation defined + */ +#define PT_INNER_NC 0 +#define PT_INNER_WB (1 << 0) +#define PT_INNER_WBWA (1 << 0) +#define PT_INNER_WT (1 << 0) +#define PT_SHAREABLE 0 +#endif /* SMP */ + +#define TTB_FLAGS_0 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC) +#define TTB_FLAGS_1 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC) +#define TTB_FLAGS_2 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC) +#define TTB_FLAGS_3 (PT_SHAREABLE | PT_NOS | PT_INNER_WT | PT_OUTER_WT) +#define TTB_FLAGS_4 (PT_SHAREABLE | PT_NOS | PT_INNER_WB | PT_OUTER_WB) +#define TTB_FLAGS_5 (PT_SHAREABLE | PT_NOS | PT_INNER_WBWA | PT_OUTER_WBWA) +#define TTB_FLAGS_6 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC) +#define TTB_FLAGS_7 (PT_SHAREABLE | PT_NOS | PT_INNER_WBWA | PT_OUTER_WB) +#endif /* (ARM_MMU_V7) != 0 */ + /* - * Pte related macros + * Pte related macros + * + * Memory types when tex remap is enabled (armv6 and armv7): + * 0 - strongly ordered + * 1 - device memory, + * 2 - normal memory, non cacheable + * 3 - normal memory, inner write-through, outer write-through + * 4 - normal memory, inner write-back, outer write-back + * 5 - normal memory, inner write-back write-allocate, + * outer write-back write-allocate + * 6 - reserved value + * 7 - normal memory, inner write-back write-allocate, outer write-back + * + * Memory types when tex remap is disabled / not supported: + * 0 - strongly ordered + * 1 - device memory, non shareable + * 2 - device memory, shareable + * 3 - normal memory, non cacheable + * 4 - normal memory, inner write-through, outer write-through + * 5 - normal memory, inner write-back, outer write-back + * 6 - normal memory, inner write-back write-allocate, + * outer write-back write-allocate */ -#if ARM_ARCH_6 || ARM_ARCH_7A + +#if ARM_MMU_V7 != 0 +#define PTE_CACHE 5 +#define PTE_DEVICE 1 +#define PTE_NOCACHE 2 + +/* TTB_FLAGS number must be the same as PTE_PAGETABLE value */ +#define PTE_PAGETABLE 5 +#define TTB_ATTR TTB_FLAGS_5 +#elif ARM_MMU_V6 != 0 #ifdef SMP #define PTE_NOCACHE 2 #else #define PTE_NOCACHE 1 -#endif +#endif /* SMP */ #define PTE_CACHE 4 #define PTE_DEVICE 2 #define PTE_PAGETABLE 4 -#else -#define PTE_NOCACHE 1 + +#define TTB_ATTR 0 +#else /* ARM_MMU_V6 == 0 && ARM_MMU_V7 == 0 */ #define PTE_CACHE 2 +#define PTE_NOCACHE 1 #define PTE_PAGETABLE 3 + +#define TTB_ATTR 0 #endif -enum mem_type { - STRONG_ORD = 0, - DEVICE_NOSHARE, - DEVICE_SHARE, - NRML_NOCACHE, - NRML_IWT_OWT, - NRML_IWB_OWB, - NRML_IWBA_OWBA -}; #ifndef LOCORE @@ -427,6 +534,8 @@ extern int pmap_needs_pte_sync; #elif defined(CPU_XSCALE_81342) #define PMAP_NEEDS_PTE_SYNC 1 #define PMAP_INCLUDE_PTE_SYNC +#elif ARM_MMU_V7 != 0 +#define PMAP_NEEDS_PTE_SYNC 1 #elif (ARM_MMU_SA1 == 0) #define PMAP_NEEDS_PTE_SYNC 0 #endif --------------090609080402090500000504 Content-Type: text/x-patch; name="5_memory_barriers.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="5_memory_barriers.diff" commit 03e3d3e90ddaa03c6a62265b96b55f122a8abb48 Author: Lukasz Plachno Date: Tue Nov 20 09:21:03 2012 +0100 arm: Add macros for memory barriers - In armv6 "dsb" operation is not supported - In armv7 use of register r7 in cp15 is deprecated diff --git a/sys/arm/include/atomic.h b/sys/arm/include/atomic.h index 1a96176..2050b55 100644 --- a/sys/arm/include/atomic.h +++ b/sys/arm/include/atomic.h @@ -47,9 +47,35 @@ #include #endif -#define mb() -#define wmb() -#define rmb() +#if ARM_ARCH_7A != 0 +#define mb() do { \ + __asm __volatile("dsb"); \ + } while (0) +#define wmb() do { \ + __asm __volatile("dsb"); \ + } while (0) +#define rmb() do { \ + __asm __volatile("dsb"); \ + } while (0) +#elif ARM_ARCH_6 != 0 +#define mb() do { \ + uint32_t reg = 0; \ + __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (reg)); \ + } while (0) +#define wmb() do { \ + uint32_t reg = 0; \ + __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (reg)); \ + } while (0) +#define rmb() do { \ + uint32_t reg = 0; \ + __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (reg)); \ + } while (0) +#else +#define mb() +#define wmb() +#define rmb() +#endif + #ifndef I32_bit #define I32_bit (1 << 7) /* IRQ disable */ --------------090609080402090500000504-- From owner-freebsd-arm@FreeBSD.ORG Thu Nov 22 16:48:28 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 7EC451CF for ; Thu, 22 Nov 2012 16:48:28 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from mail-ie0-f182.google.com (mail-ie0-f182.google.com [209.85.223.182]) by mx1.freebsd.org (Postfix) with ESMTP id 330B98FC14 for ; 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[50.78.194.198]) by mx.google.com with ESMTPS id bh3sm2386190igc.0.2012.11.22.08.46.56 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 22 Nov 2012 08:48:25 -0800 (PST) Sender: Warner Losh Subject: Re: ARM/SMP, Some patches for review. Mime-Version: 1.0 (Apple Message framework v1085) Content-Type: text/plain; charset=utf-8 From: Warner Losh In-Reply-To: <50AE3C0F.20809@semihalf.com> Date: Thu, 22 Nov 2012 09:46:25 -0700 Content-Transfer-Encoding: quoted-printable Message-Id: <94A3C1F1-0138-4D11-85BC-9E988AEF2E9F@bsdimp.com> References: <50AA4E87.3000505@semihalf.com> <50ACE2B4.8010904@semihalf.com> <50AE3C0F.20809@semihalf.com> To: =?utf-8?Q?=C5=81ukasz_P=C5=82achno?= X-Mailer: Apple Mail (2.1085) X-Gm-Message-State: ALoCoQlndsdEo3Q1qB3C0z32r5dzCz58VQESi2cazErb7rL2c/wvNEw9wPMEvZeUkuv71SfwfcyN Cc: freebsd-arm@freebsd.org, cognet@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 22 Nov 2012 16:48:28 -0000 On Nov 22, 2012, at 7:51 AM, =C5=81ukasz P=C5=82achno wrote: > On 21.11.2012 17:00, Giovanni Trematerra wrote: >> On Wed, Nov 21, 2012 at 3:18 PM, =C5=81ukasz P=C5=82achno = wrote: >>> On 20.11.2012 00:08, Giovanni Trematerra wrote: >>>>=20 >>>> On Mon, Nov 19, 2012 at 4:21 PM, =C5=81ukasz P=C5=82achno = wrote: >>>>>=20 >>>>> Hi, >>>>>=20 >>>>> I would like to propose few changes for ARM specific code. >>>>> Three attached patches for freebsd-current allows building = SMP-safe world >>>>> for ARM targets and turns on TEX remap for ARMv6 and ARMv7 = targets. >>>>>=20 >>>>> More details inside patch files. >>>>>=20 >>>>> Change introduced by "commit-2" removes armv7 targets (armv7 and = pj4b) >>>>> from >>>>> kernel.tramp. >>>>> AFAIK this feature is not working properly for armv7 targets and = is >>>>> causing >>>>> problem during compilation: >>>>> - LOCORE is defined during kernel compilation but not defined = during >>>>> kernel.tramp compilation, so #include pmap.h causes build errors. >>>>>=20 >>>>> I do not think adding hack like this: >>>>> #ifndef LOCORE >>>>> #define LOCORE >>>>> #endif >>>>>=20 >>>>> to allow building something that is already broken is a good idea, = so I >>>>> removed cpufunc_asm_pj4b.S and cpufunc_asm_armv7.S from = Makefile.arm >>>>=20 >>>>=20 >>>> In commit-2.txt >>>> you should include style changes in sys/arm/arm/cpufunc_asm_armv7.S >>>> into a different patch. >>>=20 >>>=20 >>> fixed >>>=20 >>>=20 >>>>=20 >>>> @@ -63,7 +64,6 @@ FILES_CPU_FUNC =3D = $S/$M/$M/cpufunc_asm_arm7tdmi.S \ >>>> $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ >>>> $S/$M/$M/cpufunc_asm_xscale_c3.S = $S/$M/$M/cpufunc_asm_armv5_ec.S >>>> \ >>>> $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S = \ >>>> - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S >>>>=20 >>>> You left a trailing back slash but beside that you should clean up >>>> sys/arm/arm/elf_trampoline.c >>>> and not make kernel.tramp to build at all for armv7 cpus or you'll = end >>>> up with a linker error >>>> during generation of the kernel.tramp. >>>>=20 >>>=20 >>> Fixed, updated set of patches is attached. >>>=20 >>> - TEX remap is supported only for armv6 (changed to avoid breaking = armv6 >>> targets) >>> - Fixed issues with build for pre-armv6 targets (tested with make = tinderbox >>> TARGETS=3Darm >>>=20 >>=20 >> 1_SMP_fixes.diff >> You'll endup to get a panic for PandaBoard systems. >> The arm11 functions don't handle the SMP case. >> So I propose to merge the changes below or commit them first. >>=20 >> Index: sys/arm/arm/cpufunc.c >> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >> --- sys/arm/arm/cpufunc.c (revision 243182) >> +++ sys/arm/arm/cpufunc.c (working copy) >> @@ -1079,18 +1079,18 @@ struct cpu_functions cortexa_cpufuncs =3D { >> /* Other functions */ >>=20 >> cpufunc_nullop, /* flush_prefetchbuf */ >> - arm11_drain_writebuf, /* drain_writebuf */ >> + armv7_drain_writebuf, /* drain_writebuf */ >> cpufunc_nullop, /* flush_brnchtgt_C */ >> (void *)cpufunc_nullop, /* flush_brnchtgt_E */ >>=20 >> - arm11_sleep, /* sleep */ >> + armv7_cpu_sleep, /* sleep */ >>=20 >> /* Soft functions */ >>=20 >> cpufunc_null_fixup, /* dataabt_fixup */ >> cpufunc_null_fixup, /* prefetchabt_fixup */ >>=20 >> - arm11_context_switch, /* context_switch */ >> + armv7_context_switch, /* context_switch */ >>=20 >> cortexa_setup /* cpu setup */ >> }; >>=20 >=20 > I agree, but with this change I included also: >=20 > diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c > index dd43c27..1d6f93f 100644 > --- a/sys/arm/arm/cpufunc.c > +++ b/sys/arm/arm/cpufunc.c > @@ -1049,14 +1049,14 @@ struct cpu_functions cortexa_cpufuncs =3D { > =09 > armv7_tlb_flushID, /* tlb_flushID */ > armv7_tlb_flushID_SE, /* tlb_flushID_SE */ > - arm11_tlb_flushI, /* tlb_flushI */ > - arm11_tlb_flushI_SE, /* tlb_flushI_SE */ > - arm11_tlb_flushD, /* tlb_flushD */ > - arm11_tlb_flushD_SE, /* tlb_flushD_SE */ > + armv7_tlb_flushID, /* tlb_flushI */ > + armv7_tlb_flushID_SE, /* tlb_flushI_SE */ > + armv7_tlb_flushID, /* tlb_flushD */ > + armv7_tlb_flushID_SE, /* tlb_flushD_SE */ >=20 > Changes merged into patch 1_SMP_fixes.diff >=20 >>=20 >> 2_ARM_cleanup.diff >> Changes to sys/arm/arm/machdep.c don't seem style changes and >> they should live in a separate patch with a different motivation. >>=20 >> I'm not sure changes in sys/arm/arm/locore.S are style ones. >=20 > None of changes in this patch are related to style. In this patch I = wanted to improve code readability, not remove style conflicts. >=20 >>=20 >> I think that things like this aren't so readable. >> #if (ARM_ARCH_6 + ARM_ARCH_7A) !=3D 0 >>=20 >> Instead of things like that wouldn't be better to define different >> macros when the sum is zero or non zero and stick with the >> #if defined/!defined thing? >>=20 >> I mean in sys/arm/arm/cpuconf.h we could make something like this >>=20 >> #if (ARM_ARCH_6 + ARM_ARCH_7A) !=3D 0 >> #define ARM_ARCH_6_7A >> #endif >=20 > Changed to ARM_ARCH_6_7A >=20 >>=20 >> 3_kernel_trampoline.diff >> I think we should not make kernel_trampoline at all for the = unsupported CPUs. >> I propose this change to Makefile.arm >>=20 >> Index: sys/conf/Makefile.arm >> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >> --- sys/conf/Makefile.arm (revision 243182) >> +++ sys/conf/Makefile.arm (working copy) >> @@ -51,6 +51,7 @@ SYSTEM_LD_TAIL +=3D;sed s/" + SIZEOF_HEADERS"// = ldsc >> ${SYSTEM_LD_}; \ >> ${OBJCOPY} -S -O binary ${FULLKERNEL}.noheader \ >> ${KERNEL_KO}.bin; \ >> + ${NM} ${FULLKERNEL}.noheader | sort > = ${FULLKERNEL}.map; \ >> rm ${FULLKERNEL}.noheader >>=20 >> .if defined(MFS_IMAGE) >> @@ -62,9 +63,11 @@ FILES_CPU_FUNC =3D = $S/$M/$M/cpufunc_asm_arm7tdmi.S \ >> $S/$M/$M/cpufunc_asm_sa1.S $S/$M/$M/cpufunc_asm_arm10.S \ >> $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ >> $S/$M/$M/cpufunc_asm_xscale_c3.S = $S/$M/$M/cpufunc_asm_armv5_ec.S \ >> $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ >> - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S >> + $S/$M/$M/cpufunc_asm_armv6.S >>=20 >> +NO_TRAMP!=3D grep 'CPU_CORTEXA\|CPU_MV_PJ4B' opt_global.h || true ; = echo >> + >> +.if ${NO_TRAMP} =3D=3D "" >> KERNEL_EXTRA=3Dtrampoline >> KERNEL_EXTRA_INSTALL=3Dkernel.gz.tramp >> trampoline: ${KERNEL_KO}.tramp >> @@ -110,6 +113,7 @@ ${KERNEL_KO}.tramp: ${KERNEL_KO} = $S/$M/$M/inckern. >> ${KERNEL_KO}.gz.tramp.bin >> rm ${KERNEL_KO}.tmp.gz ${KERNEL_KO}.tramp.noheader = opt_kernname.h \ >> inflate-tramp.o tmphack.S >> +.endif >>=20 >> MKMODULESENV+=3D MACHINE=3D${MACHINE} >>=20 >=20 > Change merged into commit 3. I really don't like this part of the change. The if is ok, but the grep = isn't. It should be in the kernel config file as an option. I can be = in std.XXX files easily. >> 4_tex-remap.diff >> Some style(9) consideration. >> #include(s) should be grouped together in alphabetical order. >> So you should fix the pmap.h includes that you made. >>=20 >=20 > #defines reordered >=20 >> I'll try to test the pachset ASAP. >>=20 >=20 > New set of patches attached. I'll take a look at these in more detail... Warner > Regards, > =C5=81ukasz P=C5=82achno >=20 > = <1_SMP_fixes.diff><2_ARM_cleanup.diff><3_trampoline.diff><4_tex_remap.diff= ><5_memory_barriers.diff>_______________________________________________ > freebsd-arm@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-arm > To unsubscribe, send any mail to "freebsd-arm-unsubscribe@freebsd.org" From owner-freebsd-arm@FreeBSD.ORG Fri Nov 23 04:04:39 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 01D2B676 for ; Fri, 23 Nov 2012 04:04:38 +0000 (UTC) (envelope-from freebsd@damnhippie.dyndns.org) Received: from duck.symmetricom.us (duck.symmetricom.us [206.168.13.214]) by mx1.freebsd.org (Postfix) with ESMTP id 76AD18FC08 for ; Fri, 23 Nov 2012 04:04:38 +0000 (UTC) Received: from damnhippie.dyndns.org (daffy.symmetricom.us [206.168.13.218]) by duck.symmetricom.us (8.14.5/8.14.5) with ESMTP id qAN44Pke046952 for ; Thu, 22 Nov 2012 21:04:32 -0700 (MST) (envelope-from freebsd@damnhippie.dyndns.org) Received: from [172.22.42.240] (revolution.hippie.lan [172.22.42.240]) by damnhippie.dyndns.org (8.14.3/8.14.3) with ESMTP id qAN442be033469; Thu, 22 Nov 2012 21:04:03 -0700 (MST) (envelope-from freebsd@damnhippie.dyndns.org) Subject: Re: Dreamplug and eSATA problems From: Ian Lepore To: Dave Hayes In-Reply-To: <50A150C7.2080805@jetcafe.org> References: <50A150C7.2080805@jetcafe.org> Content-Type: multipart/mixed; boundary="=-U+0tiqhzPM3RGEvKkQUg" Date: Thu, 22 Nov 2012 21:04:02 -0700 Message-ID: <1353643442.69940.45.camel@revolution.hippie.lan> Mime-Version: 1.0 X-Mailer: Evolution 2.32.1 FreeBSD GNOME Team Port Cc: freebsd-arm@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Nov 2012 04:04:39 -0000 --=-U+0tiqhzPM3RGEvKkQUg Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Mon, 2012-11-12 at 11:40 -0800, Dave Hayes wrote: > After successfully booting my dreamplug to 9.1-PRERELEASE, I hooked an eSATA drive to my dreamplug. It partitioned and formatted fine (using > GPT and UFS2). Now when I try to fetch something from the net (using... > "fetch" ;) ) I get file corruption. An example: > > # fetch http://unbound.net/downloads/unbound-1.4.18.tar.gz > # sha256 unbound-1.4.18.tar.gz > SHA256 (unbound-1.4.18.tar.gz) = 178e065d2e443dc8fa579fa762a755687e9f79ddb93a7afe1c8f80ca38899158 > # fetch http://unbound.net/downloads/unbound-1.4.18.tar.gz > SHA256 (unbound-1.4.18.tar.gz) = 88a1ae10c6bf6b28f283335ec44a23975ca2d8300d776e01c04db1878a21c615 > > This only appears to happen when fetching to the eSATA drive. Fetching to the attached USB stick or the internal SD card does not have this issue. > > I'm not sure what's going on here, and I'm hoping someone can shed light on this issue so it can be resolved. > [dmesg snipped] I found some time today to get my new DP running. At first I couldn't recreate this problem no matter what I tried. Then I noticed you're running 9.1-prerelease and I was trying with -current. I built 9.1-RC3 and sure enough, with that I see the same problem. It actually appears to have nothing to do with sata, I can get it to happen on a really minimal system (usb, sata, sound, iic drivers all disabled). I boot via tftp, mount root over nfs, and then I can just cd /tmp (a memory disk) and use tftp to get a 10M file full of zeroes, and more times than not there are 32-byte chunks of non-zero values in it. It seems to require bulk network data to trigger the glitches; I never have any trouble launching apps or anything that does small intermittant network stuff, even with root using nfs. I can turn the problem off by changing the data cache from writeback to write-through. So all in all, it looks like a cacheline flush problem, but it doesn't appear to be the usual partial cacheline flush problems, because I instrumented the code to check for that, and no partial flushes are happening during the tftp operations that get corrupted data. It'll be a while before I can get back to this and start tracking down the point at which the problem went away in -current. If you want a quick workaround for now, the attached patch will set the data cache to writethrough (the performance hit isn't as bad as you'd think). -- Ian --=-U+0tiqhzPM3RGEvKkQUg Content-Disposition: inline; filename="arm_cache_writethrough.diff" Content-Type: text/x-patch; name="arm_cache_writethrough.diff"; charset="us-ascii" Content-Transfer-Encoding: 7bit diff -r df572d6d53cd sys/arm/arm/pmap.c --- sys/arm/arm/pmap.c Thu Nov 22 16:46:06 2012 -0700 +++ sys/arm/arm/pmap.c Thu Nov 22 20:54:49 2012 -0700 @@ -481,6 +481,16 @@ pmap_pte_init_generic(void) pte_l2_s_cache_mode_pt = L2_C; } +#if 1 // Change data cache from writeback to writethrough + pte_l1_s_cache_mode = L1_S_C; + pte_l2_l_cache_mode = L2_C; + pte_l2_s_cache_mode = L2_C; + + pte_l1_s_cache_mode_pt = L1_S_C; + pte_l2_l_cache_mode_pt = L2_C; + pte_l2_s_cache_mode_pt = L2_C; +#endif + pte_l2_s_prot_u = L2_S_PROT_U_generic; pte_l2_s_prot_w = L2_S_PROT_W_generic; pte_l2_s_prot_mask = L2_S_PROT_MASK_generic; --=-U+0tiqhzPM3RGEvKkQUg-- From owner-freebsd-arm@FreeBSD.ORG Fri Nov 23 07:58:05 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 9F15920D; Fri, 23 Nov 2012 07:58:05 +0000 (UTC) (envelope-from giovanni.trematerra@gmail.com) Received: from mail-qc0-f182.google.com (mail-qc0-f182.google.com [209.85.216.182]) by mx1.freebsd.org (Postfix) with ESMTP id 373B48FC16; Fri, 23 Nov 2012 07:58:04 +0000 (UTC) Received: by mail-qc0-f182.google.com with SMTP id k19so7897375qcs.13 for ; Thu, 22 Nov 2012 23:58:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=smumi4TZC+LzhRl4rJd9IhzD2j1dGqrkvxy4OEKAsTQ=; b=TjwWd8qL3TNBxIJtPwSVeWTAhH4rsgh71nzzxkrEf5oLKyQDLdSzCAGshsWPJVAWf9 I7VY3ZTUNc1PvAO4BoqL+hNledv3+B3kpEJmUIcWLxI5v2W/JFHt6nj+4oE/Q+u4SoPk KYOlqtFnHpSVQDub2Gh8d+qGxZWUZ3ONuoUckkGPqpYYhYFO32qlFMwmmpARjC4Fkgdo DUmmeffhKzb7i0Ul+tFYy6edJ4D/nt9w/rpQHh185CIE4tnr1nWgRpI4BB4VDoZuUw/8 SlSYuTKR4FHwlb1D2ocDMe1RvMIw+NXrD8TQqY/9CfZRAoE3RWZABF6H771VytaNc2zb gaRg== MIME-Version: 1.0 Received: by 10.224.116.12 with SMTP id k12mr3543329qaq.47.1353657484228; Thu, 22 Nov 2012 23:58:04 -0800 (PST) Sender: giovanni.trematerra@gmail.com Received: by 10.229.117.1 with HTTP; Thu, 22 Nov 2012 23:58:04 -0800 (PST) In-Reply-To: <94A3C1F1-0138-4D11-85BC-9E988AEF2E9F@bsdimp.com> References: <50AA4E87.3000505@semihalf.com> <50ACE2B4.8010904@semihalf.com> <50AE3C0F.20809@semihalf.com> <94A3C1F1-0138-4D11-85BC-9E988AEF2E9F@bsdimp.com> Date: Fri, 23 Nov 2012 08:58:04 +0100 X-Google-Sender-Auth: 4kHFyo74AR4bAsxobtuzOAa4IH0 Message-ID: Subject: Re: ARM/SMP, Some patches for review. From: Giovanni Trematerra To: Warner Losh Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Cc: freebsd-arm@freebsd.org, cognet@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Nov 2012 07:58:05 -0000 On Thu, Nov 22, 2012 at 5:46 PM, Warner Losh wrote: > > On Nov 22, 2012, at 7:51 AM, =C5=81ukasz P=C5=82achno wrote: > >> On 21.11.2012 17:00, Giovanni Trematerra wrote: >>> On Wed, Nov 21, 2012 at 3:18 PM, =C5=81ukasz P=C5=82achno wrote: >>>> On 20.11.2012 00:08, Giovanni Trematerra wrote: >>>>> >>>>> On Mon, Nov 19, 2012 at 4:21 PM, =C5=81ukasz P=C5=82achno wrote: >>>>>> >>>>>> Hi, >>>>>> >>>>>> I would like to propose few changes for ARM specific code. >>>>>> Three attached patches for freebsd-current allows building SMP-safe = world >>>>>> for ARM targets and turns on TEX remap for ARMv6 and ARMv7 targets. >>>>>> >>>>>> More details inside patch files. >>>>>> >>>>>> Change introduced by "commit-2" removes armv7 targets (armv7 and pj4= b) >>>>>> from >>>>>> kernel.tramp. >>>>>> AFAIK this feature is not working properly for armv7 targets and is >>>>>> causing >>>>>> problem during compilation: >>>>>> - LOCORE is defined during kernel compilation but not defined duri= ng >>>>>> kernel.tramp compilation, so #include pmap.h causes build errors. >>>>>> >>>>>> I do not think adding hack like this: >>>>>> #ifndef LOCORE >>>>>> #define LOCORE >>>>>> #endif >>>>>> >>>>>> to allow building something that is already broken is a good idea, s= o I >>>>>> removed cpufunc_asm_pj4b.S and cpufunc_asm_armv7.S from Makefile.arm >>>>> >>>>> >>>>> In commit-2.txt >>>>> you should include style changes in sys/arm/arm/cpufunc_asm_armv7.S >>>>> into a different patch. >>>> >>>> >>>> fixed >>>> >>>> >>>>> >>>>> @@ -63,7 +64,6 @@ FILES_CPU_FUNC =3D $S/$M/$M/cpufunc_asm_arm7td= mi.S \ >>>>> $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ >>>>> $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_= ec.S >>>>> \ >>>>> $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ >>>>> - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S >>>>> >>>>> You left a trailing back slash but beside that you should clean up >>>>> sys/arm/arm/elf_trampoline.c >>>>> and not make kernel.tramp to build at all for armv7 cpus or you'll en= d >>>>> up with a linker error >>>>> during generation of the kernel.tramp. >>>>> >>>> >>>> Fixed, updated set of patches is attached. >>>> >>>> - TEX remap is supported only for armv6 (changed to avoid breaking ar= mv6 >>>> targets) >>>> - Fixed issues with build for pre-armv6 targets (tested with make tin= derbox >>>> TARGETS=3Darm >>>> >>> >>> 1_SMP_fixes.diff >>> You'll endup to get a panic for PandaBoard systems. >>> The arm11 functions don't handle the SMP case. >>> So I propose to merge the changes below or commit them first. >>> >>> Index: sys/arm/arm/cpufunc.c >>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>> --- sys/arm/arm/cpufunc.c (revision 243182) >>> +++ sys/arm/arm/cpufunc.c (working copy) >>> @@ -1079,18 +1079,18 @@ struct cpu_functions cortexa_cpufuncs =3D { >>> /* Other functions */ >>> >>> cpufunc_nullop, /* flush_prefetchbuf */ >>> - arm11_drain_writebuf, /* drain_writebuf */ >>> + armv7_drain_writebuf, /* drain_writebuf */ >>> cpufunc_nullop, /* flush_brnchtgt_C */ >>> (void *)cpufunc_nullop, /* flush_brnchtgt_E */ >>> >>> - arm11_sleep, /* sleep */ >>> + armv7_cpu_sleep, /* sleep */ >>> >>> /* Soft functions */ >>> >>> cpufunc_null_fixup, /* dataabt_fixup */ >>> cpufunc_null_fixup, /* prefetchabt_fixup */ >>> >>> - arm11_context_switch, /* context_switch */ >>> + armv7_context_switch, /* context_switch */ >>> >>> cortexa_setup /* cpu setup */ >>> }; >>> >> >> I agree, but with this change I included also: >> >> diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c >> index dd43c27..1d6f93f 100644 >> --- a/sys/arm/arm/cpufunc.c >> +++ b/sys/arm/arm/cpufunc.c >> @@ -1049,14 +1049,14 @@ struct cpu_functions cortexa_cpufuncs =3D { >> >> armv7_tlb_flushID, /* tlb_flushID */ >> armv7_tlb_flushID_SE, /* tlb_flushID_SE */ >> - arm11_tlb_flushI, /* tlb_flushI */ >> - arm11_tlb_flushI_SE, /* tlb_flushI_SE */ >> - arm11_tlb_flushD, /* tlb_flushD */ >> - arm11_tlb_flushD_SE, /* tlb_flushD_SE */ >> + armv7_tlb_flushID, /* tlb_flushI */ >> + armv7_tlb_flushID_SE, /* tlb_flushI_SE */ >> + armv7_tlb_flushID, /* tlb_flushD */ >> + armv7_tlb_flushID_SE, /* tlb_flushD_SE */ >> >> Changes merged into patch 1_SMP_fixes.diff >> >>> >>> 2_ARM_cleanup.diff >>> Changes to sys/arm/arm/machdep.c don't seem style changes and >>> they should live in a separate patch with a different motivation. >>> >>> I'm not sure changes in sys/arm/arm/locore.S are style ones. >> >> None of changes in this patch are related to style. In this patch I want= ed to improve code readability, not remove style conflicts. >> >>> >>> I think that things like this aren't so readable. >>> #if (ARM_ARCH_6 + ARM_ARCH_7A) !=3D 0 >>> >>> Instead of things like that wouldn't be better to define different >>> macros when the sum is zero or non zero and stick with the >>> #if defined/!defined thing? >>> >>> I mean in sys/arm/arm/cpuconf.h we could make something like this >>> >>> #if (ARM_ARCH_6 + ARM_ARCH_7A) !=3D 0 >>> #define ARM_ARCH_6_7A >>> #endif >> >> Changed to ARM_ARCH_6_7A >> >>> >>> 3_kernel_trampoline.diff >>> I think we should not make kernel_trampoline at all for the unsupported= CPUs. >>> I propose this change to Makefile.arm >>> >>> Index: sys/conf/Makefile.arm >>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>> --- sys/conf/Makefile.arm (revision 243182) >>> +++ sys/conf/Makefile.arm (working copy) >>> @@ -51,6 +51,7 @@ SYSTEM_LD_TAIL +=3D;sed s/" + SIZEOF_HEADERS"// ldsc >>> ${SYSTEM_LD_}; \ >>> ${OBJCOPY} -S -O binary ${FULLKERNEL}.noheader \ >>> ${KERNEL_KO}.bin; \ >>> + ${NM} ${FULLKERNEL}.noheader | sort > ${FULLKERNEL}.map= ; \ >>> rm ${FULLKERNEL}.noheader >>> >>> .if defined(MFS_IMAGE) >>> @@ -62,9 +63,11 @@ FILES_CPU_FUNC =3D $S/$M/$M/cpufunc_asm_arm7tdmi= .S \ >>> $S/$M/$M/cpufunc_asm_sa1.S $S/$M/$M/cpufunc_asm_arm10.S \ >>> $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ >>> $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.= S \ >>> $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ >>> - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S >>> + $S/$M/$M/cpufunc_asm_armv6.S >>> >>> +NO_TRAMP!=3D grep 'CPU_CORTEXA\|CPU_MV_PJ4B' opt_global.h || true ; ec= ho >>> + >>> +.if ${NO_TRAMP} =3D=3D "" >>> KERNEL_EXTRA=3Dtrampoline >>> KERNEL_EXTRA_INSTALL=3Dkernel.gz.tramp >>> trampoline: ${KERNEL_KO}.tramp >>> @@ -110,6 +113,7 @@ ${KERNEL_KO}.tramp: ${KERNEL_KO} $S/$M/$M/inckern. >>> ${KERNEL_KO}.gz.tramp.bin >>> rm ${KERNEL_KO}.tmp.gz ${KERNEL_KO}.tramp.noheader opt_kernname= .h \ >>> inflate-tramp.o tmphack.S >>> +.endif >>> >>> MKMODULESENV+=3D MACHINE=3D${MACHINE} >>> >> >> Change merged into commit 3. > > I really don't like this part of the change. The if is ok, but the grep = isn't. It should be in the kernel config file as an option. I can be in > std.XXX files easily. Well, I just mimicked what is done in sys/conf/kern.pre.mk # Are various things configured? DDB_ENABLED!=3D grep DDB opt_ddb.h || true ; echo DTR_ENABLED!=3D grep KDTRACE_FRAME opt_kdtrace.h || true ; echo HWPMC_ENABLED!=3D grep HWPMC opt_hwpmc_hooks.h || true ; echo I'm completely open to hear about the best way to accomplish that. Please could you be more specific on how I can test a kernel configuration = knob from a Makefile? Thank you -- Gianni From owner-freebsd-arm@FreeBSD.ORG Fri Nov 23 16:31:50 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 6D65E2C9 for ; Fri, 23 Nov 2012 16:31:50 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from mail-ie0-f182.google.com (mail-ie0-f182.google.com [209.85.223.182]) by mx1.freebsd.org (Postfix) with ESMTP id 192BE8FC0C for ; Fri, 23 Nov 2012 16:31:49 +0000 (UTC) Received: by mail-ie0-f182.google.com with SMTP id s9so9009179iec.13 for ; Fri, 23 Nov 2012 08:31:49 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:subject:mime-version:content-type:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to:x-mailer :x-gm-message-state; bh=umhbApdy7FYw5xjJYz3YKnN5Wv0sG3tKJ9b7Cu3Q1jU=; b=LPrLil0+R86NRcTlwjmrvlTD+2FlfJraSy2Q82jK7jRoFcCDW4NoR2H+yXMGYMaeCD M9tWzliizVetcoV20klvM0yZCPJ81kYoGAkBK4Jf7tHBh3AFkSNT5lDCdFf/8SHMyO+H FSz1/DtMgajJDALF9welWfCXzLP0cjKhCBW2NbDwy8XHflWTH5kjWxYr4b0zCrWYjGcE i6KfbQSigYc2uqKsqyS5WQuFrxlK0uSeRe7lH9w1Dr70gw3d992YGoIOmFqXKkUcRzSN miTF/cNkeoaTFiDlBef2C+V2sWG35P1EoevlGyy3xT4NZ8zEWCZV2gOF0SnKKm+wSqzj tcjg== Received: by 10.50.13.133 with SMTP id h5mr4064150igc.2.1353688309217; Fri, 23 Nov 2012 08:31:49 -0800 (PST) Received: from 53.imp.bsdimp.com (50-78-194-198-static.hfc.comcastbusiness.net. [50.78.194.198]) by mx.google.com with ESMTPS id yf6sm5030058igb.0.2012.11.23.08.31.45 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 23 Nov 2012 08:31:48 -0800 (PST) Sender: Warner Losh Subject: Re: ARM/SMP, Some patches for review. Mime-Version: 1.0 (Apple Message framework v1085) Content-Type: text/plain; charset=utf-8 From: Warner Losh In-Reply-To: Date: Fri, 23 Nov 2012 09:31:46 -0700 Content-Transfer-Encoding: quoted-printable Message-Id: <00FA807D-B984-4AE7-B174-FE0B09551627@bsdimp.com> References: <50AA4E87.3000505@semihalf.com> <50ACE2B4.8010904@semihalf.com> <50AE3C0F.20809@semihalf.com> <94A3C1F1-0138-4D11-85BC-9E988AEF2E9F@bsdimp.com> To: Giovanni Trematerra X-Mailer: Apple Mail (2.1085) X-Gm-Message-State: ALoCoQllPxvCJL04jAIcwVTnvKcadPW4NV3KO9iZflAaBqG5RSJHO1Qj+udwa6Pwhjx2ruOedgAB Cc: freebsd-arm@freebsd.org, cognet@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Nov 2012 16:31:50 -0000 On Nov 23, 2012, at 12:58 AM, Giovanni Trematerra wrote: > On Thu, Nov 22, 2012 at 5:46 PM, Warner Losh wrote: >>=20 >> On Nov 22, 2012, at 7:51 AM, =C5=81ukasz P=C5=82achno wrote: >>=20 >>> On 21.11.2012 17:00, Giovanni Trematerra wrote: >>>> On Wed, Nov 21, 2012 at 3:18 PM, =C5=81ukasz P=C5=82achno = wrote: >>>>> On 20.11.2012 00:08, Giovanni Trematerra wrote: >>>>>>=20 >>>>>> On Mon, Nov 19, 2012 at 4:21 PM, =C5=81ukasz P=C5=82achno = wrote: >>>>>>>=20 >>>>>>> Hi, >>>>>>>=20 >>>>>>> I would like to propose few changes for ARM specific code. >>>>>>> Three attached patches for freebsd-current allows building = SMP-safe world >>>>>>> for ARM targets and turns on TEX remap for ARMv6 and ARMv7 = targets. >>>>>>>=20 >>>>>>> More details inside patch files. >>>>>>>=20 >>>>>>> Change introduced by "commit-2" removes armv7 targets (armv7 and = pj4b) >>>>>>> from >>>>>>> kernel.tramp. >>>>>>> AFAIK this feature is not working properly for armv7 targets and = is >>>>>>> causing >>>>>>> problem during compilation: >>>>>>> - LOCORE is defined during kernel compilation but not defined = during >>>>>>> kernel.tramp compilation, so #include pmap.h causes build = errors. >>>>>>>=20 >>>>>>> I do not think adding hack like this: >>>>>>> #ifndef LOCORE >>>>>>> #define LOCORE >>>>>>> #endif >>>>>>>=20 >>>>>>> to allow building something that is already broken is a good = idea, so I >>>>>>> removed cpufunc_asm_pj4b.S and cpufunc_asm_armv7.S from = Makefile.arm >>>>>>=20 >>>>>>=20 >>>>>> In commit-2.txt >>>>>> you should include style changes in = sys/arm/arm/cpufunc_asm_armv7.S >>>>>> into a different patch. >>>>>=20 >>>>>=20 >>>>> fixed >>>>>=20 >>>>>=20 >>>>>>=20 >>>>>> @@ -63,7 +64,6 @@ FILES_CPU_FUNC =3D = $S/$M/$M/cpufunc_asm_arm7tdmi.S \ >>>>>> $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ >>>>>> $S/$M/$M/cpufunc_asm_xscale_c3.S = $S/$M/$M/cpufunc_asm_armv5_ec.S >>>>>> \ >>>>>> $S/$M/$M/cpufunc_asm_fa526.S = $S/$M/$M/cpufunc_asm_sheeva.S \ >>>>>> - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S >>>>>>=20 >>>>>> You left a trailing back slash but beside that you should clean = up >>>>>> sys/arm/arm/elf_trampoline.c >>>>>> and not make kernel.tramp to build at all for armv7 cpus or = you'll end >>>>>> up with a linker error >>>>>> during generation of the kernel.tramp. >>>>>>=20 >>>>>=20 >>>>> Fixed, updated set of patches is attached. >>>>>=20 >>>>> - TEX remap is supported only for armv6 (changed to avoid breaking = armv6 >>>>> targets) >>>>> - Fixed issues with build for pre-armv6 targets (tested with make = tinderbox >>>>> TARGETS=3Darm >>>>>=20 >>>>=20 >>>> 1_SMP_fixes.diff >>>> You'll endup to get a panic for PandaBoard systems. >>>> The arm11 functions don't handle the SMP case. >>>> So I propose to merge the changes below or commit them first. >>>>=20 >>>> Index: sys/arm/arm/cpufunc.c >>>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>>> --- sys/arm/arm/cpufunc.c (revision 243182) >>>> +++ sys/arm/arm/cpufunc.c (working copy) >>>> @@ -1079,18 +1079,18 @@ struct cpu_functions cortexa_cpufuncs =3D { >>>> /* Other functions */ >>>>=20 >>>> cpufunc_nullop, /* flush_prefetchbuf */ >>>> - arm11_drain_writebuf, /* drain_writebuf */ >>>> + armv7_drain_writebuf, /* drain_writebuf */ >>>> cpufunc_nullop, /* flush_brnchtgt_C */ >>>> (void *)cpufunc_nullop, /* flush_brnchtgt_E */ >>>>=20 >>>> - arm11_sleep, /* sleep */ >>>> + armv7_cpu_sleep, /* sleep */ >>>>=20 >>>> /* Soft functions */ >>>>=20 >>>> cpufunc_null_fixup, /* dataabt_fixup */ >>>> cpufunc_null_fixup, /* prefetchabt_fixup */ >>>>=20 >>>> - arm11_context_switch, /* context_switch */ >>>> + armv7_context_switch, /* context_switch */ >>>>=20 >>>> cortexa_setup /* cpu setup */ >>>> }; >>>>=20 >>>=20 >>> I agree, but with this change I included also: >>>=20 >>> diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c >>> index dd43c27..1d6f93f 100644 >>> --- a/sys/arm/arm/cpufunc.c >>> +++ b/sys/arm/arm/cpufunc.c >>> @@ -1049,14 +1049,14 @@ struct cpu_functions cortexa_cpufuncs =3D { >>>=20 >>> armv7_tlb_flushID, /* tlb_flushID */ >>> armv7_tlb_flushID_SE, /* tlb_flushID_SE */ >>> - arm11_tlb_flushI, /* tlb_flushI */ >>> - arm11_tlb_flushI_SE, /* tlb_flushI_SE */ >>> - arm11_tlb_flushD, /* tlb_flushD */ >>> - arm11_tlb_flushD_SE, /* tlb_flushD_SE */ >>> + armv7_tlb_flushID, /* tlb_flushI */ >>> + armv7_tlb_flushID_SE, /* tlb_flushI_SE */ >>> + armv7_tlb_flushID, /* tlb_flushD */ >>> + armv7_tlb_flushID_SE, /* tlb_flushD_SE */ >>>=20 >>> Changes merged into patch 1_SMP_fixes.diff >>>=20 >>>>=20 >>>> 2_ARM_cleanup.diff >>>> Changes to sys/arm/arm/machdep.c don't seem style changes and >>>> they should live in a separate patch with a different motivation. >>>>=20 >>>> I'm not sure changes in sys/arm/arm/locore.S are style ones. >>>=20 >>> None of changes in this patch are related to style. In this patch I = wanted to improve code readability, not remove style conflicts. >>>=20 >>>>=20 >>>> I think that things like this aren't so readable. >>>> #if (ARM_ARCH_6 + ARM_ARCH_7A) !=3D 0 >>>>=20 >>>> Instead of things like that wouldn't be better to define different >>>> macros when the sum is zero or non zero and stick with the >>>> #if defined/!defined thing? >>>>=20 >>>> I mean in sys/arm/arm/cpuconf.h we could make something like this >>>>=20 >>>> #if (ARM_ARCH_6 + ARM_ARCH_7A) !=3D 0 >>>> #define ARM_ARCH_6_7A >>>> #endif >>>=20 >>> Changed to ARM_ARCH_6_7A >>>=20 >>>>=20 >>>> 3_kernel_trampoline.diff >>>> I think we should not make kernel_trampoline at all for the = unsupported CPUs. >>>> I propose this change to Makefile.arm >>>>=20 >>>> Index: sys/conf/Makefile.arm >>>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>>> --- sys/conf/Makefile.arm (revision 243182) >>>> +++ sys/conf/Makefile.arm (working copy) >>>> @@ -51,6 +51,7 @@ SYSTEM_LD_TAIL +=3D;sed s/" + SIZEOF_HEADERS"// = ldsc >>>> ${SYSTEM_LD_}; \ >>>> ${OBJCOPY} -S -O binary ${FULLKERNEL}.noheader \ >>>> ${KERNEL_KO}.bin; \ >>>> + ${NM} ${FULLKERNEL}.noheader | sort > = ${FULLKERNEL}.map; \ >>>> rm ${FULLKERNEL}.noheader >>>>=20 >>>> .if defined(MFS_IMAGE) >>>> @@ -62,9 +63,11 @@ FILES_CPU_FUNC =3D = $S/$M/$M/cpufunc_asm_arm7tdmi.S \ >>>> $S/$M/$M/cpufunc_asm_sa1.S $S/$M/$M/cpufunc_asm_arm10.S \ >>>> $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ >>>> $S/$M/$M/cpufunc_asm_xscale_c3.S = $S/$M/$M/cpufunc_asm_armv5_ec.S \ >>>> $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ >>>> - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S >>>> + $S/$M/$M/cpufunc_asm_armv6.S >>>>=20 >>>> +NO_TRAMP!=3D grep 'CPU_CORTEXA\|CPU_MV_PJ4B' opt_global.h || true = ; echo >>>> + >>>> +.if ${NO_TRAMP} =3D=3D "" >>>> KERNEL_EXTRA=3Dtrampoline >>>> KERNEL_EXTRA_INSTALL=3Dkernel.gz.tramp >>>> trampoline: ${KERNEL_KO}.tramp >>>> @@ -110,6 +113,7 @@ ${KERNEL_KO}.tramp: ${KERNEL_KO} = $S/$M/$M/inckern. >>>> ${KERNEL_KO}.gz.tramp.bin >>>> rm ${KERNEL_KO}.tmp.gz ${KERNEL_KO}.tramp.noheader = opt_kernname.h \ >>>> inflate-tramp.o tmphack.S >>>> +.endif >>>>=20 >>>> MKMODULESENV+=3D MACHINE=3D${MACHINE} >>>>=20 >>>=20 >>> Change merged into commit 3. >>=20 >> I really don't like this part of the change. The if is ok, but the = grep isn't. It should be in the kernel config file as an option. I can = be in >> std.XXX files easily. >=20 >=20 > Well, I just mimicked what is done in sys/conf/kern.pre.mk >=20 > # Are various things configured? > DDB_ENABLED!=3D grep DDB opt_ddb.h || true ; echo > DTR_ENABLED!=3D grep KDTRACE_FRAME opt_kdtrace.h || true ; echo > HWPMC_ENABLED!=3D grep HWPMC opt_hwpmc_hooks.h || true ; echo >=20 > I'm completely open to hear about the best way to accomplish that. > Please could you be more specific on how I can test a kernel = configuration knob > from a Makefile? Those really shouldn't be there either. At least they are reliable. The = grepping for one of many options for the CPU is much more fragile. makeoptions in the kernel config files is the proper way to do that sort = of thing you want to disable the TRAMP code. Warner= From owner-freebsd-arm@FreeBSD.ORG Fri Nov 23 16:40:48 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 6950D579 for ; Fri, 23 Nov 2012 16:40:48 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from mail-ia0-f182.google.com (mail-ia0-f182.google.com [209.85.210.182]) by mx1.freebsd.org (Postfix) with ESMTP id 1F4B68FC1A for ; Fri, 23 Nov 2012 16:40:47 +0000 (UTC) Received: by mail-ia0-f182.google.com with SMTP id x2so8280099iad.13 for ; Fri, 23 Nov 2012 08:40:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:subject:mime-version:content-type:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to:x-mailer :x-gm-message-state; bh=lxZFHJVuqJ0drlfMAotaQVJpWknWDclxoBa9nUZjy7k=; b=TmPVsna2fb1DHhT46Ph+MkvxajRdC2raTIjUmFss3DDTB9kBw8BeE2pQoR0GRXWL2v ifxs4qq0t1TOifpB+FBSTrXa2j5xKCeqxEOlbvYg4r1qa3pr7NwBsJ5hiFQKX8py8IKI IUOuviOzt58APJdUxSn3TeYFr/TtFBrAYEXZxlyDDRUQ0dTePRPnHFdd/+ZFhBxc/Vmc P5QFL/0evBXYYgUdFesyQabH0g6IO2ppGCUWnDavwQ2jlxiJ7yCjQenriJHRNQDk2udk mF3+Ht86BpeEYphncXcrzoTksT+9PLql5SRFD+vzBmwNb/vL79YN5mCyQ9Obc451Xvv4 wLVg== Received: by 10.50.13.138 with SMTP id h10mr6699727igc.55.1353688847506; Fri, 23 Nov 2012 08:40:47 -0800 (PST) Received: from 53.imp.bsdimp.com (50-78-194-198-static.hfc.comcastbusiness.net. [50.78.194.198]) by mx.google.com with ESMTPS id s3sm5020403igb.14.2012.11.23.08.40.43 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 23 Nov 2012 08:40:46 -0800 (PST) Sender: Warner Losh Subject: Re: ARM/SMP, Some patches for review. Mime-Version: 1.0 (Apple Message framework v1085) Content-Type: text/plain; charset=utf-8 From: Warner Losh In-Reply-To: Date: Fri, 23 Nov 2012 09:40:42 -0700 Content-Transfer-Encoding: quoted-printable Message-Id: References: <50AA4E87.3000505@semihalf.com> <50ACE2B4.8010904@semihalf.com> <50AE3C0F.20809@semihalf.com> <94A3C1F1-0138-4D11-85BC-9E988AEF2E9F@bsdimp.com> To: Giovanni Trematerra X-Mailer: Apple Mail (2.1085) X-Gm-Message-State: ALoCoQmD934mNtrLOxGsq5bJY61ARoZ6RLEIZRZkgwLMsPCIxKAWrWlDskSQBYbnG1WpXxUTtu0b Cc: freebsd-arm@freebsd.org, cognet@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Nov 2012 16:40:48 -0000 On Nov 23, 2012, at 12:58 AM, Giovanni Trematerra wrote: > On Thu, Nov 22, 2012 at 5:46 PM, Warner Losh wrote: >>=20 >> On Nov 22, 2012, at 7:51 AM, =C5=81ukasz P=C5=82achno wrote: >>=20 >>> On 21.11.2012 17:00, Giovanni Trematerra wrote: >>>> On Wed, Nov 21, 2012 at 3:18 PM, =C5=81ukasz P=C5=82achno = wrote: >>>>> On 20.11.2012 00:08, Giovanni Trematerra wrote: >>>>>>=20 >>>>>> On Mon, Nov 19, 2012 at 4:21 PM, =C5=81ukasz P=C5=82achno = wrote: >>>>>>>=20 >>>>>>> Hi, >>>>>>>=20 >>>>>>> I would like to propose few changes for ARM specific code. >>>>>>> Three attached patches for freebsd-current allows building = SMP-safe world >>>>>>> for ARM targets and turns on TEX remap for ARMv6 and ARMv7 = targets. >>>>>>>=20 >>>>>>> More details inside patch files. >>>>>>>=20 >>>>>>> Change introduced by "commit-2" removes armv7 targets (armv7 and = pj4b) >>>>>>> from >>>>>>> kernel.tramp. >>>>>>> AFAIK this feature is not working properly for armv7 targets and = is >>>>>>> causing >>>>>>> problem during compilation: >>>>>>> - LOCORE is defined during kernel compilation but not defined = during >>>>>>> kernel.tramp compilation, so #include pmap.h causes build = errors. >>>>>>>=20 >>>>>>> I do not think adding hack like this: >>>>>>> #ifndef LOCORE >>>>>>> #define LOCORE >>>>>>> #endif >>>>>>>=20 >>>>>>> to allow building something that is already broken is a good = idea, so I >>>>>>> removed cpufunc_asm_pj4b.S and cpufunc_asm_armv7.S from = Makefile.arm >>>>>>=20 >>>>>>=20 >>>>>> In commit-2.txt >>>>>> you should include style changes in = sys/arm/arm/cpufunc_asm_armv7.S >>>>>> into a different patch. >>>>>=20 >>>>>=20 >>>>> fixed >>>>>=20 >>>>>=20 >>>>>>=20 >>>>>> @@ -63,7 +64,6 @@ FILES_CPU_FUNC =3D = $S/$M/$M/cpufunc_asm_arm7tdmi.S \ >>>>>> $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ >>>>>> $S/$M/$M/cpufunc_asm_xscale_c3.S = $S/$M/$M/cpufunc_asm_armv5_ec.S >>>>>> \ >>>>>> $S/$M/$M/cpufunc_asm_fa526.S = $S/$M/$M/cpufunc_asm_sheeva.S \ >>>>>> - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S >>>>>>=20 >>>>>> You left a trailing back slash but beside that you should clean = up >>>>>> sys/arm/arm/elf_trampoline.c >>>>>> and not make kernel.tramp to build at all for armv7 cpus or = you'll end >>>>>> up with a linker error >>>>>> during generation of the kernel.tramp. >>>>>>=20 >>>>>=20 >>>>> Fixed, updated set of patches is attached. >>>>>=20 >>>>> - TEX remap is supported only for armv6 (changed to avoid breaking = armv6 >>>>> targets) >>>>> - Fixed issues with build for pre-armv6 targets (tested with make = tinderbox >>>>> TARGETS=3Darm >>>>>=20 >>>>=20 >>>> 1_SMP_fixes.diff >>>> You'll endup to get a panic for PandaBoard systems. >>>> The arm11 functions don't handle the SMP case. >>>> So I propose to merge the changes below or commit them first. >>>>=20 >>>> Index: sys/arm/arm/cpufunc.c >>>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>>> --- sys/arm/arm/cpufunc.c (revision 243182) >>>> +++ sys/arm/arm/cpufunc.c (working copy) >>>> @@ -1079,18 +1079,18 @@ struct cpu_functions cortexa_cpufuncs =3D { >>>> /* Other functions */ >>>>=20 >>>> cpufunc_nullop, /* flush_prefetchbuf */ >>>> - arm11_drain_writebuf, /* drain_writebuf */ >>>> + armv7_drain_writebuf, /* drain_writebuf */ >>>> cpufunc_nullop, /* flush_brnchtgt_C */ >>>> (void *)cpufunc_nullop, /* flush_brnchtgt_E */ >>>>=20 >>>> - arm11_sleep, /* sleep */ >>>> + armv7_cpu_sleep, /* sleep */ >>>>=20 >>>> /* Soft functions */ >>>>=20 >>>> cpufunc_null_fixup, /* dataabt_fixup */ >>>> cpufunc_null_fixup, /* prefetchabt_fixup */ >>>>=20 >>>> - arm11_context_switch, /* context_switch */ >>>> + armv7_context_switch, /* context_switch */ >>>>=20 >>>> cortexa_setup /* cpu setup */ >>>> }; >>>>=20 >>>=20 >>> I agree, but with this change I included also: >>>=20 >>> diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c >>> index dd43c27..1d6f93f 100644 >>> --- a/sys/arm/arm/cpufunc.c >>> +++ b/sys/arm/arm/cpufunc.c >>> @@ -1049,14 +1049,14 @@ struct cpu_functions cortexa_cpufuncs =3D { >>>=20 >>> armv7_tlb_flushID, /* tlb_flushID */ >>> armv7_tlb_flushID_SE, /* tlb_flushID_SE */ >>> - arm11_tlb_flushI, /* tlb_flushI */ >>> - arm11_tlb_flushI_SE, /* tlb_flushI_SE */ >>> - arm11_tlb_flushD, /* tlb_flushD */ >>> - arm11_tlb_flushD_SE, /* tlb_flushD_SE */ >>> + armv7_tlb_flushID, /* tlb_flushI */ >>> + armv7_tlb_flushID_SE, /* tlb_flushI_SE */ >>> + armv7_tlb_flushID, /* tlb_flushD */ >>> + armv7_tlb_flushID_SE, /* tlb_flushD_SE */ >>>=20 >>> Changes merged into patch 1_SMP_fixes.diff >>>=20 >>>>=20 >>>> 2_ARM_cleanup.diff >>>> Changes to sys/arm/arm/machdep.c don't seem style changes and >>>> they should live in a separate patch with a different motivation. >>>>=20 >>>> I'm not sure changes in sys/arm/arm/locore.S are style ones. >>>=20 >>> None of changes in this patch are related to style. In this patch I = wanted to improve code readability, not remove style conflicts. >>>=20 >>>>=20 >>>> I think that things like this aren't so readable. >>>> #if (ARM_ARCH_6 + ARM_ARCH_7A) !=3D 0 >>>>=20 >>>> Instead of things like that wouldn't be better to define different >>>> macros when the sum is zero or non zero and stick with the >>>> #if defined/!defined thing? >>>>=20 >>>> I mean in sys/arm/arm/cpuconf.h we could make something like this >>>>=20 >>>> #if (ARM_ARCH_6 + ARM_ARCH_7A) !=3D 0 >>>> #define ARM_ARCH_6_7A >>>> #endif >>>=20 >>> Changed to ARM_ARCH_6_7A >>>=20 >>>>=20 >>>> 3_kernel_trampoline.diff >>>> I think we should not make kernel_trampoline at all for the = unsupported CPUs. >>>> I propose this change to Makefile.arm >>>>=20 >>>> Index: sys/conf/Makefile.arm >>>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>>> --- sys/conf/Makefile.arm (revision 243182) >>>> +++ sys/conf/Makefile.arm (working copy) >>>> @@ -51,6 +51,7 @@ SYSTEM_LD_TAIL +=3D;sed s/" + SIZEOF_HEADERS"// = ldsc >>>> ${SYSTEM_LD_}; \ >>>> ${OBJCOPY} -S -O binary ${FULLKERNEL}.noheader \ >>>> ${KERNEL_KO}.bin; \ >>>> + ${NM} ${FULLKERNEL}.noheader | sort > = ${FULLKERNEL}.map; \ >>>> rm ${FULLKERNEL}.noheader >>>>=20 >>>> .if defined(MFS_IMAGE) >>>> @@ -62,9 +63,11 @@ FILES_CPU_FUNC =3D = $S/$M/$M/cpufunc_asm_arm7tdmi.S \ >>>> $S/$M/$M/cpufunc_asm_sa1.S $S/$M/$M/cpufunc_asm_arm10.S \ >>>> $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \ >>>> $S/$M/$M/cpufunc_asm_xscale_c3.S = $S/$M/$M/cpufunc_asm_armv5_ec.S \ >>>> $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \ >>>> - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S >>>> + $S/$M/$M/cpufunc_asm_armv6.S >>>>=20 >>>> +NO_TRAMP!=3D grep 'CPU_CORTEXA\|CPU_MV_PJ4B' opt_global.h || true = ; echo >>>> + >>>> +.if ${NO_TRAMP} =3D=3D "" >>>> KERNEL_EXTRA=3Dtrampoline >>>> KERNEL_EXTRA_INSTALL=3Dkernel.gz.tramp >>>> trampoline: ${KERNEL_KO}.tramp >>>> @@ -110,6 +113,7 @@ ${KERNEL_KO}.tramp: ${KERNEL_KO} = $S/$M/$M/inckern. >>>> ${KERNEL_KO}.gz.tramp.bin >>>> rm ${KERNEL_KO}.tmp.gz ${KERNEL_KO}.tramp.noheader = opt_kernname.h \ >>>> inflate-tramp.o tmphack.S >>>> +.endif >>>>=20 >>>> MKMODULESENV+=3D MACHINE=3D${MACHINE} >>>>=20 >>>=20 >>> Change merged into commit 3. >>=20 >> I really don't like this part of the change. The if is ok, but the = grep isn't. It should be in the kernel config file as an option. I can = be in >> std.XXX files easily. >=20 >=20 > Well, I just mimicked what is done in sys/conf/kern.pre.mk >=20 > # Are various things configured? > DDB_ENABLED!=3D grep DDB opt_ddb.h || true ; echo > DTR_ENABLED!=3D grep KDTRACE_FRAME opt_kdtrace.h || true ; echo > HWPMC_ENABLED!=3D grep HWPMC opt_hwpmc_hooks.h || true ; echo >=20 > I'm completely open to hear about the best way to accomplish that. > Please could you be more specific on how I can test a kernel = configuration knob > from a Makefile? Furthermore these items are used exclusively to change the compiler args = only (except the weird DDB_ENABLED for clean files in the arm makefile = that I see absolutely no reason to be there). There should be a better = way of doing things, and I'll investigate it. However, I sometimes = think we need to revamp all the building substantially, and not just add = hacks to config. There have often been times that I wanted to disable building these for = my own reasons not related to what CPU I'm on. Warner= From owner-freebsd-arm@FreeBSD.ORG Fri Nov 23 16:48:55 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 5BD3A6E9; Fri, 23 Nov 2012 16:48:55 +0000 (UTC) (envelope-from mlfbsd@kanar.ci0.org) Received: from kanar.ci0.org (unknown [IPv6:2a01:e0b:1:150:ca0a:a9ff:fef1:a4c9]) by mx1.freebsd.org (Postfix) with ESMTP id DC9688FC15; Fri, 23 Nov 2012 16:48:54 +0000 (UTC) Received: from kanar.ci0.org (pluxor@localhost [127.0.0.1]) by kanar.ci0.org (8.14.5/8.14.5) with ESMTP id qANGm52h018842; Fri, 23 Nov 2012 17:48:05 +0100 (CET) (envelope-from mlfbsd@kanar.ci0.org) Received: (from mlfbsd@localhost) by kanar.ci0.org (8.14.5/8.14.5/Submit) id qANGm5cY018841; Fri, 23 Nov 2012 17:48:05 +0100 (CET) (envelope-from mlfbsd) Date: Fri, 23 Nov 2012 17:48:05 +0100 From: Olivier Houchard To: Warner Losh Subject: Re: ARM/SMP, Some patches for review. Message-ID: <20121123164805.GA18800@ci0.org> References: <50AA4E87.3000505@semihalf.com> <50ACE2B4.8010904@semihalf.com> <50AE3C0F.20809@semihalf.com> <94A3C1F1-0138-4D11-85BC-9E988AEF2E9F@bsdimp.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.3i Cc: freebsd-arm@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Nov 2012 16:48:55 -0000 On Fri, Nov 23, 2012 at 09:40:42AM -0700, Warner Losh wrote: > Furthermore these items are used exclusively to change the compiler args only (except the weird DDB_ENABLED for clean files in the arm makefile that I see absolutely no reason to be there). There should be a better way of doing things, and I'll investigate it. However, I sometimes think we need to revamp all the building substantially, and not just add hacks to config. > > There have often been times that I wanted to disable building these for my own reasons not related to what CPU I'm on. > Maybe it's time to make it a separate target again ? I guess now that we have proper bootloaders it will get less and less useful. Regards, Olivier From owner-freebsd-arm@FreeBSD.ORG Fri Nov 23 16:53:23 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id C2AC18B4 for ; Fri, 23 Nov 2012 16:53:23 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from mail-ie0-f182.google.com (mail-ie0-f182.google.com [209.85.223.182]) by mx1.freebsd.org (Postfix) with ESMTP id 7640F8FC18 for ; Fri, 23 Nov 2012 16:53:23 +0000 (UTC) Received: by mail-ie0-f182.google.com with SMTP id s9so9045945iec.13 for ; Fri, 23 Nov 2012 08:53:22 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:subject:mime-version:content-type:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to:x-mailer :x-gm-message-state; bh=OabXEcrUstwggbke17BzOxdGmyWXX5x1jPeYDt11F3g=; b=hJJQc1pilWTRfiTzhi6F5KlVKLNuACfntp3hxgWlarvpDWvB8C+KSYEV8/nPRhNZju uz0xhnMaQiH/HhMtqISY7fl+SeKzdCf+h8FVyWJA9B7KMumtEjXF8AJv17AnFpZgHjPV C7ui8efzmjhL51cvdlFSSJHEJhsDVIQMzXKaeQF2d1LOTWfCr1j52YlMp8qtbG5DcxM6 g7Vn2mlA7lwoEvxwMRVz7EiR6sbO73OmUewxiHMYGTlvFgwBi+47yKMCzQlHlYCbIrWR jCg2fXJDzA/5fdIP0dt6YhOPjxxMzhOmjt/gqDwASYXUEkDryHMf7xJQvr3L8ZcyGjDc a1zQ== Received: by 10.50.33.138 with SMTP id r10mr4160049igi.6.1353689602630; Fri, 23 Nov 2012 08:53:22 -0800 (PST) Received: from 53.imp.bsdimp.com (50-78-194-198-static.hfc.comcastbusiness.net. [50.78.194.198]) by mx.google.com with ESMTPS id hg2sm4616370igc.3.2012.11.23.08.53.18 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 23 Nov 2012 08:53:20 -0800 (PST) Sender: Warner Losh Subject: Re: ARM/SMP, Some patches for review. Mime-Version: 1.0 (Apple Message framework v1085) Content-Type: text/plain; charset=us-ascii From: Warner Losh In-Reply-To: <20121123164805.GA18800@ci0.org> Date: Fri, 23 Nov 2012 09:53:17 -0700 Content-Transfer-Encoding: quoted-printable Message-Id: References: <50AA4E87.3000505@semihalf.com> <50ACE2B4.8010904@semihalf.com> <50AE3C0F.20809@semihalf.com> <94A3C1F1-0138-4D11-85BC-9E988AEF2E9F@bsdimp.com> <20121123164805.GA18800@ci0.org> To: Olivier Houchard X-Mailer: Apple Mail (2.1085) X-Gm-Message-State: ALoCoQn43nrP7ZODiIx0XOhSkimNMWISMZfsgDlXmSN8GjyvexC1IlVL2Ilc/L7HwirBeUKcHtqx Cc: freebsd-arm@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Nov 2012 16:53:23 -0000 On Nov 23, 2012, at 9:48 AM, Olivier Houchard wrote: > On Fri, Nov 23, 2012 at 09:40:42AM -0700, Warner Losh wrote: >> Furthermore these items are used exclusively to change the compiler = args only (except the weird DDB_ENABLED for clean files in the arm = makefile that I see absolutely no reason to be there). There should be = a better way of doing things, and I'll investigate it. However, I = sometimes think we need to revamp all the building substantially, and = not just add hacks to config. >>=20 >> There have often been times that I wanted to disable building these = for my own reasons not related to what CPU I'm on. >>=20 >=20 > Maybe it's time to make it a separate target again ?=20 > I guess now that we have proper bootloaders it will get less and less = useful. I think that you may be right. I'll work up a couple of patches and = post them here for review. Warner From owner-freebsd-arm@FreeBSD.ORG Fri Nov 23 21:29:43 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id D61CA683; Fri, 23 Nov 2012 21:29:43 +0000 (UTC) (envelope-from garmitage@swin.edu.au) Received: from gpo2.cc.swin.edu.au (gpo2.cc.swin.edu.au [136.186.1.31]) by mx1.freebsd.org (Postfix) with ESMTP id 6C2388FC19; Fri, 23 Nov 2012 21:29:42 +0000 (UTC) Received: from [136.186.229.44] (garmitage3.caia.swin.edu.au [136.186.229.44]) by gpo2.cc.swin.edu.au (8.14.3/8.14.3) with ESMTP id qANLTf5x003083 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sat, 24 Nov 2012 08:29:41 +1100 Message-ID: <50AFEAC5.6040607@swin.edu.au> Date: Sat, 24 Nov 2012 08:29:41 +1100 From: grenville armitage User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:7.0.1) Gecko/20111003 Thunderbird/7.0.1 MIME-Version: 1.0 To: freebsd-emulation@freebsd.org, freebsd-arm@freebsd.org Subject: FreeBSD-CURRENT on Qemu-emulated Gumstix Verdex? Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Nov 2012 21:29:44 -0000 All, Apologies if I have the wrong lists, feel free to redirect me. I recently decided to try getting an arm build of 10.0-CURRENT (r243319) (TARGET=arm KERNCONF=GUMSTIX-QEMU) running inside a Qemu-emulated Gumstix Verdex board, using qemu-devel (1.1.1) as the emulator. Short version: I fire up qemu-system-arm with "-m 768" to make sure there's enough virtual RAM. u-boot reports the emulated Verdex board as having 256MB of DRAM (I believe this limit is imposed by u-boot). But when control passes to FreeBSD the kernel prints the usual copyright messages, detects the CPU type ("PXA27x step C-0 (XScale core)"), auto-detects 512MB of real memory rather than 256MB and promptly panics (with "panic: vm_page_insert: page already inserted"). The problem appears to be FreeBSD auto-detecting twice the emulated available RAM. Does this ring any bells with anyone? My google-fu has so far failed me. (I've been contemplating trying this for awhile, since noticing sys/arm/conf/GUMSTIX-QEMU was added to head earlier this year. Admittedly GUMSTIX-QEMU relies on GUMSTIX, which notes it is for the Basix and Connex boards. So I recognise that the answer when emulating Verdex boards might simply be "don't do that".) FWIW, this is a side project to get an emulated ARM environment running on my amd64 box for building ARM Ports. I've also tried booting the same kernel using Qemu's emulation of the Gumstix Connex board -- this does seem to work, but the emulated 64MB RAM is too tight. (http://matrossi.blogspot.com.au/2011/09/freebsd-arm-on-qemu-in-virtualbox.html was my early motivation for doing this.) FWIW#2, the actual console output during a failed boot: ----------------------------------------------- % qemu-system-arm -M verdex -m 768 -pflash flash6-moduboot -net nic -net tap -nographic pxa2xx_clkpwr_write: CPU frequency change attempt U-Boot 1.2.0 (May 10 2008 - 21:22:03) - PXA270@600 MHz - 1604 *** Welcome to Gumstix *** DRAM: 256 MB Flash: 32 MB Using default environment Hit any key to stop autoboot: 0 Instruction Cache is ON Copying kernel to 0xa2000000 from 0x01f00000 (length 0x00100000)...done ## Booting image at a2000000 ... Bad Magic Number GUM> bootelf 40000 -v bootelf 40000 -v Usage: bootelf - Boot from an ELF image in memory GUM> GUM> bootelf 40000 bootelf 40000 Loading .text @ 0xa0200054 (14400 bytes) Loading .rodata @ 0xa0203894 (356 bytes) Loading .rodata.str1.4 @ 0xa02039f8 (48 bytes) Loading .data @ 0xa0204a28 (28 bytes) Loading .real_kernel @ 0xa0204a44 (1565298 bytes) Clearing .bss @ 0xa0382cb8 (34080 bytes) ## Starting application at 0xa0200054 ... KDB: debugger backends: ddb KDB: current backend: ddb Copyright (c) 1992-2012 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights reserved. FreeBSD is a registered trademark of The FreeBSD Foundation. FreeBSD 10.0-CURRENT #4 r243319M: Fri Nov 23 13:34:32 EST 2012 root@nsk330-builder:/usr/obj/arm.arm/usr/wr1403nd-dev/head/src/sys/GUMSTIX-QEMU arm CPU: PXA27x step C-0 (XScale core) Little-endian DC enabled IC enabled WB enabled LABT branch prediction enabled 16KB/32B 64-way instruction cache 16KB/32B 64-way write-back-locking-A data cache real memory = 536870912 (512 MB) panic: vm_page_insert: page already inserted KDB: enter: panic ----------------------------------------------- cheers, gja From owner-freebsd-arm@FreeBSD.ORG Sat Nov 24 04:20:49 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id C03097ED; Sat, 24 Nov 2012 04:20:49 +0000 (UTC) (envelope-from gonzo@id.bluezbox.com) Received: from id.bluezbox.com (id.bluezbox.com [88.198.91.248]) by mx1.freebsd.org (Postfix) with ESMTP id 4F7308FC12; Sat, 24 Nov 2012 04:20:48 +0000 (UTC) Received: from [88.198.91.248] (helo=[IPv6:::1]) by id.bluezbox.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.77 (FreeBSD)) (envelope-from ) id 1Tc7ET-0009ku-0O; Fri, 23 Nov 2012 20:20:46 -0800 Message-ID: <50B04B1A.8090907@bluezbox.com> Date: Fri, 23 Nov 2012 20:20:42 -0800 From: Oleksandr Tymoshenko User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:16.0) Gecko/20121026 Thunderbird/16.0.2 MIME-Version: 1.0 To: grenville armitage Subject: Re: FreeBSD-CURRENT on Qemu-emulated Gumstix Verdex? References: <50AFEAC5.6040607@swin.edu.au> In-Reply-To: <50AFEAC5.6040607@swin.edu.au> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Sender: gonzo@id.bluezbox.com X-Spam-Level: -- X-Spam-Report: Spam detection software, running on the system "id.bluezbox.com", has identified this incoming email as possible spam. The original message has been attached to this so you can view it (if it isn't spam) or label similar future email. If you have any questions, see The administrator of that system for details. Content preview: On 11/23/2012 1:29 PM, grenville armitage wrote: > All, > > Apologies if I have the wrong lists, feel free to redirect me. > > I recently decided to try getting an arm build of 10.0-CURRENT > (r243319) (TARGET=arm KERNCONF=GUMSTIX-QEMU) running inside a > Qemu-emulated Gumstix Verdex board, using qemu-devel (1.1.1) as the > emulator. > > Short version: I fire up qemu-system-arm with "-m 768" to make sure > there's enough virtual RAM. u-boot reports the emulated Verdex board > as having 256MB of DRAM (I believe this limit is imposed by u-boot). > But when control passes to FreeBSD the kernel prints the usual > copyright messages, detects the CPU type ("PXA27x step C-0 (XScale > core)"), auto-detects 512MB of real memory rather than 256MB and > promptly panics (with "panic: vm_page_insert: page already inserted"). > > The problem appears to be FreeBSD auto-detecting twice the emulated > available RAM. Does this ring any bells with anyone? My google-fu has > so far failed me. > > (I've been contemplating trying this for awhile, since noticing > sys/arm/conf/GUMSTIX-QEMU was added to head earlier this year. > Admittedly GUMSTIX-QEMU relies on GUMSTIX, which notes it is for the > Basix and Connex boards. So I recognise that the answer when emulating > Verdex boards might simply be "don't do that".) > > FWIW, this is a side project to get an emulated ARM environment > running on my amd64 box for building ARM Ports. I've also tried > booting the same kernel using Qemu's emulation of the Gumstix Connex > board -- this does seem to work, but the emulated 64MB RAM is too > tight. > (http://matrossi.blogspot.com.au/2011/09/freebsd-arm-on-qemu-in-virtualbox.html > was my early motivation for doing this.) > > FWIW#2, the actual console output during a failed boot: [...] Content analysis details: (-2.9 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: freebsd-emulation@freebsd.org, freebsd-arm@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 24 Nov 2012 04:20:49 -0000 On 11/23/2012 1:29 PM, grenville armitage wrote: > All, > > Apologies if I have the wrong lists, feel free to redirect me. > > I recently decided to try getting an arm build of 10.0-CURRENT > (r243319) (TARGET=arm KERNCONF=GUMSTIX-QEMU) running inside a > Qemu-emulated Gumstix Verdex board, using qemu-devel (1.1.1) as the > emulator. > > Short version: I fire up qemu-system-arm with "-m 768" to make sure > there's enough virtual RAM. u-boot reports the emulated Verdex board > as having 256MB of DRAM (I believe this limit is imposed by u-boot). > But when control passes to FreeBSD the kernel prints the usual > copyright messages, detects the CPU type ("PXA27x step C-0 (XScale > core)"), auto-detects 512MB of real memory rather than 256MB and > promptly panics (with "panic: vm_page_insert: page already inserted"). > > The problem appears to be FreeBSD auto-detecting twice the emulated > available RAM. Does this ring any bells with anyone? My google-fu has > so far failed me. > > (I've been contemplating trying this for awhile, since noticing > sys/arm/conf/GUMSTIX-QEMU was added to head earlier this year. > Admittedly GUMSTIX-QEMU relies on GUMSTIX, which notes it is for the > Basix and Connex boards. So I recognise that the answer when emulating > Verdex boards might simply be "don't do that".) > > FWIW, this is a side project to get an emulated ARM environment > running on my amd64 box for building ARM Ports. I've also tried > booting the same kernel using Qemu's emulation of the Gumstix Connex > board -- this does seem to work, but the emulated 64MB RAM is too > tight. > (http://matrossi.blogspot.com.au/2011/09/freebsd-arm-on-qemu-in-virtualbox.html > was my early motivation for doing this.) > > FWIW#2, the actual console output during a failed boot: AFAIU you can't specify just any memory size for PXA2XX-based boards since they've got strict SDRAM configuration format. From quick glance it seems that FreeBSD's SDRAM size detection code thinks that there are 4 banks of 128Mb. While the same MDCNFG register value(0x8ad30ad3) is used in U-Boot source to indicate 256Mb memory size. So I assume our code is broken for PXA270. If anybody got a datasheet for it - please take a look, or send datasheet my way.